CN115224191A - Ferroelectric superlattice multi-value memory device and manufacturing method thereof - Google Patents
Ferroelectric superlattice multi-value memory device and manufacturing method thereof Download PDFInfo
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- 229910052582 BN Inorganic materials 0.000 claims description 3
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 3
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- 229910021393 carbon nanotube Inorganic materials 0.000 claims description 3
- KQHQLIAOAVMAOW-UHFFFAOYSA-N hafnium(4+) oxygen(2-) zirconium(4+) Chemical compound [O--].[O--].[O--].[O--].[Zr+4].[Hf+4] KQHQLIAOAVMAOW-UHFFFAOYSA-N 0.000 claims description 3
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/253—Multistable switching devices, e.g. memristors having three or more electrodes, e.g. transistor-like devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8822—Sulfides, e.g. CuS
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8836—Complex metal oxides, e.g. perovskites, spinels
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Abstract
The invention discloses a ferroelectric superlattice multivalued memory and a manufacturing method thereof, comprising a substrate, wherein a source electrode, a drain electrode and a grid window consisting of the source electrode and the drain electrode are arranged on the substrate; the gate window is provided with a ferroelectric superlattice structure, the ferroelectric superlattice structure consists of a plurality of ferroelectric layers and a channel layer, and a source electrode and a drain electrode are in end-type contact with the ferroelectric superlattice structure; the ferroelectric superlattice structure is provided with a gate dielectric layer, and the gate dielectric layer is provided with a gate. The invention realizes the multi-valued memory by adopting the two-dimensional ferroelectric superlattice, improves the data operation efficiency, further realizes the high-density storage of the data, and has wide application prospect.
Description
Technical Field
The present invention relates to a ferroelectric superlattice memory device, and more particularly, to a ferroelectric superlattice multi-valued memory device and a method for fabricating the same.
Background
And multi-value storage can store multi-value values, so that the adjustment range of weight parameters in a weight matrix network is enlarged, complex calculation can be conveniently realized in an artificial neural network, and a non-Von architecture storage and calculation integrated bottom hardware unit is realized. Molybdenum sulfide (MoS) due to two-dimensional transition metal dihalide compounds (TMDs) having dangling bond-free, atomic-scale thickness, excellent electrostatic control ability 2 ) As a typical representative, it has a suitable band gap (1.2 eV for a single layer) and a high on-off ratio (I) ON /I OFF ≈10 8 ) The method is convenient for scaling down and integration of the device size, and is a powerful choice for low-power-consumption storage and logic circuits.
The greatest advantage of ferroelectric storage over Flash (industry) is three orders of magnitude speed improvement. The ferroelectric memory has the following advantages: (1) High speed erase-write (nanosecond level), non-destructive read (2) endurance (over 10 years), high reliability (polarization stability), low power consumption, and convenience for high density integration. At present, the storage capacity and the integration level of the ferroelectric memory are not high, and the storage capacity and the integration level of the ferroelectric memory cannot reach a commercial level which is comparable with a Flash memory. The structure function is single, and only low-capacity data can be stored; and at present, a single device of the ferroelectric memory can only store one-bit binary data and can not realize multi-value storage.
Disclosure of Invention
The embodiment of the invention provides a multi-value memory realized by adopting a two-dimensional ferroelectric superlattice. The first aspect of the invention provides a ferroelectric superlattice multivalued memory device:
the semiconductor device comprises a substrate, a source electrode, a drain electrode and a gate window consisting of the source electrode and the drain electrode, wherein the substrate is provided with the source electrode and the drain electrode;
the gate window is provided with a ferroelectric superlattice structure, the ferroelectric superlattice structure consists of a plurality of ferroelectric layers and a channel layer, and the source electrode and the drain electrode are in end contact with the ferroelectric superlattice structure;
the ferroelectric superlattice structure is provided with a gate dielectric layer, and the gate dielectric layer is provided with a gate.
In an embodiment of the first aspect of the present invention, the ferroelectric layer is selected from copper indium thiophosphate (CIPS) or Hafnium Zirconium Oxide (HZO).
In an embodiment of the first aspect of the present invention, the above-mentioned channel layer is selected from molybdenum sulfide or carbon nanotubes.
In an embodiment of the first aspect of the present invention, the gate dielectric layer is selected from SiO 2 、Si 3 N 4 、HfO 2 Or hexagonal boron nitride.
In a second aspect, the present invention provides a method for manufacturing a ferroelectric superlattice multivalued memory device, comprising the following steps: providing a substrate, and growing a ferroelectric superlattice structure on the substrate;
patterning the ferroelectric superlattice structure to define an active region;
forming a source electrode and a drain electrode on two sides of the active region respectively;
and forming a high-k gate oxide layer and a gate electrode above the active region.
In an embodiment of the second aspect of the present invention, the above-described ferroelectric superlattice structure is formed by alternately growing the channel layer and the ferroelectric layer a plurality of times.
In an embodiment of the second aspect of the invention, the above-described channel layer is formed by growing 1-5 layers of molybdenum sulfide by CVD, ALD or MBE.
In an embodiment of the second aspect of the invention, the ferroelectric layer is formed by growing 1-20nm of copper indium thiophosphate (CIPS) by CVD, ALD or MBE.
In an embodiment of the second aspect of the invention, a 1-10nm high-k gate dielectric layer is grown by ALD.
In an embodiment of the second aspect of the present invention, the source electrode and the drain electrode are formed by PVD.
The invention realizes a multi-value memory by a two-dimensional ferroelectric superlattice structure, improves the data operation efficiency and further realizes the high-density storage of data; and may also serve as the underlying unit in a computationally integrated neural network.
Drawings
The invention may be better understood from the following description of specific embodiments of the invention taken in conjunction with the accompanying drawings, in which like reference numerals identify like or similar features.
FIG. 1 is a schematic view of a ferroelectric superlattice multivalued memory in accordance with an embodiment of the present invention;
FIG. 2 is a graph showing the transfer characteristics of a ferroelectric superlattice multivalued memory in accordance with an embodiment of the present invention;
FIG. 3 is a schematic diagram of a ferroelectric superlattice multivalued memory in accordance with an embodiment of the present invention;
FIG. 4 illustrates the formation of a ferroelectric superlattice structure and a silicon nitride layer on a substrate;
FIG. 5 is a drawing of an active area defined by photolithography and ICP etching;
FIG. 6 illustrates the formation of a source drain metal layer;
FIG. 7 illustrates the formation of a silicon oxide layer;
FIG. 8 is a CMP silicon oxide layer;
fig. 9 is a view showing the removal of silicon nitride to expose the ferroelectric superlattice active layer;
FIG. 10 is a high-k gate dielectric layer;
FIG. 11 is a gate patterned by photolithography;
FIG. 12 illustrates the formation of a silicon nitride mask layer;
FIG. 13 illustrates the formation of patterned tungsten pillars and the completion of peripheral connections;
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Like elements in the drawings are represented by like reference numerals, and parts of the drawings are not drawn to scale. Moreover, certain well-known elements may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.
It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly above another layer, another region, the expression "a directly above B" or "a above and adjacent to B" will be used herein. In the present application, "a is directly in B" means that a is in B and a and B are directly adjacent, rather than a being in a doped region formed in B.
Fig. 1 is a schematic view of a ferroelectric superlattice multivalued memory in accordance with an embodiment of the present invention. As can be seen, there is a substrate (not shown) on which there are source 1, drain 2 and a gate window consisting of source 1 and drain 2; having ferroelectric super-capacitor in gate windowA lattice structure, a ferroelectric superlattice structure consisting of a multi-layer channel layer 3 and a ferroelectric layer 4, wherein the channel layer 3 may be selected from molybdenum sulfide (MoS) or carbon nanotubes, in this embodiment molybdenum sulfide (MoS) is used 2 ) As a channel layer. Wherein the ferroelectric layer is selected from copper indium thiophosphate (CIPS) or Hafnium Zirconium Oxide (HZO), copper indium thiophosphate (CIPS) is used as the ferroelectric layer in this embodiment. MoS with at least 3 periods of ferroelectric superlattice 2 the/CIPS structure, in this example, takes 3 cycles. Generally, the metal-to-semiconductor Contact is divided into a Side-Contact (Side-Contact) and an End-Contact (End-Contact), the metal electrode of the Side-Contact is parallel to the semiconductor material, and the metal electrode of the End-Contact is perpendicular to the semiconductor material. The source electrode 1 and the drain electrode 2 are in end-to-end contact with the ferroelectric superlattice structure. The source and drain metal can be Ti, pd, au, tiN, etc. A high-k gate dielectric layer 5 and a gate electrode 6 are formed on the ferroelectric superlattice structure, wherein the high-k gate dielectric layer 5 may be any high-k dielectric, and may be selected from SiO, for example 2 、Si 3 N 4 、HfO 2 Or hexagonal boron nitride (h-bn), which is used in this embodiment. The gate electrode 6 may be a Ti or Au electrode.
By applying voltage to the grid of the ferroelectric superlattice multi-valued memory provided by the embodiment of the invention, the CIPS ferroelectric materials with different layers are subjected to polarization inversion, and MoS is subjected to different pairing pairs 2 The more inversion layers, the larger the conduction current or conductance value, thereby realizing multi-value storage. The operation principle of the ferroelectric superlattice multivalue memory according to the embodiment of the invention is described in detail by taking an NMOS device with three-layer channels as an example in conjunction with fig. 2 and 3. Fig. 2 is a schematic diagram of electrical characteristics of the multi-value memory of the present device, with the abscissa representing the gate voltage applied to the device and the ordinate representing the drain current. Fig. 3-a to 3-g show the working principle of data writing and data erasing in the embodiment of the present invention in detail, wherein fig. 3-a is the initial state of the device, assuming that the CIPS initial polarization direction of the ferroelectric layer is all upward, since no voltage is applied to the gate, the molybdenum sulfide trilayer is a depletion layer, the device is off, the current is "0", and no data is written, corresponding to the curve state (1) in fig. 2. When data is written, e.g.As shown in FIG. 3-b, when a small positive voltage is applied to the gate, the field strength is sufficient to turn the top CIPS only and thus only up to the corresponding lower MoS 2 Forming an inversion layer, writing a copy of data "1", corresponding to curve state (2) in fig. 2; as shown in FIG. 3-c, when the positive voltage is applied to the gate, the electric field strength causes the two-layer CIPS to flip, thereby achieving MoS corresponding to the two layers 2 An inversion layer is formed and data "2" is written, and the current rises to "2", corresponding to the curve state (3) in fig. 2. As shown in FIG. 3-d, as the positive voltage is further applied to the gate, eventually all CIPS polarizations are reversed, corresponding to all layers MoS 2 An inversion layer is formed, data "3" is written, and the current rises to "3", corresponding to curve state (4) in fig. 2, and the memory space is full. When data erasure is performed, it is assumed that the initial state memory storage space is full and the stored data is "3", as shown in fig. 3-d, on which basis data erasure is performed. As shown in FIG. 3-e, by applying a small negative voltage to the gate, the field strength is sufficient to flip the CIPS at the uppermost layer and only reach the MoS corresponding to the lower layer 2 A depletion layer is formed and after partial erasure, the data becomes "2", corresponding to the curve state (5) in fig. 2. As shown in FIG. 3-f, when the negative voltage is applied to the gate, the electric field strength is reversed for two layers of CIPS, and the MoS corresponding to the lower layer is reached 2 A depletion layer is formed and the data becomes "1" after erasure, corresponding to the curve state (6) in fig. 2. As further shown in FIG. 3-g, when the negative voltage on the gate is sufficiently large, the electric field strength is sufficient to cause all CIPS polarizations to flip, thereby achieving all MoS 2 A depletion layer is formed, data is completely erased, the current is reduced to 0, and the initial curve state (7) is returned.
In another embodiment of the present invention, the process steps of the ferroelectric superlattice multi-level memory of the present invention are described as shown in fig. 4-13. First, as shown in fig. 4, a wafer 101 is provided as a substrate, which may be sapphire, silicon oxide, silicon nitride, or the like, and in this embodiment, a silicon oxide substrate is used. Then about 1-5 layers of molybdenum sulfide (MoS) are grown on the wafer 101 by chemical vapor deposition 2 ) Channel layer 102, in other embodiments, may also be formed by Atomic Layer Deposition (ALD) or depositionAnd growing the molybdenum sulfide channel layer by using electron beam epitaxy (MBE). A 1-20nm copper indium thiophosphate (CIPS) ferroelectric layer 103 is then further grown on the molybdenum sulfide channel layer by Chemical Vapor Deposition (CVD), which in other embodiments may also be grown by Atomic Layer Deposition (ALD) or Molecular Beam Epitaxy (MBE). A ferroelectric superlattice structure is formed by alternately growing the above molybdenum sulfide channel layer 102 and copper indium thiophosphate (CIPS) ferroelectric layer 103 a plurality of times. In this embodiment, the molybdenum sulfide channel layer 102 and the copper indium thiophosphate (CIPS) ferroelectric layer 103 are 3 layers. A silicon nitride layer 104 is then deposited by chemical vapor deposition or plasma chemical vapor deposition on the ferroelectric superlattice structure.
As further shown in fig. 5, the silicon nitride layer 104 is patterned by photolithography to define active regions, and then the ferroelectric superlattice is IPC etched using the silicon nitride as a mask to form the active regions. Subsequently, as shown in fig. 6, a source/drain contact metal layer 105 is deposited on the active region by PVD, in this embodiment, ti is used as the source/drain contact metal, and in other embodiments, pd, au, tiN, or other metals may be used. A silicon oxide layer 106 is further deposited by CVD on the source drain contact metal layer 105 and thermally annealed to improve the tip contact of the source drain metal. The silicon oxide 106 is then CMP processed to expose the silicon nitride layer 104 on top of the active layer, and then the silicon nitride layer 104 is removed with hot phosphoric acid to expose the ferroelectric superlattice structure. A high-k gate dielectric layer 107 of 1-10nm is further deposited on the above structure by ALD, in this embodiment, the high-k gate dielectric layer 107 is hafnium oxide, and in other embodiments, aluminum oxide, silicon nitride, etc. may be used as the high-k gate dielectric layer. Then, the high-k gate dielectric layer 107 is further patterned by photolithography, and a metal gate 108 is formed on the high-k gate dielectric layer 107 by a metal deposition + etching patterning process, where the metal gate 108 is a Ti metal gate in this embodiment.
Further, a silicon nitride mask layer 109 is formed on the structure formed in the above step by CVD or PECVD, and a via hole pattern is defined, then a connection via hole is etched by ICP, a tungsten pillar 110 is formed in the via hole by sputtering by PVD, and a peripheral connection line is completed, thereby forming the ferroelectric superlattice multi-value memory according to the embodiment of the present invention.
The manufacturing process of the ferroelectric superlattice multivalue memory in the embodiment of the invention is compatible with the traditional integrated circuit process, and meanwhile, the ferroelectric material and the channel material required in the superlattice structure can grow in a CVD/ALD/MBE mode, thereby being convenient for device integration and large-scale production. The silicon oxide mask of CVD in the process is beneficial to protecting end-type core contact metal and maintaining the stability of a superlattice structure in the device manufacturing process.
Although the invention has been described in detail with respect to specific embodiments thereof, it will be apparent to those skilled in the art that the invention is susceptible to modification or alteration. Accordingly, it is intended that all such modifications and alterations be included within the scope of this invention as defined in the appended claims.
Claims (10)
1. A ferroelectric superlattice multivalued memory device, characterized in that:
the transistor comprises a substrate, a source electrode, a drain electrode and a grid window consisting of the source electrode and the drain electrode, wherein the substrate is provided with the source electrode and the drain electrode;
the gate window is provided with a ferroelectric superlattice structure, the ferroelectric superlattice structure consists of a plurality of ferroelectric layers and a channel layer, and the source electrode and the drain electrode are in end-type contact with the ferroelectric superlattice structure;
the ferroelectric superlattice structure is provided with a gate dielectric layer, and the gate dielectric layer is provided with a gate.
2. A ferroelectric superlattice multivalued memory device as recited in claim 1, wherein said ferroelectric layer is selected from copper indium thiophosphate (CIPS) or Hafnium Zirconium Oxide (HZO).
3. A ferroelectric superlattice multivalued memory device as recited in claim 1, wherein said channel layer is selected from molybdenum sulfide or carbon nanotubes.
4. A ferroelectric superlattice multivalued memory device as recited in claim 1, wherein said gate dielectric layer is selected from the group consisting of SiO 2 、Si 3 N 4 、HfO 2 Or hexagonal boron nitride.
5. A method of fabricating a ferroelectric superlattice multivalued memory device as claimed in any one of claims 1-4, characterized by comprising the steps of:
providing a substrate, and growing a ferroelectric superlattice structure on the substrate;
patterning the ferroelectric superlattice structure to define an active region;
forming a source electrode and a drain electrode on two sides of the active region respectively;
and forming a high-k gate dielectric layer and a gate above the active region.
6. A method of fabricating a ferroelectric superlattice multivalued memory device as claimed in claim 5, wherein said ferroelectric superlattice structure is formed by alternately growing a channel layer and a ferroelectric layer a plurality of times.
7. A method of fabricating a ferroelectric superlattice multi-value memory device as in claim 6, wherein said channel layer is formed by growing 1-5 layers of molybdenum sulfide by CVD, ALD or MBE.
8. A method of fabricating a ferroelectric superlattice multivalued memory device as claimed in claim 6, wherein said ferroelectric layer is formed by growing 1-20nm copper indium thiophosphate (CIPS) by CVD, ALD or MBE.
9. A method of fabricating a ferroelectric superlattice multivalued memory device as in claim 5, wherein a 1-10nm high-k gate dielectric layer is grown by ALD.
10. A method of fabricating a ferroelectric superlattice multivalued memory device as claimed in claim 5, wherein said source electrode and said drain electrode are formed by PVD.
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08274195A (en) * | 1995-03-30 | 1996-10-18 | Mitsubishi Chem Corp | Ferroelectric fet element |
| US9685215B1 (en) * | 2016-04-01 | 2017-06-20 | SK Hynix Inc. | Semiconductor memory device including a ferroelectric layer |
| CN106910776A (en) * | 2017-04-10 | 2017-06-30 | 温州大学 | Large area molybdenum bisuphide field-effect transistor and its preparation based on high-k gate dielectric |
| CN108878642A (en) * | 2018-06-28 | 2018-11-23 | 上海电力学院 | A kind of organic ferromagnetic material superlattices memory cell of two-dimensional material-and its preparation |
| KR20180134124A (en) * | 2017-06-08 | 2018-12-18 | 에스케이하이닉스 주식회사 | Ferroelectric Memory Device |
| US20200303417A1 (en) * | 2019-03-18 | 2020-09-24 | Mitsubishi Electric Research Laboratories, Inc. | Low Power 2D Memory Transistor for Flexible Electronics and the Fabrication Methods Thereof |
| CN111755447A (en) * | 2020-07-13 | 2020-10-09 | 湘潭大学 | High-density ferroelectric memory unit based on multiple logic states and regulation and control method thereof |
| KR102321010B1 (en) * | 2020-05-18 | 2021-11-03 | 충북대학교 산학협력단 | Synapse device and fabrication method of the same |
| CN113948635A (en) * | 2021-09-10 | 2022-01-18 | 山东师范大学 | Ferroelectric tunnel junction memristor with high tunnel resistance and preparation method and application thereof |
| CN114093927A (en) * | 2021-11-11 | 2022-02-25 | 西安电子科技大学杭州研究院 | Complementary field effect transistor based on ferroelectric doping and manufacturing method thereof |
-
2022
- 2022-07-01 CN CN202210765689.1A patent/CN115224191B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08274195A (en) * | 1995-03-30 | 1996-10-18 | Mitsubishi Chem Corp | Ferroelectric fet element |
| US9685215B1 (en) * | 2016-04-01 | 2017-06-20 | SK Hynix Inc. | Semiconductor memory device including a ferroelectric layer |
| CN106910776A (en) * | 2017-04-10 | 2017-06-30 | 温州大学 | Large area molybdenum bisuphide field-effect transistor and its preparation based on high-k gate dielectric |
| KR20180134124A (en) * | 2017-06-08 | 2018-12-18 | 에스케이하이닉스 주식회사 | Ferroelectric Memory Device |
| CN108878642A (en) * | 2018-06-28 | 2018-11-23 | 上海电力学院 | A kind of organic ferromagnetic material superlattices memory cell of two-dimensional material-and its preparation |
| US20200303417A1 (en) * | 2019-03-18 | 2020-09-24 | Mitsubishi Electric Research Laboratories, Inc. | Low Power 2D Memory Transistor for Flexible Electronics and the Fabrication Methods Thereof |
| KR102321010B1 (en) * | 2020-05-18 | 2021-11-03 | 충북대학교 산학협력단 | Synapse device and fabrication method of the same |
| CN111755447A (en) * | 2020-07-13 | 2020-10-09 | 湘潭大学 | High-density ferroelectric memory unit based on multiple logic states and regulation and control method thereof |
| CN113948635A (en) * | 2021-09-10 | 2022-01-18 | 山东师范大学 | Ferroelectric tunnel junction memristor with high tunnel resistance and preparation method and application thereof |
| CN114093927A (en) * | 2021-11-11 | 2022-02-25 | 西安电子科技大学杭州研究院 | Complementary field effect transistor based on ferroelectric doping and manufacturing method thereof |
Non-Patent Citations (2)
| Title |
|---|
| LI T, SHARMA P, LIPATOV A, ET AL.: "Polarization-mediated modulation of electronic and transport properties of hybrid MoS2–BaTiO3–SrRuO3 tunnel junctions", 《NANO LETTERS》, vol. 17, no. 2, 17 January 2017 (2017-01-17), pages 5 * |
| YANG K, WANG S, HAN T, ET AL.: "Low-power OR logic ferroelectric in-situ transistor based on a CuInP2S6/MoS2 van der Waals heterojunction", 《NANOMATERIALS》, vol. 11, no. 8, 31 July 2021 (2021-07-31) * |
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