CN115224105A - Fast recovery diode and manufacturing method and application thereof - Google Patents
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Abstract
The application provides a fast recovery diode and a manufacturing method and application thereof. The fast recovery diode comprises a substrate, wherein a P + stop ring area and a P type active area are respectively arranged on two opposite sides of the surface of the substrate, a P + field limiting ring area and a main junction area are also arranged on the surface of the substrate between the P + stop ring area and the P type active area, and the P + field limiting ring area and the main junction area are sequentially arranged along the direction of the P + stop ring area pointing to the P type active area; the P-type active region comprises a P-body region doped with low ion concentration and a shallow P + region doped with high ion concentration, and the P-body region and the shallow P + region are sequentially arranged along the direction of the P + stop ring region pointing to the P-type active region; wherein, the junction depth and the carrier concentration of the P-body region are different from those of the P + field limiting ring region and the P + stop ring region. In the application, voltage drop is generated between the P-body region and the P + field limiting ring region, and simultaneously, because the P-body region is doped with low ion concentration, the width of a depletion region of the main region close to one side of the P-body region can be expanded, so that the voltage resistance of the fast recovery diode is effectively improved.
Description
[ technical field ] A method for producing a semiconductor device
The application relates to the technical field of power electronic devices, in particular to a fast recovery diode and a manufacturing method and application thereof.
[ background of the invention ]
In the related art, the lifetime of a conventional Fast Recovery Diode (FRD) is controlled mainly by doping with a heavy metal (such as a nickel-platinum alloy) or by electron irradiation, that is, by reducing the lifetime of minority carriers in a chip, the minority carriers of the FRD can be rapidly extracted and recombined during reverse recovery, thereby reducing the reverse recovery time of the FRD; however, if the reverse recovery time of the FRD is further reduced to a range of several tens of nanoseconds, the concentration of recombination centers introduced into the chip must be increased, which brings risks of large leakage, poor reliability, and the like to the FRD, and degrades the performance of the FRD. In addition, the doping of metal can cause the voltage drop of the FRD to have the characteristic of negative temperature coefficient, which is not favorable for the parallel use of the FRD and the insulated gate bipolar transistor. In addition, conventional FRD has many disadvantages, such as: the fringing electric field of the FRD terminal is concentrated, so that the withstand voltage of the FRD is reduced, the electric leakage is increased, the performance of the FRD is deteriorated or broken down, and further the FRD fails, and at the moment, a protection technology needs to be adopted at the FRD terminal to achieve the purposes of reducing the surface electric field strength of the fringing terminal of the FRD and improving the withstand voltage level of the FRD; the reverse recovery time of the FRD is a main factor influencing the turn-off loss of the FRD, and the forward conduction voltage drop is a main factor influencing the turn-on loss of the FRD, so that the contradiction between the improvement of the reverse recovery time of the FRD and the reduction of the forward conduction voltage drop of the FRD is mutually realized; the recovery softness of the FRD is directly related to the peak current of the FRD, namely the harder the recovery characteristic of the FRD is, the larger the peak current is, so that the FRD is subjected to overlarge power consumption, and the performance degradation or the service life of the FRD is reduced; the FRD is easy to generate instantaneous current mutation in the reverse recovery process, so that the FRD is easy to burn due to overload.
Therefore, there is a need for an improved structure of the fast recovery diode.
[ summary of the invention ]
The application provides a fast recovery diode and a manufacturing method and application thereof, and aims to solve the problems of voltage resistance, current transient, parallel application and the like of the fast recovery diode in the related technology.
In order to solve the above technical problem, a first aspect of the embodiments of the present application provides a fast recovery diode, including a substrate, where P + stop ring regions and P-type active regions are respectively disposed on two opposite sides of a surface of the substrate, a P + field limiting ring region and a main junction region are further disposed on the surface of the substrate at a position between the P + stop ring regions and the P-type active regions, and the P + field limiting ring region and the main junction region are sequentially disposed along a direction in which the P + stop ring region points to the P-type active region;
the P-type active region comprises a P-body region doped with low ion concentration and a shallow P + region doped with high ion concentration, and the P-body region and the shallow P + region are sequentially arranged along the direction of the P + stop ring region pointing to the P-type active region; wherein the junction depth and the carrier concentration of the P-body region are different from those of the P + field limiting ring region and the P + stop ring region.
A second aspect of the embodiments of the present application provides a method for manufacturing a fast recovery diode, including:
injecting and forming a P + stop ring region and a P + field limiting ring region on the surface of the substrate; the surface of the substrate is provided with a first side and a second side opposite to the first side, the P + stop ring area and the P + field limiting ring area are both positioned on the first side, and the P + stop ring area and the P + field limiting ring area are sequentially arranged along the direction from the first side to the second side;
implanting to form a main junction region and a low ion concentration doped P-body region on the surface of the substrate; the P-body region is located on the second side, the main region is arranged adjacent to the P-body region and located between the P-body region and the P + field limiting ring region, and the junction depth and the carrier concentration of the P-body region are different from those of the P + field limiting ring region and the P + stop ring region;
implanting a shallow P + region doped with high ion concentration on the surface of the substrate; the shallow P + region is arranged adjacent to the P-body region and is positioned on one side of the P-body region far away from the main region.
A third aspect of embodiments of the present application provides a use of the fast recovery diode according to the first aspect of embodiments of the present application in a power electronic device.
As can be seen from the above description, the present application has the following advantages compared with the related art:
the substrate, the P + stop ring region, the P + field limiting ring region, the main junction region, the P-body region doped with low ion concentration and the shallow P + region doped with high ion concentration form the fast recovery diode, and the junction depth and the carrier concentration of the P-body region are set to be different from those of the P + field limiting ring region and the P + stop ring region, namely the P-body region, the P + field limiting ring region and the P + stop ring region are formed in different process steps. It can be understood that the active region and the field limiting ring region in the conventional FRD are formed in the same process step, which results in the same junction depth and carrier concentration between the active region and the field limiting ring region in the conventional FRD, i.e. there is no longitudinal electric field (or that is, no potential difference) between the active region and the field limiting ring region in the conventional FRD, thereby resulting in no voltage drop between the active region and the field limiting ring region in the conventional FRD, whereas the junction depth and carrier concentration of the P-body region in the present application are different from those of the P + field limiting ring region, and therefore there is a longitudinal electric field (or that is, a potential difference) between the P-body region and the P + field limiting ring region in the present application, i.e. there is a voltage drop between the P-body region and the P + field limiting ring region in the present application, and since the P-body region is doped with a low ion concentration, the width of the depletion region (i.e. the region between the main body region and the P + field limiting ring region) on the side of the main body region can be extended, thereby effectively improving the performance of the diode. Meanwhile, the manufacturing method of the shallow P + region and the local metal barrier not only inhibits the transient of reverse recovery current and enhances the recovery softness of the diode, but also enables the diode to have the positive temperature coefficient characteristic of voltage drop, eliminates the hidden danger caused by parallel use of devices and improves the reliability of the devices.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions in the related art or the embodiments of the present application, the drawings needed to be used in the description of the related art or the embodiments of the present application will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, not all embodiments, and other drawings can be obtained by those skilled in the art without inventive efforts.
FIG. 1 is a schematic diagram of a conventional FRD;
fig. 2 is a schematic structural diagram of a fast recovery diode according to an embodiment of the present disclosure;
fig. 3 is a schematic flow chart of a method for manufacturing a fast recovery diode according to an embodiment of the present disclosure.
[ detailed description ] A
In order to make the objects, technical solutions and advantages of the present application more apparent and understandable, the present application will be clearly and completely described below in conjunction with the embodiments of the present application and the corresponding drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. It should be understood that the embodiments of the present application described below are only for explaining the present application and are not intended to limit the present application, that is, all other embodiments obtained by a person of ordinary skill in the art without making creative efforts based on the embodiments of the present application belong to the protection scope of the present application. In addition, the technical features involved in the embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
In power electronic devices, insulated Gate Bipolar Transistors (IGBTs) are widely used, and Fast Recovery Diodes (FRDs) used in parallel with the IGBTs also have a great development prospect. FRD is a semiconductor diode having advantages of good switching characteristics and short reverse recovery time, and is mainly applied to electronic circuits such as electric vehicles, traction locomotives, switching power supplies, PWM (Pulse Width Modulation) Pulse Width modulators and frequency converters, and is used as a high-frequency rectifier diode, a freewheeling diode, or a damping diode. The internal structure of the FRD is different from that of a common PN junction diode, the FRD has the characteristics of P-I-N (namely, a base region I is added between a P-type silicon material and an N-type silicon material to form a PIN silicon wafer), and the relationship among recovery time, recovery charge and forward voltage drop is achieved by adjusting minority carriers. With the continuous improvement and progress of power electronic technology, although the application field of the FRD is expanded, higher requirements are provided for the frequency response, the switching loss, the reliability and the like of the FRD.
In the related art, referring to fig. 1, fig. 1 is a schematic structural diagram of a conventional FRD. The conventional FRD generally includes a substrate 1', an epitaxial layer 2', a field limiting ring region 3', a stop ring region 4' and an emitter region 5', and the lifetime of the conventional FRD is controlled mainly by doping with a heavy metal (such as nickel-platinum alloy) or by electron irradiation, that is, by reducing the lifetime of minority carriers in a chip, the minority carriers of the FRD can be rapidly extracted and recombined during reverse recovery, thereby reducing the reverse recovery time of the FRD; however, if the reverse recovery time of the FRD is further reduced to a range of several tens of nanoseconds, the concentration of recombination centers introduced into the chip must be increased, which brings risks of large leakage, poor reliability, and the like to the FRD, and degrades the performance of the FRD. In addition, conventional FRD has many drawbacks, such as: the fringing electric field of the FRD terminal is concentrated, so that the withstand voltage of the FRD is reduced, the electric leakage is increased, the functional characteristic of the FRD is deteriorated or broken down, and further the FRD fails, and at the moment, a protection technology needs to be adopted at the FRD terminal to achieve the purposes of reducing the surface electric field strength of the fringing terminal of the FRD and improving the withstand voltage level of the FRD; the reverse recovery time of the FRD is a main factor influencing the turn-off loss of the FRD, and the forward conduction voltage drop is a main factor influencing the turn-on loss of the FRD, so that the contradiction between the improvement of the reverse recovery time of the FRD and the reduction of the forward conduction voltage drop of the FRD is mutually realized; the recovery softness of the FRD is directly related to the peak current thereof, that is, the harder the recovery characteristic of the FRD is, the larger the peak current thereof is, thereby causing the FRD to suffer from excessive power consumption, and further causing performance degradation or reduction in service life of the FRD; the FRD is easy to generate instantaneous current mutation in the reverse recovery process, so that the FRD is easy to burn due to overload. To this end, embodiments of the present application provide a fast recovery diode, which may be applied to various power electronic devices, such as electric vehicles, traction locomotives, switching power supplies, PWM pulse width modulators, frequency converters, and the like.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a fast recovery diode according to an embodiment of the present disclosure. The fast recovery diode provided by the embodiment of the application comprises a substrate 10, a P + stop ring area 20 and a P type active area 30 are respectively arranged on two opposite sides of the surface of the substrate 10, a P + field limiting ring area 40 and a main junction area 50 are further arranged on the surface of the substrate 10 between the P + stop ring area 20 and the P type active area 30, and the P + field limiting ring area 40 and the main junction area 50 are sequentially arranged along the direction of the P + stop ring area 20 pointing to the P type active area 30. Specifically, the P-type active region 30 includes a P-body region 31 doped with low ion concentration and a shallow P + region 32 doped with high ion concentration, the P-body region 31 and the shallow P + region 32 are sequentially disposed along the P + stop ring region 20 in a direction pointing to the P-type active region 30; the junction depth and the carrier concentration of the P-body region 31 are different from those of the P + field limiting ring region 40 and the P + stop ring region 20.
In the embodiment of the present application, the substrate 10, the P + stop ring region 20, the P + field limiting ring region 40, the main junction region 50, the P-body region 31 doped with low ion concentration and the shallow P + region 32 doped with high ion concentration together form a fast recovery diode, and the junction depth and the carrier concentration of the P-body region 31 are set to be different from those of the P + field limiting ring region 40 and the P + stop ring region 20, that is, the P-body region 31, the P + field limiting ring region 40 and the P + stop ring region 20 are formed in different process steps. It is understood that the active region (i.e., the emitter region 5' in fig. 1) and the field limiting ring region 3' in the conventional FRD are formed in the same process step, which results in the same junction depth and carrier concentration between the active region and the field limiting ring region 3' in the conventional FRD, i.e., there is no longitudinal electric field (or no potential difference) between the active region and the field limiting ring region 3' in the conventional FRD, resulting in no voltage drop between the active region and the field limiting ring region 3' in the conventional FRD, whereas the junction depth and carrier concentration of the P-body region 31 in the present embodiment are different from those of the P + field limiting ring region 40, and thus there is a longitudinal electric field (or a potential difference may be formed) between the P-body region 31 and the P + field limiting ring region 40 in the present embodiment, i.e., there is a voltage drop between the P-body region 31 and the P + field limiting ring region 40 in the present embodiment, and since the P-body region 31 is doped with a low ion concentration, the main body region 50 is close to the P-body region 31, thus effectively expanding the width of the P-body region 50.
Still referring to fig. 2,P + field limiting ring region 40, as an embodiment, may include a plurality of P + field limiting rings 41 spaced apart from each other, the width of the P + field limiting ring region 40 in a direction pointing from the P-type active region 30 to the P + stop ring region 20 remains constant, and the distance between the plurality of P + field limiting rings 41 exhibits an increasing trend in a direction pointing from the P-type active region 30 to the P + stop ring region 20. For example, the P + field limiting ring 40 includes 5P + field limiting rings 41, the 5P + field limiting rings 41 are respectively denoted by A, B, C, D and E, and a to E are sequentially arranged along the P-type active region 30 in the direction toward the P + stop ring 20, and further denoted by AB, the distance between a and B, BC, the distance between B and C, CD, and D, and DE, the distance between D and E, so DE > CD > BC > AB.
As a specific implementation of this embodiment, the width of the P + field limiting ring region 40 in the direction from the P-type active region 30 to the P + stop ring region 20 is kept constant at 10 μm, and the distance between the plurality of P + field limiting rings 41 increases within 21 to 30 μm along the direction from the P-type active region 30 to the P + stop ring region 20. Here, still following the example given in the previous paragraph, AE (distance between A and E) is 10 μm, and AB may be 22 μm, BC may be 25 μm, CD may be 28 μm, and DE may be 30 μm.
It should be understood that this embodiment is merely a preferred implementation of the present example, which is not the only limitation on the P + field limiting ring region 40; in this regard, a person skilled in the art can flexibly set the setting according to the actual application scenario on the basis of the embodiment of the present application.
As an embodiment, still referring to fig. 2, substrate 10 may include an N + substrate layer 11, an N-type buffer layer 12, and an N-epitaxial layer 13; the N-type buffer layer 12 covers the surface of the N + substrate layer 11, and the N-epitaxial layer 13 covers the surface of the N-type buffer layer 12. It can be understood that the substrate of the conventional FRD only includes the substrate 1' and the epitaxial layer 2' in fig. 1, and does not include the N-type buffer layer 12 in this embodiment, which means that the present embodiment reduces the thickness of the epitaxial layer 2' in the conventional FRD by adding the N-type buffer layer 12, so as to reduce the forward conduction voltage drop of the fast recovery diode, i.e., reduce the conduction loss of the fast recovery diode.
As a specific implementation of the present embodiment, the thickness of the N-type buffer layer 12 may be 10 to 30 μm, and the resistivity may be 4 to 7. Omega. Cm. The thickness of the N-epitaxial layer 13 may be 70 to 120 μm, and the resistivity may be 50 to 60. Omega. Cm. It follows that N-epitaxial layer 13 is higher than N-type buffer layer 12, regardless of thickness or resistivity.
It should be understood that this embodiment is merely a preferred implementation of the examples of the present application and is not the only limitation on the substrate 10; in this regard, a person skilled in the art can flexibly set the setting according to the actual application scenario on the basis of the embodiment of the present application.
As an example, still referring to 2,P, the metal barrier 60 may be formed between the P-body regions 31 in the active region 30 of the type 5363 and the metal thickness of the metal barrier 60 may be
Of course, in the present embodiment
The embodiments of the present application are not limited to these examples, which are merely preferred.
In some embodiments, the fast recovery diode provided in the embodiments of the present application may further include other common structures disposed in the FRD in the art, such as a metal field plate 70 and a metal electrode 80 (including an anode and a cathode) covering the surface of the substrate 10 (i.e., the surface of the N-epitaxial layer 13), besides the substrate 10 (composed of the N + substrate layer 11, the N-type buffer layer 12, and the N-epitaxial layer 13), the P + stop ring region 20, the P-type active region 30 (composed of the P-body region 31 and the shallow P + region 32), the P + field stop ring region 40, and the main junction region 50, which are not listed herein.
Referring to fig. 3, fig. 3 is a schematic flow chart illustrating a method for manufacturing a fast recovery diode according to an embodiment of the present disclosure. The embodiment of the present application further provides a manufacturing method of a fast recovery diode, which is used for manufacturing the fast recovery diode provided by the embodiment of the present application, and the manufacturing method of the fast recovery diode includes the following steps 301 to 303.
In the embodiment of the present application, the surface of the substrate 10 has a first side and a second side opposite to the first side, and when manufacturing the fast recovery diode, a P + stop ring region 20 and a P + field limiting ring region 40 need to be formed by implantation on the surface of the substrate 10, the P + stop ring region 20 and the P + field limiting ring region 40 are both located on the first side of the substrate 10, and the P + stop ring region 20 and the P + field limiting ring region 40 are sequentially arranged along a direction from the first side to the second side of the substrate 10.
In the embodiment of the present invention, after the P + stop ring region 20 and the P + field limiting ring region 40 are formed on the surface of the substrate 10, a main junction region 50 and a P-body region 31 doped with low ion concentration are formed on the surface of the substrate 10 by implantation, such that the P-body region 31 is located on the second side of the substrate 10, and the main junction region 50 is disposed adjacent to the P-body region 31 and between the P-body region 31 and the P + field limiting ring region 40.
It is understood that the P-body region 31 is formed in step 302, and the P + stop ring region 20 and the P + field limiting ring region 40 are both formed in step 301, which makes the junction depth and the carrier concentration of the P-body region 31 different from those of the P + field limiting ring region 40 and the P + stop ring region 20, in order to: a longitudinal electric field (i.e., a potential difference) is formed between the P-body region 31 and the P + field limiting ring region 40, so that a voltage drop occurs between the P-body region 31 and the P + field limiting ring region 40. Meanwhile, since the P-body region 31 is doped with low ion concentration, the width of the depletion region (i.e., the region between the main region 50 and the P-body region 31) of the main region 50 near the P-body region 31 can be expanded, thereby effectively improving the voltage endurance of the fast recovery diode. In one example, the junction depth of the main region 50 and the P-body region 31 may be greater than or equal to 4 μm and less than 5 μm, and the junction depth of the P + stop ring region 20 and the P + field limiting ring region 40 may be greater than or equal to 5 μm and less than 6 μm.
In the embodiment of the present invention, after the main junction region 50 and the P-body region 31 are formed on the surface of the substrate 10 by implantation, a shallow P + region 32 doped with high ion concentration is also formed on the surface of the substrate 10 by implantation, the shallow P + region 32 is disposed adjacent to the P-body region 31, and the shallow P + region 32 is located on a side of the P-body region 31 away from the main junction region 50, and the P-body region 31 and the shallow P + region 32 together form the P-type active region 30.
In order to clearly understand the method for manufacturing the fast recovery diode provided in the embodiments of the present application, the following will help understand the method for manufacturing the fast recovery diode through a specific example, which is as follows:
1. cleaning and oxidizing the silicon chip, and performing field oxygen growth at 1100 ℃ and with the thickness of
2. After the processes of coating, photoetching and developing are finished, field oxygen to-be-etched areas of the P + stop ring area 20 and the P + field limiting ring area 40 are formed;
3. after the field oxide wet etching is finished, forming a P + stop ring area 20 and a to-be-implanted area of a P + field limiting ring area 40;
4. after photoresist removing corrosion is finished, cleaning the silicon wafer;
5. growing a pre-oxidation layer to form a P + stop ring area 20 and a masking area of a window to be injected of a P + field limiting ring area 40;
6. after the processes of gluing, photoetching and developing are finished, windows to be injected of a P + stop ring area 20 and a P + field limiting ring area 40 are formed;
7. implanting boron ions at an implant dose of 2E14/cm 2 ～5E14/cm 2 Forming a P + stop ring region 20 and a P + field limiting ring region 40 which are not activated;
8. after photoresist removing corrosion is finished, cleaning the silicon wafer;
9. corroding the pre-oxidation layer, and removing the masking regions of the windows to be injected of the P + stop ring region 20 and the P + field limiting ring region 40;
10. after the processes of gluing, photoetching and developing are finished, field oxide to-be-etched areas of the main area 50 and the P-body area 31 are formed;
11. after the field oxide wet etching is finished, forming a main junction region 50 and a region to be implanted of the P-body region 31;
12. after photoresist removing corrosion is finished, cleaning the silicon wafer;
13. growing a pre-oxidation layer to form a main junction region 50 and a masking region of a window to be implanted of the P-body region 31;
14. the implantation of boron ions is advanced, and the implantation dosage is 2E12/cm 2 ～5E11/cm 2 The temperature is T =1050 ℃, the time is 400min, and the junction depth of the P + field limiting ring region 40 and the P + stop ring region 20 is 5-5.5 μm; and a main region 50, a P-body region 31, and the junction depth of the main region 50, the P-body region 31 is 4.2-4.5 μm;
15. LPTEOS is grown to a thickness of
16. After the processes of gluing, photoetching and developing are finished, a region to be injected of the shallow P + region 32 is formed;
17. etching the dielectric layer at the lead hole to a thickness of
Forming a masking region of a window to be implanted of the shallow P + region 32;
18. implanting boron ions at an implant dose of 3E14/cm 2 ～9E14/cm 2 Forming shallow P + regions 32 that are not activated;
19. corroding and removing the residual dielectric layer when the shallow P + region 32 which is not activated is formed;
20. after photoresist removing corrosion is finished, cleaning the silicon wafer;
21. BPTEOS grown to a thickness of
22. BPTEOS reflex, the temperature is 950 ℃, and the time duration is 20-40 min;
23. after the processes of gluing, photoetching and developing are finished, forming a first lead hole;
24. BPTEOS etching to remove the oxide layer when forming the first lead hole;
25. after photoresist removing corrosion is finished, cleaning the silicon wafer;
26. deposition of nickel and platinum metal to a thickness of
27. Forming metal nickel-platinum alloy at the temperature of 450-500 ℃;
28. boiling aqua regia and cleaning silicon wafers;
29. after the processes of gluing, photoetching and developing are finished, forming a second lead hole;
30. BPTEOS etching to remove the oxide layer when forming the second lead hole;
31. after photoresist removing corrosion is finished, cleaning the silicon wafer;
32. metal wiring, depositing 3.5 μm aluminum silicon to form the leading-out terminal required by the metal electrode 80;
33. after the processes of gluing, photoetching and developing are finished, a wiring pattern is formed;
34. carrying out wet corrosion on metallized aluminum silicon to form anode metal;
35. after photoresist removing corrosion is finished, cleaning the silicon wafer;
36. PETEOS displacement of thickness
37. PESIN displacement of thickness
38. Forming a metallized alloy at the temperature of 410-450 ℃ for 30-60 min;
39. coating polyimide and photoetching polyimide to completely form a metal electrode 80;
40. curing the polyimide at high temperature, wherein the temperature is 350-400 ℃ and the time is 60min;
41. back attenuate and back metal coating by vaporization, the metal is following respectively to supreme: thickness of Ti (titanium)
Thickness of Ni (nickel)
And Ag (silver) thickness
It is understood that, in the above steps 1 to 41, steps 1 to 7 are used to form the P + stop collar 20 and the P + field limiting collar 40, steps 8 to 14 are used to form the main junction 50 and the P-body region 31, steps 15 to 19 are used to form the shallow P + region 32, and steps 20 to 41 are used to perform ion activation on the P + stop collar 20, the P + field limiting collar 40, the main junction 50, the P-body region 31 and the shallow P + region 32 that are not activated, and to form other common structures in the fast recovery diode, such as the metal electrode 80.
In summary, the embodiments of the present application provide a fast recovery diode, which adopts a device structure formed by an N-type buffer layer 12, a shallow P + region 32, a P-body region 31, a plurality of P + field limiting rings 41, a P + stop ring region 20, a main junction region 50, a substrate layer 11, an N-epitaxial layer 13, a contact metal field plate 70, and a metal electrode 80, and combines with a local metal alloying process of a cell region (i.e., a P-type active region 30), so that the fast recovery diode has a voltage withstanding requirement in reverse operation, and also has a low forward conduction voltage drop with a positive temperature coefficient, and the recovery softness of the fast recovery diode is also improved (i.e., no "hard"). In addition, in the manufacturing method, the thin dielectric layer is grown to ensure that the fast recovery diode meets the requirement of high reverse breakdown voltage, the ion implantation of the shallow P + region 32 shortens the reverse recovery time of the fast recovery diode, reduces the turn-off loss of the fast recovery diode, has good inhibition capability on the instantaneous sudden change of the reverse recovery current of the fast recovery diode, and meanwhile, the manufacturing method has the advantages of short period and low cost, and can well meet the requirement of large-scale production.
In the embodiment of the application, the photoresist is used as the masking layer, so that the local ion implantation is respectively carried out on the N-epitaxial layer 13 doped with uniform ions, and the high-temperature drive-in is carried out at the same time, and as a result, a P + stop ring region 20, a P + field limiting ring region 40, a main junction region 50, a P-body region 31 and a shallow P + region 32 are formed. Specifically, when the fast recovery diode is under reverse bias, the P-body region 31 doped with low ion concentration is beneficial to rapidly sweep out carriers, and plays roles in reducing reverse recovery charges and suppressing reverse peak current. On one hand, the P + stop ring region 20 can continue to expand the depletion region on the side of the main junction region 50 close to the P-body region 31, so that the voltage resistance of the fast recovery diode is improved; on the other hand, the electric field can be effectively terminated within the ring; on the other hand, the photoetching process is reduced, and the manufacturing cost is saved. During the reverse recovery of the fast recovery diode, a part of carriers are pumped away through the negative electrode (i.e. the cathode in the metal electrode 80), and another part of carriers slowly disappear in the form of carrier recombination at the later stage of the reverse recovery, and practice shows that during the reverse recovery of the fast recovery diode, if the recombination probability of the carriers is increased, the recovery characteristics of the fast recovery diode are improved (i.e. the conversion from "hard" to "soft").
In the fabrication process, the ion implantation step of the shallow P + region 32 is included, which results in a relatively shallow plasma level in the metal electrode 80 near the anode, so that even the high commutating di/dt produces a reverse peak current that is not very large. When the fast recovery diode performs reverse recovery, the shallow plasma layer of the buffer region (i.e. the region between the main region 50 and the P-body region 31) increases the ratio of the base region width to the minority carrier, which easily causes current transient during reverse recovery and damages the fast recovery diode, while the ion implantation process of the shallow P + region 32 can suppress the occurrence of current transient, and the steeper the gradient of ion doping, the fewer carriers implanted means that the shorter the reverse recovery time is, the smaller the turn-off loss is; in addition, the ion implantation process of the shallow P + region 32 is also beneficial to the formation of ohmic contact characteristics, so as to achieve the effect of reducing the forward conduction voltage drop, i.e., the effect of reducing the turn-on loss. In the embodiment of the present application, after the ion implantation of the shallow P + region 32 is performed, a BPSG reflow process is used to achieve the purpose of ion activation (i.e., ion activation is performed on the P + stop ring 20, the P + field limiting ring 40, the main region 50, the P-body region 31, and the shallow P + region 32 that are not activated). The embodiment of the application also adopts a polyimide coating process, utilizes the negative electricity characteristic of polyimide, inhibits the fixed charges and the movable charges of the terminal oxide layer, stabilizes the voltage withstanding characteristic of the fast recovery diode, and improves the reliability of the fast recovery diode.
Compared with the conventional FRD, the embodiment of the application has at least the following advantages: by injecting the shallow P + region 32, the reverse recovery time of the fast recovery diode is improved, and the generation of reverse recovery current transient is inhibited; under the condition of meeting the withstand voltage, the purpose of reducing the carrier recovery speed at the later stage of reverse recovery is achieved by adopting the structure of the N-type buffer layer 12, and the softness of the reverse recovery is improved to a certain extent; injecting a low-ion-concentration doped P-body region 31 and a high-ion-concentration doped shallow P + region 32, so as to reduce reverse recovery charges and inhibit reverse peak current, and improve the voltage resistance of the fast recovery diode; the ion implantation process of the shallow P + region 32 can realize the adjustment of the implantation efficiency without implantation annealing, and has simple process steps and low manufacturing cost; the P-body region 31, the P + field limiting ring region 40 and the P + stop ring region 20 are formed in different process steps, which is beneficial to the voltage-resistant characteristic of the fast recovery diode; a local metal deposition window process is introduced, and the positive temperature coefficient of the fast recovery diode drop is realized.
It should be noted that, the embodiments in the present disclosure are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. For the product class embodiment, since it is similar to the method class embodiment, the description is relatively simple, and for the relevant points, refer to the partial description of the method class embodiment.
It is further noted that, within the context of this application, relational terms such as first and second, and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined in this application may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A fast recovery diode comprises a substrate and is characterized in that a P + stop ring area and a P type active area are respectively arranged on two opposite sides of the surface of the substrate, a P + field limiting ring area and a main junction area are also arranged on the surface of the substrate between the P + stop ring area and the P type active area, and the P + field limiting ring area and the main junction area are sequentially arranged along the direction of the P + stop ring area pointing to the P type active area;
the P-type active region comprises a P-body region doped with low ion concentration and a shallow P + region doped with high ion concentration, and the P-body region and the shallow P + region are sequentially arranged along the direction of the P + stop ring region pointing to the P-type active region; and the junction depth and the carrier concentration of the P-body region are different from those of the P + field limiting ring region and the P + stop ring region.
2. The fast recovery diode of claim 1, wherein the P + field limiting ring region comprises a plurality of P + field limiting rings spaced apart from one another, the P + field limiting ring region having a constant width in a direction from the P-type active region toward the P + stop ring region, and a distance between the plurality of P + field limiting rings exhibiting an increasing trend in a direction from the P-type active region toward the P + stop ring region.
3. The fast recovery diode of claim 2, wherein a width of the P + field limiting ring region in a direction from the P-type active region toward the P + stop ring region remains constant at 10 μm, and a distance between a plurality of the P + field limiting rings increases within 21 to 30 μm in a direction from the P-type active region toward the P + stop ring region.
4. The fast recovery diode of claim 1, wherein the substrate comprises an N + substrate layer, an N-type buffer layer, and an N-epitaxial layer; the N-type buffer layer covers the surface of the N + substrate layer, and the N-epitaxial layer covers the surface of the N-type buffer layer.
5. The fast recovery diode of claim 4, wherein the N-type buffer layer has a thickness of 10 to 30 μm and a resistivity of 4 to 7 Ω -cm.
6. The fast recovery diode of claim 4, wherein the N-epitaxial layer has a thickness of 70 to 120 μm and a resistivity of 50 to 60 Ω -cm.
7. The fast recovery diode of claim 1, wherein metal barrier regions are formed between the P-body regions.
8. The fast recovery diode of claim 7, wherein the metal barrier region has a metal thickness of
9. A method for manufacturing a fast recovery diode is characterized by comprising the following steps:
injecting and forming a P + stop ring region and a P + field limiting ring region on the surface of the substrate; the surface of the substrate is provided with a first side and a second side opposite to the first side, the P + stop ring area and the P + field limiting ring area are both positioned on the first side, and the P + stop ring area and the P + field limiting ring area are sequentially arranged along the direction from the first side to the second side;
implanting a main junction region and a low-ion-concentration doped P-body region on the surface of the substrate; the P-body region is located on the second side, the main region is arranged adjacent to the P-body region and located between the P-body region and the P + field limiting ring region, and the junction depth and the carrier concentration of the P-body region are different from those of the P + field limiting ring region and the P + stop ring region;
implanting a shallow P + region doped with high ion concentration on the surface of the substrate; the shallow P + region is arranged adjacent to the P-body region and is positioned on one side of the P-body region far away from the main region.
10. Use of a fast recovery diode according to any of claims 1-8 in a power electronic device.
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| CN117577675A (en) * | 2024-01-15 | 2024-02-20 | 汉轩微电子制造(江苏)有限公司 | IGBT device embedded with FRD and manufacturing method thereof |
| CN117577675B (en) * | 2024-01-15 | 2024-04-12 | 汉轩微电子制造(江苏)有限公司 | IGBT device embedded with FRD and manufacturing method thereof |
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