CN115223505A

CN115223505A - Display device and driving method of display panel

Info

Publication number: CN115223505A
Application number: CN202210861267.4A
Authority: CN
Inventors: 吴昊; 吴薇
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2022-07-20
Filing date: 2022-07-20
Publication date: 2022-10-21

Abstract

The embodiment of the invention provides a display device and a driving method of a display panel, relates to the technical field of display, and improves the display uniformity. The display device includes a display panel and a driving circuit, the display panel including: a charging transistor connected with the first scan line and the data line; a gating circuit including a first gating transistor connected to the first clock line and a second gating transistor connected to the second clock line; the first scanning line transmits a first enabling level and a first non-enabling level, and the first enabling level jumps to the first non-enabling level to be a first jumping edge; the clock line transmits a second enabling level and a second disabling level, and the second enabling level jumps to the second disabling level to be a second jumping edge; the drive circuit is used for: when the first scanning line outputs the first enabling level, the clock line is controlled to output the second enabling level, the second enabling level is later than the second enabling level, and a second transition edge of a second clock line connected with at least part of the gating circuit is not earlier than the first transition edge.

Description

Display device and driving method of display panel

[ technical field ] A method for producing a semiconductor device

The present invention relates to the field of display technologies, and in particular, to a display device and a driving method of a display panel.

[ background of the invention ]

In order to realize normal picture display of the display panel, a plurality of data lines are arranged in the display panel, and the data lines are electrically connected with the sub-pixels and used for transmitting data voltage to the sub-pixels and charging the sub-pixels so as to drive the sub-pixels to emit light.

However, in the prior art, the charging states of different sub-pixels are different greatly, and the display uniformity of the display panel is seriously affected.

[ summary of the invention ]

In view of the above, embodiments of the present invention provide a display device and a driving method of a display panel, so as to improve the display uniformity of the display panel.

In one aspect, an embodiment of the present invention provides a display device, including a display panel and a driving circuit, where the display panel includes a plurality of sub-pixels, each of the sub-pixels includes a charging transistor, a gate of the charging transistor is electrically connected to a first scan line, and a first electrode of the charging transistor is electrically connected to a data line;

the display panel further comprises a plurality of gating circuits, wherein each gating circuit comprises at least one first gating transistor and one second gating transistor, the gate electrode of each first gating transistor is electrically connected with at least one first clock line, the gate electrode of each second gating transistor is electrically connected with a second clock line, the first poles of the at least one first gating transistor and the second gating transistor are electrically connected with a source signal line, and the second poles of the at least one first gating transistor and the second gating transistor are respectively electrically connected with a plurality of data lines;

the first scanning line is used for transmitting a first scanning signal containing a first enabling level and a first non-enabling level, and a transition edge when the first enabling level jumps to the first non-enabling level is a first transition edge; the first clock line and the second clock line are respectively used for transmitting clock signals containing a second enabling level and a second non-enabling level, and a transition edge when the second enabling level jumps to the second non-enabling level is a second transition edge;

the drive circuit is configured to: and in one frame time, when the first scanning line is controlled to output the first enable level, the first clock line and the second clock line are controlled to output the second enable level in a time sharing manner, wherein the time for the second clock line to output the second enable level is later than the time for the first clock line to output the second enable level, and the second transition edge of the clock signal output by the second clock line electrically connected with at least part of the gating circuits is not earlier than the first transition edge.

On the other hand, an embodiment of the present invention provides a driving method of a display panel, for driving the display panel, including:

and controlling the first clock line and the second clock line to output the second enable level in a time sharing manner when the first scan line is controlled to output the first enable level, wherein the second clock line outputs the second enable level later than the first clock line outputs the second enable level, and the second transition edge of the clock signal output by the second clock line electrically connected with at least part of the gating circuit is not earlier than the first transition edge.

One of the above technical solutions has the following beneficial effects:

in the embodiment of the present invention, the first enable level and the second enable level are respectively high levels, that is, the first transition edge and the second transition edge are respectively falling edges. In the embodiment of the present invention, for the charging transistor and the second gating transistor electrically connected to the same data line, since the falling edge of the second clock signal received by the second gating transistor is not earlier than the falling edge of the first scan signal, the charging transistor is turned off either synchronously when the falling edge of the second clock signal occurs or already before the falling edge of the second clock signal occurs. Therefore, the change of the data voltage on the data line caused by the falling edge of the second clock signal can not be written into the sub-pixel where the charging transistor is located through the charging transistor any more, and further the charging state of the sub-pixel can not be influenced.

Especially for the display panel with the non-rectangular shape, the change of the data voltage caused by the falling edge of the second clock signal can not be further written into the sub-pixels, so even if the length of the data line connected with the second gating transistor is short, the influence of the falling edge of the second clock signal on the data voltage can not further influence the charging state of the sub-pixels, thereby effectively weakening the difference of the luminous brightness of different sub-pixels and obviously improving the display uniformity of the display panel.

In other words, because the above technical solution can effectively improve the influence of the length difference of the data lines on the display uniformity, when the shape of the irregular display panel is designed, the limitation of the factor of the display uniformity on the appearance of the display panel can be reduced. Especially to the display device in on-vehicle field, for example on-vehicle display screen, can effectively deal with the special-shaped display panel's of on-vehicle customization demand, experience for the car owner provides the on-vehicle screen of higher end.

[ description of the drawings ]

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a top view of a prior art display panel;

FIG. 2 is a timing diagram corresponding to FIG. 1;

FIG. 3 is an equivalent diagram of a parasitic capacitor in the prior art;

FIG. 4 is a top view of a display device according to an embodiment of the present invention;

FIG. 5 is a top view of a display panel according to an embodiment of the present invention;

FIG. 6 is a timing diagram corresponding to FIGS. 4 and 5;

FIG. 7 is a schematic top view of a display panel according to an embodiment of the present invention;

FIG. 8 is a timing diagram corresponding to FIG. 7;

FIG. 9 is another timing diagram corresponding to FIGS. 4 and 5;

FIG. 10 is a partial top view of a display panel according to an embodiment of the present invention;

FIG. 11 is a timing diagram corresponding to FIG. 10;

FIG. 12 is a partial top view of a display panel according to an embodiment of the present invention;

FIG. 13 is a timing diagram corresponding to FIG. 12;

FIG. 14 is a partial top view of a display panel according to an embodiment of the present invention;

FIG. 15 is a timing diagram corresponding to FIG. 14;

FIG. 16 is a partial top view of a display panel according to an embodiment of the present invention;

FIG. 17 is a top view of another embodiment of a display panel;

FIG. 18 is a top view of the corresponding film structure of FIG. 17;

FIG. 19 is a top view of another embodiment of a display panel;

FIG. 20 is a top view of the corresponding film structure of FIG. 19;

FIG. 21 is a top view of another embodiment of a display panel;

FIG. 22 is a top view of another film structure of a display panel according to an embodiment of the present invention;

FIG. 23 is a top view of yet another film structure of a display panel in accordance with an embodiment of the present invention;

FIG. 24 is a schematic view of another structure of a sub-pixel according to an embodiment of the present invention;

fig. 25 is a timing diagram corresponding to fig. 24.

[ detailed description ] A

For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.

It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter associated objects are in an "or" relationship.

With the continuous development of display technologies, the pixel density of the display panel is higher and higher, and accordingly, the number of data lines required to be arranged in the display panel is also greatly increased.

In order to reduce the number of pins of the driver chip, in the prior art, as shown in fig. 1, fig. 1 is a top view of a display panel in the prior art, a plurality of gate circuits 101 are usually disposed in the display panel, each gate circuit 101 includes a plurality of gate transistors 102, gates of the plurality of gate transistors 102 are electrically connected to a plurality of clock signal lines CK in a one-to-one correspondence manner (for convenience of understanding, the clock signal line electrically connected to the ith gate transistor 102 is denoted by reference sign CK _ i in fig. 1), first poles of the plurality of gate transistors 102 are electrically connected to one source signal line D1, and second poles of the plurality of gate transistors 102 are electrically connected to a plurality of data lines D2 in a one-to-one correspondence manner.

When the display panel displays a picture, in combination with the timing diagram shown in fig. 2, the plurality of clock signal lines output a high level in a time-sharing manner, and control the plurality of control transistors in the gate circuit 101 to be turned on in a time-sharing manner, so as to transmit the data voltage on the source signal line D1 to the plurality of data lines D2 in a time-sharing manner.

However, the inventor finds in the course of research that the clock signal provided by the clock signal line is going high and lowThe flat transition affects the data voltage transmitted on the data line D2. FIG. 3 is an equivalent diagram of the parasitic capacitance, wherein C is _D1 Parasitic capacitance, C, of a source signal line D1 electrically connected to the gate transistor 102 _D2 Parasitic capacitance, C, of the data line D2 electrically connected to the gate transistor 102 _gd Is the parasitic capacitance between the gate and the second pole of the gating transistor 102.

When the clock signal provided by the clock signal line changes from high level to low level, the clock signal is influenced by the parasitic capacitor C _gd The falling edge of the clock signal pulls the data voltage on the data line D2 to which the gating transistor 102 is electrically connected low, so that the data voltage also makes a downward transition.

Especially for the display panel with non-rectangular shape, the length of the data line D2 in the display panel is different. For the data line D2 with smaller length, the load and parasitic capacitance C of the data line D2 _D2 The data voltage transmitted on the data line D2 is more affected by the falling edge of the clock signal, and therefore the data voltage is pulled down to a greater extent. Therefore, the data voltages written in the sub-pixels electrically connected with different data lines are obviously different, so that the display uniformity of the display panel is poor, and the poor phenomena such as picture flicker are easy to occur.

To this end, an embodiment of the present invention provides a display device, as shown in fig. 4 and fig. 5, fig. 4 is a top view of the display device provided in the embodiment of the present invention, fig. 5 is a top view of the display panel 1 provided in the embodiment of the present invention, the display device includes the display panel 1 and the driving circuit 2, and the driving circuit 2 may be a driving chip.

The display panel 1 includes a plurality of sub-pixels 3, each sub-pixel 3 includes a charging transistor M1, a gate of the charging transistor M1 is electrically connected to a first Scan line Scan1, and a first pole of the charging transistor M1 is electrically connected to a Data line Data. The charging transistor M1 is used to write the Data voltage on the Data line Data into the sub-pixel 3 when turned on, so as to charge the sub-pixel 3.

The display panel 1 further includes a plurality of gate circuits 4, each gate circuit 4 includes at least one first gate transistor T1 and one second gate transistor T2, a gate of each first gate transistor T1 is electrically connected to at least one first clock line CK1 in a one-to-one correspondence manner, a gate of each second gate transistor T2 is electrically connected to the second clock line CK2, first poles of each first gate transistor T1 and each second gate transistor T2 are electrically connected to the source signal line S, and second poles of each first gate transistor T1 and each second gate transistor T2 are electrically connected to the plurality of Data lines Data in a one-to-one correspondence manner. For convenience of understanding, in the drawings of the embodiments of the present invention, an ith first gate transistor is denoted by reference numeral T1_ i, and an ith first clock line electrically connected to the ith first gate transistor T1_ i is denoted by reference numeral CK1_ i.

In the above structure, by controlling the first and second gate transistors T1 and T2 to be turned on at a time division basis, the Data voltage supplied from the source signal line S can be transferred to the plurality of Data lines Data electrically connected to the first and second gate transistors T1 and T2 at a time division basis. This structure can reduce the number of source signal lines S required to be provided in the display panel 1, and further reduce the number of pins for supplying data voltages in the driving circuit 2, so as to reduce the manufacturing cost of the driving circuit 2.

As shown in fig. 6, fig. 6 is a timing diagram corresponding to fig. 4 and 5, in which the first Scan line Scan1 is used for transmitting a first Scan signal including a first enable level and a first disable level, and the charging transistor M1 is used for being turned on by the first enable level and being turned off by the first disable level. Wherein, the transition edge when the first enable level is transitioned to the first non-enable level is a first transition edge 5.

It should be noted that the level state of the first enable level is related to the device type of the charging transistor M1: when the charging transistor M1 is a P-type transistor, the first enable level is a low level, and the first transition edge 5 is a rising edge; when the charging transistor M1 is an N-type transistor, the first enable level is high, and the first transition edge 5 is a falling edge.

The first clock line CK1 and the second clock line CK2 are respectively used for transmitting clock signals including a second enable level and a second disable level, wherein the clock signal provided by the first clock line CK1 is defined as the first clock signal, and the clock signal provided by the second clock line CK2 is defined as the second clock signal. The first and second pass transistors T1 and T2 are adapted to be turned on by a second enable level and turned off by a second disable level. Wherein the transition edge when the second enable level transitions to the second disable level is a second transition edge 6.

It should be noted that the level state of the second enable level is related to the device type of the gating transistor: when the first gating transistor T1 and the second gating transistor T2 are P-type transistors, the second enable level is a low level, and the second transition edge 6 is a rising edge; when the first gating transistor T1 and the second gating transistor T2 are N-type transistors, the second enable level is high, and the first transition edge 5 is a falling edge. Fig. 6 is a schematic diagram illustrating an example in which the first enable level and the second enable level are both high.

With reference to fig. 6, the driving circuit 2 is configured to: in one frame time F, when the first Scan line Scan1 is controlled to output the first enable level, the first clock line CK1 and the second clock line CK2 are controlled to output the second enable level in a time-sharing manner, wherein the time when the second clock line CK2 outputs the second enable level is later than the time when the first clock line CK1 outputs the second enable level, that is, in any one of the gate circuits 4, the second gate transistor T2 is turned on last, and the turn-on time of the second gate transistor T2 is later than the turn-on time of any one of the first gate transistors T1. And, the second transition edge 6 of the clock signal output by the second clock line CK2 electrically connected to at least a part of the gating circuit 4 is not earlier than the first transition edge 5, i.e., the second transition edge 6 of the second clock signal corresponding to the part of the gating circuit 4 either occurs simultaneously with the first transition edge 5 of the first scan signal or is later than the first transition edge 5 of the first scan signal.

The embodiment of the present invention is described by taking an example that the first enable level and the second enable level are respectively high levels, that is, the first transition edge 5 and the second transition edge 6 are respectively falling edges. In the embodiment of the present invention, for the charging transistor M1 and the second gating transistor T2 electrically connected to the same Data line Data, since the falling edge of the second clock signal received by the second gating transistor T2 is not earlier than the falling edge of the first scan signal, the charging transistor M1 is turned off either synchronously when the falling edge of the second clock signal occurs or before the falling edge of the second clock signal occurs. Therefore, the change of the Data voltage on the Data line Data caused by the falling edge of the second clock signal is not further written into the sub-pixel 3 where the charging transistor M1 is located through the charging transistor M1, and the charging state of the sub-pixel 3 is not affected.

Especially for the display panel with non-rectangular shape, the change of the Data voltage caused by the falling edge of the second clock signal is not written into the sub-pixel 3 any more, therefore, even if the length of the Data line Data connected with the second gating transistor T2 is very short, the influence of the falling edge of the second clock signal on the Data voltage does not further influence the charging state of the sub-pixel 3, thereby effectively weakening the difference of the light-emitting brightness of different sub-pixels 3 and significantly improving the display uniformity of the display panel 1.

In other words, since the above technical solution can effectively improve the influence of the length difference of the Data lines Data on the display uniformity, when the shape of the irregular display panel is designed, the limitation of the display uniformity, which is a factor causing the appearance of the display panel 1, can be reduced. Especially to the display device in on-vehicle field, for example on-vehicle display screen, can effectively deal with the special-shaped display panel's of on-vehicle customization demand, experience for the car owner provides the on-vehicle screen of higher end.

In addition, referring to fig. 4 again, the display panel 1 further includes a shift register 7, the shift register 7 includes a plurality of stages of shift units 71 arranged in cascade, and the shift units 71 are electrically connected to the first scan lines. The driving circuit 2 is electrically connected to the shift register 7 through the frame start signal line STV, the third clock line CK3, and the fourth clock line CK4, and the driving circuit 2 outputs corresponding signals to the shift register 7 through the frame start signal line STV, the third clock line CK3, and the fourth clock line CK4, thereby controlling the shift units 71 in the shift register 7 to sequentially output high levels to the first Scan line Scan 1.

Further, referring to fig. 4 to 6, the second transition edge 6 of the clock signal output from the second clock line CK2 electrically connected to at least a part of the gate circuit 4 is later than the first transition edge 5.

In the above arrangement, for the charging transistor M1 and the second gating transistor T2 electrically connected to the same Data line Data, the charging transistor M1 is already turned off before the falling edge of the second clock signal occurs, and therefore, at the time when the second clock signal transitions from a high level to a low level, the charging transistor M1 is already in a completely turned-off state, thereby more effectively preventing the change of the Data voltage caused by the transition of the second clock signal from affecting the charging of the sub-pixel 3.

In one possible embodiment, referring again to fig. 4 to 6, for any one of the gating circuits 4, the second transition edge 6 of the clock signal output by the second clock line CK2 electrically connected to the gating circuit 4 is not earlier than the first transition edge 5.

The setting mode is that the time sequence of the second clock signal received by each gating circuit 4 is adjusted, and at this time, the time sequences of the second clock signals received by the second gating transistors T2 in the gating circuits 4 are the same, so that the second gating transistors T2 in each gating circuit 4 only need to be electrically connected with the same second clock line CK2, the wiring design in the display panel 1 is simplified, and the narrow-frame design of the display device is favorably realized.

Alternatively, in another possible implementation manner, as shown in fig. 7 and fig. 8, fig. 7 is another top view of the display panel 1 according to the embodiment of the present invention, and fig. 8 is a timing diagram corresponding to fig. 7, where the Data lines Data include a first type Data line Data1 and a second type Data line Data2, and the length of the first type Data line Data1 is smaller than the length of the second type Data line Data 2. For example, in a display panel 1 of a type, such as the display panel 1 applied to a vehicle-mounted display screen, the Data lines Data on both sides of the display panel 1 are short in length, and the Data lines Data can be regarded as the first type Data lines Data1, that is, the irregular Data lines with the length reduced due to the influence of the shape of the display panel 1; the middle Data line Data has a larger length, and the Data line Data can be regarded as a second type Data line Data2, i.e. a conventional Data line with unchanged length without being influenced by the appearance of the display panel 1.

Based on this, the gate circuit 4 includes a first gate circuit 41 and a second gate circuit 42, wherein the first gate circuit 41 is electrically connected to the first type Data lines Data1, and the second gate circuit 42 is electrically connected to the second type Data lines Data 2. The second clock line CK2 includes a second clock line CK21 electrically connected to the first gate circuit 41 and a second clock line CK22 electrically connected to the second gate circuit 42. Within one frame time F, the second transition edge 6 of the clock signal output from the second clock line CK21 is not earlier than the first transition edge 5, and the second transition edge 6 of the clock signal output from the second clock line CK22 is earlier than the first transition edge 5.

For convenience of description, the sub-pixel 3 electrically connected to the first type Data line Data1 is defined as a first sub-pixel, and the sub-pixel 3 electrically connected to the second type Data line Data2 is defined as a second sub-pixel. For the Data line Data1 of the first type with a smaller length, the anti-coupling performance is lower, so the falling edge of the clock signal will pull down the Data voltage to a greater extent, and if the pulled-down Data voltage is written into the first sub-pixel, the luminance of the first sub-pixel will be different from that of the other second sub-pixels. Therefore, the embodiment of the invention can effectively reduce the influence of the falling edge of the second clock signal on the light-emitting brightness of the first sub-pixel by electrically connecting the first type Data line Data1 with a shorter length with the first gating circuit 41 and adjusting the time sequence of the second clock signal corresponding to the first gating circuit 41, thereby weakening the difference of the light-emitting brightness of the first sub-pixel and the second sub-pixel to a greater extent.

Note that, in general, the number of sub-pixels 3 electrically connected to the second-type Data lines Data2 (regular Data lines) in the display panel 1 is much larger than the number of sub-pixels 3 electrically connected to the first-type Data lines Data1 (irregular Data lines). By adopting the above arrangement, while weakening the difference between the luminance of the two sub-pixels 3, the timing of the second clock signal corresponding to the second gate circuit 42 does not need to be changed, and thus the charging time of the sub-pixels 3 electrically connected to the second Data line Data2 (normal Data line) is not affected, and further the luminance of the sub-pixels is not affected.

Further, referring again to fig. 7, in at least a part of the first gate circuit 41, the length of the first type Data line Data1 electrically connected to the second gate transistor T2 in the first gate circuit 41 is smaller than the length of the first type Data line Data1 electrically connected to the first gate transistor T1 in the first gate circuit 41. As analyzed above, the shorter the Data line Data is, the more the influence of the transition of the clock signal on the Data voltage is, and the more the changed Data voltage is written into the sub-pixel 3, the more the influence on the light-emitting luminance of the sub-pixel 3 is. Therefore, by electrically connecting the first-type Data lines Data1 having a shorter length to the second gate transistor T2, the difference in the light emission luminance of the sub-pixels 3 connected to different first-type Data lines Data1 can be weakened more by the timing of the second clock signal.

In one possible embodiment, referring to fig. 4 and 5 in combination, as shown in fig. 9, fig. 9 is another timing diagram corresponding to fig. 4 and 5, and the time for the first clock line CK1 to output the second enable level in one frame time F is t1. The transition edge when the second non-enable level transitions to the second enable level is the fourth transition edge 8, and the time between the fourth transition edge 8 of the clock signal provided by the second clock line CK2 electrically connected to at least part of the gating circuit 4 and the first transition edge 5 is t2, and t2= t1.

Taking the first enable level and the second enable level as high levels as an example, in one frame time F, the duration of the high level output by the first clock line CK1 is t1, the time between the rising edge of the second clock signal and the falling edge of the first scan signal corresponding to at least part of the gating circuit 4 is t2, and t1= t2.

Specifically, when the first scan signal is at a high level, the charging transistor M1 electrically connected to the first gate transistor T1 and the second gate transistor T2 is in a conductive state. When the first clock line CK1 provides a high level, the first gating transistor T1 is turned on, and the Data voltage provided by the source signal line S is transmitted to the Data line Data electrically connected thereto through the turned-on first gating transistor T1, and is further written into the sub-pixel 3 where the charging transistor M1 is located through the charging transistor M1; when the second clock line CK2 provides a high level, the second gating transistor T2 is turned on, and the Data voltage provided by the source signal line S is transmitted to the Data line Data electrically connected thereto through the turned-on second gating transistor T2, and is further written into the sub-pixel 3 where the charging transistor M1 is located through the charging transistor M1.

In the above arrangement, in the period in which the first scan signal is set high, the time in which the first clock signal is set high and the time in which the second clock signal is set high are equal, so that the on times of the first gate transistor T1 and the second gate transistor T2 are equal. Therefore, for the Data line Data electrically connected to the first and second gate transistors T1 and T2, the time of the process of the Data voltage being transmitted to the Data line Data via the source Data line Data and further being written to the sub-pixel 3 via the charge transistor M1 is equal. In this way, the charging time lengths of the sub-pixels 3 connected with different Data lines Data are consistent, the charging effect of the sub-pixels 3 is more uniform, and the display uniformity of the display device is further improved.

In a possible implementation manner, as shown in fig. 10 and fig. 11, fig. 10 is a partial top view of the display panel 1 according to an embodiment of the present invention, and fig. 11 is a timing diagram corresponding to fig. 10, in which the Data lines Data include a first Data line Data3, and the first Data line Data3 is electrically connected to at least a portion of the first gating transistor T1 in the gating circuit 4.

The display panel 1 further includes a compensation structure 9, and the compensation structure 9 is electrically connected to the compensation line CL and the first Data line Data3, respectively. The compensation line CL is used for transmitting a compensation signal including a first level and a second level, wherein a transition edge when the second level transitions to the first level is a third transition edge 11, and transition states of the third transition edge 11 and the second transition edge 6 are opposite. That is, when the second enable level is high and the second transition edge 6 is a falling edge, the first level is high, the second level is low, and the third transition edge 11 is a rising edge.

When controlling the first Scan line Scan1 to output the first enable level, the driving circuit 2 is further configured to: the compensation signal output by the compensation line CL is controlled to jump from the second level to the first level, and for the first clock line CK1 and the compensation line CL corresponding to the same first Data line Data3, the third jumping edge 11 of the compensation signal output by the compensation line CL is later than the second jumping edge 6 of the clock signal output by the first clock line CK 1.

The first clock line CK1 and the compensation line CL corresponding to the same first Data line Data3 refer to: for one first Data line Data3, a first clock line CK1 to which a first gate transistor T1 electrically connected to the first Data line Data3 is connected, and a compensation line CL connected to the first Data line Data3.

Specifically, taking the first enable level, the second enable level, and the first level as high levels as an example, when the first scan signal is at a high level, the charging transistor M1 electrically connected to the first gate transistor T1 and the second gate transistor T2 is all turned on. When the first clock line CK1 provides a high level, the first gating transistor T1 is turned on, and the Data voltage provided by the source signal line S is transmitted to the Data line Data electrically connected thereto via the turned-on first gating transistor T1, and is further written into the sub-pixel 3 where the charging transistor M1 is located via the charging transistor M1. However, when the first clock signal jumps from a high level to a low level, the falling edge of the first clock signal pulls the Data voltage on the first Data line Data3 connected to the first gating transistor T1 down by Δ V1 (Δ V1 > 0) due to the influence of the parasitic capacitor. When the falling edge of the first clock signal occurs, the charging transistor M1 corresponding to the first gating transistor T1 is still in a conducting state, so that the change of the data voltage is further fed back to the sub-pixel 3, thereby affecting the charging of the sub-pixel 3.

In contrast, in the embodiment of the present invention, by providing the compensation structure 9 electrically connected to the first Data line Data3, after the falling edge of the first clock signal occurs, a rising edge is generated by controlling the compensation signal, the rising edge can be used to pull up Δ V2 to the Data voltage on the first Data line Data3, and then the portion of Δ V2 that is pulled up is used to compensate for the Δ V1 that was pulled down before, so as to weaken the influence of the falling edge of the first clock signal on the charging of the sub-pixel 3, and improve the uniformity of the light-emitting luminance of different sub-pixels 3.

Further, the voltage of the first level may be equal to the voltage of the second enable level, and the voltage of the second level may be equal to the voltage of the second disable level.

Therefore, the voltage difference of the rising edge of the compensation signal is equal to the voltage difference of the falling edge of the first clock signal, the Δ V2 of the rising edge of the compensation signal for pulling up the data voltage is approximately consistent with the Δ V1 of the falling edge of the first clock signal for pulling down the data voltage, the two can be offset better, and the compensation effect is better.

In a possible implementation manner, as shown in fig. 12 and fig. 13, fig. 12 is another partial top view of the display panel 1 according to an embodiment of the present invention, and fig. 13 is a timing diagram corresponding to fig. 12, the first Data line Data3 includes a first a Data line Data31, the compensation structure 9 includes a first compensation structure 91, the compensation line CL includes a first compensation line CL1, and the first compensation structure 91 is electrically connected to the first compensation line CL1 and the first a Data line Data31, respectively. Wherein, the first compensation line CL1 is multiplexed with the second clock line CK 2.

In one frame time F, the first gating transistor T1 and the second gating transistor T2 need to be turned on in time division, and thus, the rising edge of the second clock signal is later than the falling edge of the first clock signal. Therefore, the first compensation line CL1 can be multiplexed with the second clock line CK2, and the pull-up effect of the rising edge of the second clock signal on the data voltage is utilized to compensate the pull-down effect of the falling edge of the first clock signal on the data voltage before, so as to weaken the influence of the transition of the first clock signal on the charging of the sub-pixel 3.

In addition, since the falling edge of the second clock signal occurs after the charging transistor M1 is turned off, the influence of the falling edge generated subsequently by the second clock signal on the Data voltage on the first Data line Data31 will not be further written into the sub-pixel 3 where the charging transistor M1 is located through the charging transistor M1. In the above arrangement, only the rising edge of the second clock signal can affect the charging of the sub-pixel 3, and the falling edge does not affect the charging of the sub-pixel 3, so that overcompensation is avoided.

In addition, by multiplexing the first compensation line CL1 and the second clock line CK2, it is possible to simplify wiring, reduce the number of signal lines required to be provided in the display panel 1, and contribute to reducing the lower bezel width of the display panel 1.

In a possible implementation manner, as shown in fig. 14 and 15, fig. 14 is a partial top view of the display panel 1 according to an embodiment of the present invention, fig. 15 is a timing diagram corresponding to fig. 14, the first Data line Data3 includes a first second Data line Data32, the compensation structure 9 includes a second compensation structure 92, the compensation line CL includes a second compensation line CL2, and the second compensation structure 92 is electrically connected to the second compensation line CL2 and the first second Data line Data32, respectively.

The first gate transistor T1 includes a first gate-a transistor T11 and a first gate-b transistor T12, and the first gate-a transistor T11 is electrically connected to the first gate-b Data line Data 32. The time when the first clock line CK1 electrically connected to the first gate-down transistor T12 outputs the second enable level is later than the time when the first clock line CK1 electrically connected to the first gate-up transistor T11 outputs the second enable level for one frame time F. Wherein the second compensation line CL2 is multiplexed with the first clock line CK1 electrically connected to the first second gating transistor T12.

For example, it is assumed that the first gating module includes 1 st to kth first gating transistors T1 to T1, and k first clock lines CK1 electrically connected to the 1 st to kth first gating transistors T1 sequentially time-share and output a high level. When the first gate transistor T11 is the ith first gate transistor T1, i is greater than or equal to 1 and less than k, the first gate transistor T12 may be any one of the (i + 1) th first gate transistor T1 to the kth first gate transistor T1.

In one frame time F, since the rising edge of the first clock signal corresponding to the first second gate transistor T12 is later than the falling edge of the first clock signal corresponding to the first gate transistor T11, the second compensation line CL2 can be multiplexed with the first clock line CK1 electrically connected to the first second gate transistor T12, and the influence of the rising edge of the first clock signal corresponding to the first second gate transistor T12 on the pull-up of the Data voltage on the first second Data line Data32 is utilized to compensate the influence of the falling edge of the first clock signal corresponding to the first gate transistor T11 on the pull-down of the Data voltage on the first second Data line Data32, thereby weakening the influence of the transition of the first clock signal on the charging of the sub-pixel 3.

In addition, by multiplexing the second compensation line CL2 and the first clock line CK1 electrically connected to the first second gate transistor T12, it is possible to simplify wiring, reduce the number of signal lines required to be provided in the display panel 1, and contribute to reducing the lower frame width of the display panel 1.

In one possible implementation, referring again to fig. 10, the compensation structure 9 includes a compensation transistor T3, a gate of the compensation transistor T3 is electrically connected to the compensation line CL, and a second pole of the compensation transistor T3 is electrically connected to the first Data line Data3.

When the compensation structure 9 includes the compensation transistor T3, a parasitic capacitance C is formed between the gate and the second pole of the compensation transistor T3 _gd When the compensation line CL generates a rising edge, the parasitic capacitance C is received _gd The positive change of the Data voltage is offset by the negative change of the Data voltage caused by the first clock signal, so as to reduce the influence of the falling edge of the first clock signal on the charging state of the sub-pixel 3.

Furthermore, it should be noted that, by configuring the compensation structure 9 as a transistor structure, the influence of the rising edge of the compensation signal on the data voltage and the influence of the falling edge of the first clock signal on the data voltage are both caused by the parasitic capacitance C of the transistor _gd The influence is generated, so that the influence degrees of the two signals on the data voltage are similar, and the compensation effect of the compensation transistor T3 is better.

Further, referring again to fig. 10, the first pole of the compensation transistor T3 is floating, i.e., the first pole of the compensation transistor T3 is not connected to any structure. With this arrangement, even if the compensation transistor T3 is turned on when the compensation signal is set high, no signal is written into the first electrode of the compensation transistor T3, so that no signal is written into the first Data line Data3 from the first electrode of the compensation transistor T3, and interference to the signal transmitted on the first Data line Data3 can be avoided.

Alternatively, as shown in fig. 16, fig. 16 is still another partial top view of the display panel 1 according to the embodiment of the invention, in which the first pole and the second pole of the compensation transistor T3 are electrically connected to the same first Data line Data3. With this arrangement, the first and second poles of the compensation transistor T3 are electrically connected to each other, and even if the compensation transistor T3 is turned on when the compensation signal is set high, only the Data voltage is transmitted to the first and second poles of the compensation transistor T3, and thus the signal transmitted to the first Data line Data3 is not disturbed.

In a possible implementation manner, as shown in fig. 17 and 18, fig. 17 is a partial top view of a display panel 1 according to an embodiment of the present invention, and fig. 18 is a top view of a film structure corresponding to fig. 17, in order to reduce a voltage drop generated when a data voltage is transmitted across a first gate transistor T1 and a second gate transistor T2, the first gate transistor T1 and the second gate transistor T2 may respectively include x sub-gate transistors K1 arranged in parallel, where x ≧ 2. At this time, the compensation transistor T3 may include x sub-compensation transistors K2, the gates of the x sub-compensation transistors K2 are all electrically connected to the compensation line CL, and the second poles of the x sub-compensation transistors K2 are all electrically connected to the first Data line Data3.

By setting the compensation transistor T3 to have the same circuit structure as the first gating transistor T1, the parasitic capacitance of the compensation transistor T3 is close to the parasitic capacitance of the compensation transistor T3, and therefore, the influence of the rising edge of the compensation signal on the pull-up of the Data line Data voltage tends to the influence of the falling edge of the first clock signal on the pull-down of the Data voltage, so that the compensation transistor T3 achieves a better compensation effect.

Of course, as shown in fig. 19 and 20, fig. 19 is another partial top view of the display panel 1 according to the embodiment of the present invention, and fig. 20 is a top view of the film structure corresponding to fig. 19, when the first gate transistor T1 includes x sub-gate transistors K1 arranged in parallel, the compensation transistor T3 may also include only one sub-compensation transistor K2, and at this time, the compensation transistor T3 can still be used to compensate for the voltage jump of the data voltage.

In a possible implementation manner, as shown in fig. 21, fig. 21 is a partial top view of the display panel 1 according to an embodiment of the present invention, and the compensation structure 9 includes a compensation capacitor C, a first plate of the compensation capacitor C is electrically connected to the compensation line CL, and a second plate of the compensation capacitor C is electrically connected to the first Data line Data3, so that when a rising edge occurs in the compensation signal, the compensation capacitor C is used to pull up the Data voltage transmitted on the first Data line Data3.

In a possible implementation manner, as shown in fig. 22 and 23, fig. 22 is a top view of another film structure of the display panel 1 provided in the embodiment of the present invention, fig. 23 is a top view of another film structure of the display panel 1 provided in the embodiment of the present invention, the first gate transistor T1 includes a first third gate transistor T13 and a first third gate transistor T14, and a length of the first Data line Data3 electrically connected to the first third gate transistor T13 is smaller than a length of the first Data line Data3 electrically connected to the first third gate transistor T14.

The compensation structure 9 includes a third compensation structure 93 and a fourth compensation structure 94, the third compensation structure 93 and the first third gate transistor T13 are electrically connected to the same first Data line Data3, and the fourth compensation structure 94 and the first third gate transistor T14 are electrically connected to the same first Data line Data3. Referring to fig. 22, the area of the third compensation structure 93 is greater than that of the fourth compensation structure 94, and/or, referring to fig. 23, the minimum distance between the third compensation structure 93 and the first Data line Data3 connected thereto is less than the minimum distance between the fourth compensation structure 94 and the first Data line Data3 connected thereto.

When the length of the first Data line Data3 electrically connected to the first third gating transistor T13 is small, the first Data line Data3 has low anti-coupling performance, and at this time, the falling edge of the first clock signal pulls down the Data voltage transmitted on the first Data line Data3 to a greater extent. At this time, by increasing the area of the third compensation structure 93 and/or decreasing the minimum distance between the third compensation structure 93 and the first Data line Data3 connected thereto, the coupling between the third compensation structure 93 and the first Data line Data3 connected thereto can be increased, and further, the parasitic capacitance of the first Data line Data3 is increased, and the anti-coupling property thereof is increased, so as to decrease the influence of the transition of the first clock signal on the Data voltage on the first Data line Data3.

In one possible embodiment, referring again to fig. 4, the sub-pixel 3 further comprises a pixel electrode 31, and the second pole of the charging transistor M1 is electrically connected to the pixel electrode 31. In this case, the Display panel 1 provided in the embodiment of the present invention is a Liquid Crystal Display (LCD) panel. In this structure, the display panel 1 further includes a common electrode and liquid crystal molecules. When the sub-pixel 3 is driven to emit light, the first Scan line Scan1 controls the charging transistor M1 to be turned on, and writes the Data voltage transmitted on the Data line Data into the pixel electrode 31, so as to control the liquid crystal molecules to rotate under the action of the electric field formed by the pixel electrode 31 and the common electrode, and the light is emitted through the liquid crystal molecules.

Alternatively, in another possible implementation manner, as shown in fig. 24, fig. 24 is another schematic structural diagram of the sub-pixel 3 provided in the embodiment of the present invention, and the sub-pixel 3 may also include a pixel circuit 32 and a light emitting element 33 that are electrically connected. The pixel circuit 32 includes a driving transistor M0 and a charging transistor M1, and a second electrode of the charging transistor M1 is electrically connected to the driving transistor M0. At this time, the display panel 1 provided in the embodiment of the invention is an Organic Light-Emitting Diode (OLED) display panel.

In addition, the pixel circuit 32 further includes a gate reset transistor M2, an anode reset transistor M3, a threshold compensation transistor M4, first and second emission control transistors M5 and M6, and a storage capacitor Cst.

In conjunction with the timing chart shown in fig. 25, the gate reset transistor M2 is electrically connected between the reset signal line Vref and the gate of the driving transistor M0, and is used to reset the gate of the driving transistor M0 in response to a low level supplied from the second Scan line Scan 2. The anode reset transistor M3 is electrically connected between the reset signal line Vref and the light emitting element 33, and resets the anode voltage of the light emitting element 33 in response to a low level supplied from the first Scan line Scan 1.

The threshold compensation transistor M4 is electrically connected between the second pole of the driving transistor M0 and the gate electrode of the driving transistor M0, and the charging transistor M1 and the threshold compensation transistor M4 are used to write the data voltage into the gate electrode of the driving transistor M0 in response to the low level supplied from the first Scan line Scan1 and perform threshold compensation on the driving transistor M0.

The first light emission controlling transistor M5 is electrically connected between the power supply signal line PVDD and the first pole of the driving transistor M0, the second light emission controlling transistor M6 is electrically connected between the second pole of the driving transistor M0 and the light emitting element 33, and the first light emission controlling transistor M5 and the second light emission controlling transistor M6 are configured to transmit the driving current converted by the driving transistor M0 to the light emitting element 33 in response to the low level supplied from the light emission controlling signal line Emit to drive the light emitting element 33 to Emit light.

In the above circuit configuration, the charging transistor M1 may be a P-type transistor, and at this time, the first enable level is low, the first disable level is high, and the second transition edge 6 is a rising edge.

Based on the same inventive concept, the embodiment of the present invention further provides a driving method of the display panel 1, and the driving method is used for driving the display panel 1. With reference to fig. 4 to 6, the driving method includes: and in one frame time F, when the first Scan line Scan1 is controlled to output the first enable level, the first clock line CK1 and the second clock line CK2 are controlled to output the second enable level in a time-sharing manner, wherein the time for outputting the second enable level by the second clock line CK2 is later than the time for outputting the second enable level by the first clock line CK1, and a second transition edge 6 of a clock signal output by the second clock line CK2 which is electrically connected with at least part of the gating circuit 4 is not earlier than the first transition edge 5.

Taking the first enable level and the second enable level as high levels respectively, that is, the first transition edge 5 and the second transition edge 6 are falling edges respectively, in the embodiment of the present invention, for the charging transistor M1 and the second gating transistor T2 electrically connected to the same Data line Data, since the falling edge of the second clock signal received by the second gating transistor T2 is not earlier than the falling edge of the first scan signal, the charging transistor M1 is turned off synchronously either when the falling edge of the second clock signal occurs or before the falling edge of the second clock signal occurs. Therefore, the change of the Data voltage on the Data line Data caused by the falling edge of the second clock signal is not further written into the sub-pixel 3 where the charging transistor M1 is located through the charging transistor M1, and the charging state of the sub-pixel 3 is not affected.

In one possible embodiment, in conjunction with fig. 4 to 6, the second transition edge 6 of the clock signal output by the second clock line CK2 electrically connected to at least part of the gating circuit 4 is later than the first transition edge 5.

In the above driving method, for the charging transistor M1 and the second gating transistor T2 electrically connected to the same Data line Data, the charging transistor M1 is already turned off before the falling edge of the second clock signal occurs, and therefore, the charging transistor M1 is already in a completely turned-off state at the time when the second clock signal transitions from a high level to a low level, thereby more effectively preventing the change of the Data voltage caused by the transition of the second clock signal from affecting the charging of the sub-pixel 3.

In one possible implementation, referring to fig. 10 and 11, the Data lines Data include a first Data line Data3, and the first Data line Data3 is electrically connected to at least a portion of the first gating transistor T1 in the first gating circuit 41.

The display panel 1 further comprises a compensation structure 9, wherein the compensation structure 9 is electrically connected to a compensation line CL and the first Data line Data3 respectively, the compensation line CL is used for transmitting a compensation signal containing a first level and a second level, wherein a transition edge when the second level is transited to the first level is a third transition edge 11, and transition states of the third transition edge 11 and the second transition edge 6 are opposite.

When controlling the first Scan line Scan1 to output the first enable level, the driving method further includes: the compensation signal output by the compensation line CL is controlled to jump from the second level to the first level, and for the first clock line CK1 and the compensation line CL corresponding to the same first Data line Data3, a third jumping edge 11 of the compensation signal output by the compensation line CL is later than a second jumping edge 6 of the clock signal output by the first clock line CK 1.

By arranging the compensation structure 9 electrically connected with the first Data line Data3, after the falling edge of the first clock signal occurs, a rising edge is generated by controlling the compensation signal, the rising edge can be used for raising the Data voltage on the first Data line Data3 by delta V2, and then the raised delta V2 is used for compensating the delta V1 of the falling edge of the first clock signal for lowering the Data voltage, so that the influence of the falling edge of the first clock signal on the charging of the sub-pixel 3 is weakened, and the consistency of the light-emitting brightness of different sub-pixels 3 is improved.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display device comprising a display panel and a driving circuit, wherein,

the display panel comprises a plurality of sub-pixels, each sub-pixel comprises a charging transistor, the grid electrode of each charging transistor is electrically connected with a first scanning line, and the first electrode of each charging transistor is electrically connected with a data line;

the display panel further comprises a plurality of gating circuits, wherein each gating circuit comprises at least one first gating transistor and one second gating transistor, the grid electrode of the at least one first gating transistor is electrically connected with at least one first clock line, the grid electrode of the second gating transistor is electrically connected with a second clock line, the first poles of the at least one first gating transistor and the second gating transistor are electrically connected with a source signal line, and the second poles of the at least one first gating transistor and the second gating transistor are respectively and electrically connected with the plurality of data lines;

the drive circuit is configured to: and controlling the first clock line and the second clock line to output the second enable level in a time sharing manner when the first scan line is controlled to output the first enable level, wherein the second clock line outputs the second enable level later than the first clock line outputs the second enable level, and the second transition edge of the clock signal output by the second clock line electrically connected with at least part of the gating circuit is not earlier than the first transition edge.

2. The display device according to claim 1,

the second transition edge of the clock signal output by the second clock line electrically connected to at least part of the gating circuit is later than the first transition edge.

3. The display device according to claim 1,

for any one of the gating circuits, the second transition edge of the clock signal output by the second clock line electrically connected with the gating circuit is not earlier than the first transition edge.

4. The display device according to claim 1,

the data lines comprise first class data lines and second class data lines, the length of the first class data lines is smaller than that of the second class data lines, and the gating circuit comprises a first gating circuit and a second gating circuit, wherein the first gating circuit is electrically connected with the first class data lines, and the second gating circuit is electrically connected with the second class data lines;

the second clock line comprises a second clock line electrically connected with the first gating circuit and a second clock line electrically connected with the second gating circuit, the second transition edge of the clock signal output by the second clock line is not earlier than the first transition edge in one frame time, and the second transition edge of the clock signal output by the second clock line is earlier than the first transition edge.

5. The display device according to claim 4,

in at least part of the first gating circuit, the length of the first type of data line electrically connected with the second gating transistor is smaller than the length of the first type of data line electrically connected with the first gating transistor.

6. The display device according to claim 1,

in one frame time, the time for the first clock line to output the second enabling level is t1;

a transition edge when the second non-enable level transitions to the second enable level is a fourth transition edge, and a time between the fourth transition edge and the first transition edge of the clock signal output by the second clock line electrically connected to at least a part of the gating circuit is t2, where t2= t1.

7. The display device according to claim 1,

the data line comprises a first data line electrically connected with the first gating transistor in at least part of the gating circuit;

the display panel further comprises a compensation structure, the compensation structure is electrically connected with a compensation line and the first data line respectively, the compensation line is used for transmitting a compensation signal containing a first level and a second level, a jumping edge when the second level jumps to the first level is a third jumping edge, and jumping states of the third jumping edge and the second jumping edge are opposite;

when controlling the first scan line to output the first enable level, the driving circuit is further configured to: and controlling the compensation signal output by the compensation line to jump from the second level to the first level, wherein the third jumping edge of the compensation signal output by the compensation line is later than the second jumping edge of the clock signal output by the first clock line for the first clock line and the compensation line corresponding to the same first data line.

8. The display device according to claim 7,

the voltage of the first level is equal to the voltage of the second enable level, and the voltage of the second level is equal to the voltage of the second non-enable level.

9. The display device according to claim 7,

the first data line comprises a first A data line, the compensation structure comprises a first compensation structure, the compensation line comprises a first compensation line, and the first compensation structure is electrically connected with the first A data line and the first compensation line respectively;

wherein the first compensation line is multiplexed with the second clock line.

10. The display device according to claim 7,

the first data line comprises a first second data line, the compensation structure comprises a second compensation structure, the compensation line comprises a second compensation line, and the second compensation structure is electrically connected with the first second data line and the second compensation line respectively;

the first gating transistor comprises a first gate-A transistor and a first gate-B transistor, the first gate-A transistor is electrically connected with the first gate-B data line, and the time of the first clock line electrically connected with the first gate-B transistor outputting the second enabling level is later than the time of the first clock line electrically connected with the first gate-A transistor outputting the second enabling level in one frame time;

wherein the second compensation line is multiplexed with the first clock line electrically connected to the first B-gating transistor.

11. The display device according to claim 7,

the compensation structure comprises a compensation transistor, a grid electrode of the compensation transistor is electrically connected with the compensation line, and a second pole of the compensation transistor is electrically connected with the first data line.

12. The display device according to claim 11,

the first pole of the compensation transistor is floating.

13. The display device according to claim 11,

the first pole and the second pole of the compensation transistor are electrically connected to the same first data line.

14. The display device according to claim 11,

the first gating transistor comprises x sub-gating transistors which are arranged in parallel, x is larger than or equal to 2, the compensation transistor comprises x sub-compensation transistors, the grid electrodes of the x sub-compensation transistors are electrically connected with the compensation line, and the second poles of the x sub-compensation transistors are electrically connected with the first data line.

15. The display device according to claim 7,

the compensation structure comprises a compensation capacitor, a first polar plate of the compensation capacitor is electrically connected with the compensation line, and a second polar plate of the compensation capacitor is electrically connected with the first data line.

16. The display device according to claim 7,

the first gating transistor comprises a first third gating transistor and a first third gating transistor, and the length of the first data line electrically connected with the first third gating transistor is smaller than that of the first data line electrically connected with the first third gating transistor;

the compensation structure comprises a third compensation structure and a fourth compensation structure, the third compensation structure and the first third gating transistor are electrically connected to the same first data line, and the fourth compensation structure and the first third gating transistor are electrically connected to the same first data line;

the area of the third compensation structure is larger than that of the fourth compensation structure, and/or the minimum distance between the third compensation structure and the first data line connected with the third compensation structure is smaller than that between the fourth compensation structure and the first data line connected with the fourth compensation structure.

17. The display device according to claim 1,

the sub-pixel further comprises a pixel electrode, and the second pole of the charging transistor is electrically connected with the pixel electrode.

18. The display device according to claim 1,

the sub-pixel comprises a pixel circuit, the pixel circuit comprises a driving transistor and the charging transistor, and the second pole of the charging transistor is electrically connected with the driving transistor.

19. A driving method for a display panel, for driving the display panel according to claim 1, comprising:

20. The method for driving a display panel according to claim 19,

21. The method for driving a display panel according to claim 19,

the display panel further comprises a compensation structure, the compensation structure is electrically connected with a compensation line and the first data line respectively, the compensation line is used for transmitting a compensation signal containing a first level and a second level, wherein a transition edge when the second level jumps to the first level is a third transition edge, and the transition states of the third transition edge and the second transition edge are opposite;

when controlling the first scan line to output the first enable level, the driving method further includes: and controlling the compensation signal output by the compensation line to jump from the second level to the first level, wherein the third jumping edge of the compensation signal output by the compensation line is later than the second jumping edge of the clock signal output by the first clock line for the first clock line and the compensation line corresponding to the same first data line.