CN115207912A - Small signal stability enhancement control strategy for grid-connected converter under weak grid asymmetric voltage drop fault - Google Patents

Small signal stability enhancement control strategy for grid-connected converter under weak grid asymmetric voltage drop fault Download PDF

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CN115207912A
CN115207912A CN202210892279.3A CN202210892279A CN115207912A CN 115207912 A CN115207912 A CN 115207912A CN 202210892279 A CN202210892279 A CN 202210892279A CN 115207912 A CN115207912 A CN 115207912A
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locked loop
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CN115207912B (en
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姚骏
关磊
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Chongqing University
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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00Circuit arrangements for ac mains or ac distribution networks
    • H02J3/001Methods to deal with contingencies, e.g. abnormalities, faults or failures
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00Circuit arrangements for ac mains or ac distribution networks
    • H02J3/38Arrangements for parallely feeding a single network by two or more generators, converters or transformers
    • H02J3/46Controlling of the sharing of output between the generators, converters, or transformers
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J2203/00Indexing scheme relating to details of circuit arrangements for AC mains or AC distribution networks
    • H02J2203/20Simulating, e g planning, reliability check, modelling or computer assisted design [CAD]
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/56Power conversion systems, e.g. maximum power point trackers

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Abstract

The invention discloses a small signal stability enhancement control strategy of a grid-connected converter under the asymmetric voltage drop fault of a weak power grid. B) And calculating the dynamic interference of the output dynamics of the phase-locked loop on the negative sequence grid-connected voltage, the output current and the output voltage of the system, and introducing a compensation term on a negative sequence current loop to eliminate the related dynamic interference. According to the invention, on the basis of not increasing hardware equipment, the control strategy of the converter system is redesigned, disturbance caused by a phase-locked loop in a positive sequence current loop and a negative sequence current loop of the grid-connected converter under the asymmetric voltage drop fault is compensated and controlled, the small signal stability of the system during the asymmetric voltage drop fault is enhanced, and the success rate of asymmetric voltage drop fault ride-through is improved.

Description

Small signal stability enhancement control strategy for grid-connected converter under weak grid asymmetric voltage drop fault
Technical Field
The invention relates to a grid-connected converter system control method during an asymmetric voltage drop fault, which aims to enhance the small signal stability of a system during the asymmetric voltage drop fault and improve the success rate of asymmetric voltage drop fault ride-through, and belongs to the field of new energy power generation.
Background
With the increasing severity of energy and environmental issues, new energy power generation technology has gained wide attention and great development. Among these, a large number of photovoltaic power plants and wind generators are connected to the grid by means of power electronic converters as interfaces. However, because the power generation equipment is usually far away from the load center, the transmission lines of some new energy grid-connected systems are relatively weak, which causes frequent faults of the power system, and this brings various challenges to the stable operation of the power grid. Divided on a time scale, a power system fault can be divided into two transient phases (fault onset phase, fault clearance phase) and one steady-state phase (fault steady-state phase). Therefore, the stability problem of the new energy grid-connected system during the grid fault includes transient stability (large signal stability) in the fault transient stage and dynamic stability (small signal stability) in the fault steady-state stage. Transient stability of the fault transient stage can ensure that the grid-connected system has a balance point under the condition of the grid fault and can smoothly reach the balance point. On the other hand, during fault steady-state, transient components in the system have completely decayed. And the dynamic stability in the fault steady state period ensures that the grid-connected system keeps normal operation at the balance point in the fault steady state period until the fault is cleared. Therefore, the dynamic stability of the new energy grid-connected system during fault steady state is also important, and it may also affect the success rate of fault ride-through. At present, scholars at home and abroad research the dynamic stability of a new energy power generation system connected to a weak power grid based on a grid-connected converter.
(1) Huqi, fulijun, mafan, jifeng, zhangu, wang Guangyu, weak current network, based on the phase-locked control grid-connected converter small disturbance synchronous stability analysis [ J ], chinese Motor engineering report, 2021,41 (01): 98-108.
(2)J.Hu,B.Wang,W.Wang,H.Tang,Y.Chi and Q.Hu,“Small Signal Dynamics of DFIG-Based Wind Turbines During Riding Through Symmetrical Faults in Weak AC grid,”IEEE Transactions on Energy Conversion,vol.32,no.2,pp.720-730,Jun.2017.
The small signal stability of the grid-connected converter under a weak power grid is researched in the literature (1), and the influence of factors such as power grid impedance and controller parameters on the small signal stability is discussed. However, the small signal stability of grid-connected converters during weak grid faults has not been investigated. During the fault period, the small signal stability of the system is changed due to the change of the operation state and the grid structure of the grid-connected converter, and the grid-connected converter is easy to have the small signal instability phenomenon in the fault steady-state stage. How to improve the small-signal stability of the grid-connected converter during the weak grid fault needs to be studied.
Document (2) studies the small-signal stability of the doubly-fed wind power system during a weak grid symmetric voltage sag fault, however, does not study the dynamic stability during an asymmetric voltage sag fault. First, there is a dynamic coupling between the positive and negative sequence control systems, which affects the dynamic stability of the system during an asymmetric voltage sag fault. In addition, the effect of dynamic coupling between the negative sequence control system and the phase locked loop should also be considered. Due to the existence of the negative sequence component and the negative sequence power grid, compared with the symmetric fault, the problem of small signal stability of the grid-connected converter during the asymmetric voltage drop fault is more complicated. Therefore, how to improve the small-signal stability of the grid-connected converter during the steady state of the asymmetric voltage drop fault is not researched at present.
Disclosure of Invention
In view of the above defects in the prior art, the present invention aims to provide a grid-connected converter system control method during the asymmetric voltage drop fault of a weak grid, which redesigns the control strategy of a converter system on the basis of not increasing hardware devices. Disturbance caused by a phase-locked loop in a positive sequence control system and a negative sequence control system of the grid-connected converter under the asymmetric voltage drop fault is compensated and controlled, the small signal stability of the system during the asymmetric voltage drop fault is enhanced, and the success rate of ride-through of the asymmetric voltage drop fault is improved.
The technical scheme of the invention is realized as follows:
the small signal stability enhancement control strategy of the grid-connected converter under the weak grid asymmetric voltage drop fault is characterized in that: the method comprises the steps that under the condition of asymmetric voltage drop faults, disturbance caused by a phase-locked loop in a positive sequence control system and a negative sequence control system of a grid-connected converter is compensated and controlled;
(A) Compensating the influence of disturbance caused by a phase-locked loop under the asymmetric voltage drop fault on a grid-connected converter positive sequence control system, wherein the specific control steps are as follows:
a1 Calculate the dynamic delta theta of the PLL output according to the equations (1) and (2) pll+
Figure BDA0003768065830000021
Figure BDA0003768065830000022
In the formula, G N (s) and G PI_PLL (s) a frequency doubling trap transfer function and a PI controller transfer function respectively applied in the phase locked loop,
Figure BDA0003768065830000023
ω 0 =200πrad/s,ξ=0.707,
Figure BDA0003768065830000024
k p and k i Proportional coefficient and integral coefficient of PI controller; g PLL (s) is the transfer function of the phase locked loop;
Figure BDA0003768065830000025
the stable value of the positive sequence component of the grid-connected voltage of the system is obtained;
Figure BDA0003768065830000026
is the dynamic of the q-axis component of the positive sequence voltage of the grid-connected point, and can be formed by a positive sequence current loop
Figure BDA0003768065830000027
The difference between the actual value and 0. Where theta is pll+ Is the output of the phase-locked loop, theta pll+ =-θ pll- ;Δθ pll+ Is the error in the output of the phase locked loop, which cannot be directly measured, but can be calculated from equations (1) (2).
A2 Output dynamic delta theta of phase locked loop pll+ Positive sequence to system d axisGrid connection voltage
Figure BDA0003768065830000028
Output current
Figure BDA0003768065830000029
And an output voltage
Figure BDA0003768065830000031
System q-axis positive sequence grid-connected voltage
Figure BDA0003768065830000032
Output current
Figure BDA0003768065830000033
And an output voltage
Figure BDA0003768065830000034
Is calculated as in equation (3):
Figure BDA0003768065830000035
in the formula (I), the compound is shown in the specification,
Figure BDA0003768065830000036
and
Figure BDA0003768065830000037
expressing the dynamics of the positive sequence grid-connected voltage, the output current and the output voltage of the d axis of the system when the phase-locked loop outputs the dynamics;
Figure BDA0003768065830000038
and
Figure BDA0003768065830000039
expressing the dynamics of the q-axis positive sequence grid-connected voltage, the output current and the output voltage of the system when the phase-locked loop outputs the dynamics;
Figure BDA00037680658300000310
and
Figure BDA00037680658300000311
representing the dynamics of the positive sequence grid-connected voltage, the output current and the output voltage of a system d axis when the phase-locked loop outputs the dynamics;
Figure BDA00037680658300000312
and
Figure BDA00037680658300000313
representing the dynamics of the q-axis positive sequence grid-connected voltage, the output current and the output voltage of the system when the phase-locked loop outputs the dynamics;
Figure BDA00037680658300000314
and
Figure BDA00037680658300000315
stable values of a d-axis positive sequence component of the system positive sequence grid-connected voltage, the output current and the output voltage are obtained;
Figure BDA00037680658300000316
and
Figure BDA00037680658300000317
the stable values of the q-axis positive sequence component of the system positive sequence grid-connected voltage, the output current and the output voltage are obtained;
a3 Substituting formula (2) into formula (3) to calculate formula (4):
Figure BDA00037680658300000318
a4 Subtract the compensation term at the output of the positive sequence current loop
Figure BDA00037680658300000319
And
Figure BDA00037680658300000320
subtracting the compensation term at the input of the positive sequence current loop
Figure BDA00037680658300000321
Respectively eliminating the positive sequence grid-connected voltage of the phase-locked loop output dynamic pair system obtained in A3)
Figure BDA00037680658300000322
Output current
Figure BDA00037680658300000323
And an output voltage
Figure BDA00037680658300000324
Dynamic interference of (2). Wherein
Figure BDA00037680658300000325
Figure BDA00037680658300000326
Figure BDA00037680658300000327
The vector expression form of the system positive sequence grid-connected voltage, the output current and the output voltage is adopted;
Figure BDA00037680658300000328
the vector expression form of the stable values of the positive sequence grid-connected voltage, the output current and the output voltage of the system is adopted.
(B) Compensating the influence of disturbance caused by a phase-locked loop under the asymmetric voltage drop fault on a negative sequence control system of the grid-connected converter, wherein the specific control steps are as follows:
b1 Output dynamic delta theta of phase locked loop pll+ Negative sequence grid-connected voltage for system d shaft
Figure BDA0003768065830000041
Output current
Figure BDA0003768065830000042
And an output voltage
Figure BDA0003768065830000043
System q-axis positive sequence grid-connected voltage
Figure BDA0003768065830000044
Output current
Figure BDA0003768065830000045
And an output voltage
Figure BDA0003768065830000046
Is calculated according to equation (5):
Figure BDA0003768065830000047
in the formula (I), the compound is shown in the specification,
Figure BDA0003768065830000048
and
Figure BDA0003768065830000049
expressing the dynamics of the negative sequence grid-connected voltage, the output current and the output voltage of the d axis of the system when the output dynamics of the phase-locked loop is not considered;
Figure BDA00037680658300000410
and
Figure BDA00037680658300000411
expressing the dynamics of the q-axis negative sequence grid-connected voltage, the output current and the output voltage of the system when the phase-locked loop does not consider the output dynamics;
Figure BDA00037680658300000412
and
Figure BDA00037680658300000413
representing the dynamics of the negative sequence grid-connected voltage, the output current and the output voltage of a system d-axis when the output dynamics of the phase-locked loop are considered;
Figure BDA00037680658300000414
and
Figure BDA00037680658300000415
representing the dynamics of the q-axis negative sequence grid-connected voltage, the output current and the output voltage of the system when the phase-locked loop outputs the dynamics;
Figure BDA00037680658300000416
and
Figure BDA00037680658300000417
stable values of the d-axis positive sequence component of the system negative sequence grid-connected voltage, the output current and the output voltage are obtained;
Figure BDA00037680658300000418
and
Figure BDA00037680658300000419
stable values of q-axis positive sequence components of the system negative sequence grid-connected voltage, the output current and the output voltage are obtained;
b2 Substituting formula (2) into formula (5) to calculate formula (6):
Figure BDA00037680658300000420
b3 Subtract the compensation term at the output of the negative sequence current loop
Figure BDA00037680658300000421
And
Figure BDA00037680658300000422
subtracting the compensation term at the input of the negative-sequence current loop
Figure BDA00037680658300000423
Respectively eliminating negative sequence grid-connected voltage of phase-locked loop output dynamic pair system obtained in B2)
Figure BDA00037680658300000424
Output current
Figure BDA00037680658300000425
And an output voltage
Figure BDA00037680658300000426
Dynamic interference of (2). Wherein
Figure BDA00037680658300000427
Figure BDA00037680658300000428
Figure BDA00037680658300000429
Figure BDA0003768065830000051
The vector expression form of the system negative sequence grid-connected voltage, the output current and the output voltage is adopted;
Figure BDA0003768065830000052
the vector expression form of the stable values of the system negative sequence grid-connected voltage, the output current and the output voltage is adopted.
Compared with the prior art, the invention has the following beneficial effects:
the invention carries out compensation control on disturbance caused by a phase-locked loop in the positive sequence control system and the negative sequence control system of the grid-connected converter under the asymmetric voltage drop fault, enhances the small signal stability of the grid-connected converter during the asymmetric voltage drop fault, and improves the success rate of ride-through of the asymmetric voltage drop fault.
Drawings
Fig. 1 is a control block diagram of a grid-connected converter under an asymmetric voltage sag fault.
Fig. 2 is a schematic diagram of a phase-locked loop control structure adopted under an asymmetric voltage drop fault.
Fig. 3 is a control block diagram of a grid-connected converter adopting a small-signal stability enhancement control strategy.
Fig. 4 is a comparison graph of simulation waveforms of the grid-connected converter under the asymmetric voltage drop fault and with or without a small signal stability enhancement control strategy.
Detailed Description
The following detailed description of specific embodiments of the invention refers to the accompanying drawings.
Fig. 1 is a control block diagram of a grid-connected converter under an asymmetric voltage drop fault, in which a grid-connected converter system cuts off a power outer ring during the asymmetric voltage drop fault, only uses a current inner ring for control, and the system opens a negative sequence current control ring to control a negative sequence current component. U shape g Or U gdq The grid connection point voltage of the system; I.C. A g Or I gdq To output a current; v g Or V gdq Is the system output terminal voltage; z is a linear or branched member f Is the filter circuit impedance; z g Is the grid impedance; the + and-in the superscript or subscript represents the positive or negative sequence component, e.g.,
Figure BDA0003768065830000053
and
Figure BDA0003768065830000054
representing the positive sequence output current and the positive sequence grid-connected point voltage,
Figure BDA0003768065830000055
and
Figure BDA0003768065830000056
representing a negative sequence output current and a negative sequence grid-connected point voltage; the index ref indicates the reference value and the index pll indicates the quantity in the reference coordinate system detected by pll.
Fig. 2 is a schematic diagram of a control structure of a phase-locked loop adopted by a system under an asymmetric voltage drop fault, wherein a frequency doubling wave trap is added in the phase-locked loop to filter out the influence of a negative sequence component. G N (s) and G PI_PLL (s) a transfer function of a frequency-doubled trap applied in the phase-locked loop and a transfer function of the PI controller respectively,
Figure BDA0003768065830000057
ω 0 =200πrad/s,ξ=0.707,
Figure BDA0003768065830000058
k p and k i Proportional coefficient and integral coefficient of the PI controller respectively.
Fig. 3 is a control block diagram of a grid-connected converter adopting a small-signal stability enhancement control strategy. Subtracting the compensation term at the output of the positive sequence current loop
Figure BDA0003768065830000059
And
Figure BDA00037680658300000510
subtracting the compensation term at the input of the positive sequence current loop
Figure BDA00037680658300000511
Respectively eliminating positive sequence grid-connected voltage of phase-locked loop output dynamic pair system
Figure BDA00037680658300000512
Output current
Figure BDA00037680658300000513
And an output voltage
Figure BDA0003768065830000061
Dynamic interference of (2); subtracting the compensation term at the output of the negative-sequence current loop
Figure BDA0003768065830000062
And
Figure BDA0003768065830000063
subtracting a compensation term at the input of the negative sequence current loop
Figure BDA0003768065830000064
Respectively eliminating negative sequence grid-connected voltage of phase-locked loop output dynamic pair system
Figure BDA0003768065830000065
Output current
Figure BDA0003768065830000066
And an output voltage
Figure BDA0003768065830000067
Dynamic interference of (2).
The method comprises the following specific implementation steps:
(A) Compensating the influence of disturbance caused by a phase-locked loop under the asymmetric voltage drop fault on a grid-connected converter positive sequence control system, wherein the specific control steps are as follows:
a1 Calculate the dynamic delta theta of the PLL output according to the equations (1) and (2) pll+
Figure BDA0003768065830000068
Figure BDA0003768065830000069
In the formula, G N (s) and G PI_PLL (s) a frequency doubling trap transfer function and a PI controller transfer function respectively applied in the phase locked loop,
Figure BDA00037680658300000610
ω 0 =200πrad/s,ξ=0.707,
Figure BDA00037680658300000611
k p and k i Proportional coefficient and integral coefficient of PI controller; g PLL (s) is the transfer function of the phase locked loop;
Figure BDA00037680658300000612
the voltage is a stable value of a positive sequence component of the grid-connected voltage of the system;
Figure BDA00037680658300000613
is the dynamic of the q-axis component of the positive sequence voltage of the grid-connected point, and can be formed by a positive sequence current loop
Figure BDA00037680658300000614
The difference between the actual value and 0. Where theta is pll+ Is the output of the phase-locked loop, θ pll+ =-θ pll- (ii) a Phase locked loop output dynamics delta theta pll+ Cannot be directly measured, but can be calculated by the formulas (1) and (2).
A2 Output dynamic delta theta of phase locked loop pll+ To system d-axis positive sequence grid-connected voltage
Figure BDA00037680658300000615
Output current
Figure BDA00037680658300000616
And an output voltage
Figure BDA00037680658300000617
System q-axis positive sequence grid-connected voltage
Figure BDA00037680658300000618
Output current
Figure BDA00037680658300000619
And an output voltage
Figure BDA00037680658300000620
Is calculated according to equation (3):
Figure BDA00037680658300000621
in the formula (I), the compound is shown in the specification,
Figure BDA00037680658300000622
and
Figure BDA00037680658300000623
expressing the dynamics of the positive sequence grid-connected voltage, the output current and the output voltage of the d axis of the system when the phase-locked loop does not consider the output dynamics;
Figure BDA00037680658300000624
and
Figure BDA00037680658300000625
expressing the dynamics of the q-axis positive sequence grid-connected voltage, the output current and the output voltage of the system when the phase-locked loop outputs the dynamics;
Figure BDA00037680658300000626
and
Figure BDA00037680658300000627
representing the dynamics of the positive sequence grid-connected voltage, the output current and the output voltage of a system d axis when the phase-locked loop outputs the dynamics;
Figure BDA0003768065830000071
and
Figure BDA0003768065830000072
representing the dynamics of the q-axis positive sequence grid-connected voltage, the output current and the output voltage of the system when the phase-locked loop outputs the dynamics;
Figure BDA0003768065830000073
and
Figure BDA0003768065830000074
stable values of a d-axis positive sequence component of the system positive sequence grid-connected voltage, the output current and the output voltage are obtained;
Figure BDA0003768065830000075
and
Figure BDA0003768065830000076
the stable values of the q-axis positive sequence component of the system positive sequence grid-connected voltage, the output current and the output voltage are obtained;
a3 Substituting formula (2) into formula (3) to calculate formula (4):
Figure BDA0003768065830000077
a4 Subtract the compensation term at the output of the positive sequence current loop
Figure BDA0003768065830000078
And
Figure BDA0003768065830000079
subtracting the compensation term at the input of the positive sequence current loop
Figure BDA00037680658300000710
Respectively eliminating the positive sequence grid-connected voltage of the phase-locked loop output dynamic pair system obtained in A3)
Figure BDA00037680658300000711
Output current
Figure BDA00037680658300000712
And an output voltage
Figure BDA00037680658300000713
Dynamic interference of (2). Wherein
Figure BDA00037680658300000714
Figure BDA00037680658300000715
Figure BDA00037680658300000716
The vector expression form of the positive sequence grid-connected voltage, the output current and the output voltage of the system is adopted;
Figure BDA00037680658300000717
the vector expression form of the stable values of the positive sequence grid-connected voltage, the output current and the output voltage of the system is adopted.
(B) Compensating the influence of disturbance caused by a phase-locked loop under the asymmetric voltage drop fault on a negative sequence control system of the grid-connected converter, wherein the specific control steps are as follows:
b1 Output dynamic delta theta of phase locked loop pll+ Negative sequence grid-connected voltage for system d shaft
Figure BDA00037680658300000718
Output current
Figure BDA00037680658300000719
And an output voltage
Figure BDA00037680658300000720
System q-axis negative sequence grid-connected voltage
Figure BDA00037680658300000721
Output current
Figure BDA00037680658300000722
And an output voltage
Figure BDA00037680658300000723
Is calculated as in equation (5):
Figure BDA00037680658300000724
in the formula (I), the compound is shown in the specification,
Figure BDA0003768065830000081
and
Figure BDA0003768065830000082
expressing the dynamics of the negative sequence grid-connected voltage, the output current and the output voltage of the system d-axis when the phase-locked loop outputs the dynamics;
Figure BDA0003768065830000083
and
Figure BDA0003768065830000084
expressing the dynamics of the q-axis negative sequence grid-connected voltage, the output current and the output voltage of the system when the phase-locked loop outputs the dynamics;
Figure BDA0003768065830000085
and
Figure BDA0003768065830000086
representing the dynamics of the negative sequence grid-connected voltage, the output current and the output voltage of a system d-axis when the output dynamics of the phase-locked loop are considered;
Figure BDA0003768065830000087
and
Figure BDA0003768065830000088
representing the dynamics of the q-axis negative sequence grid-connected voltage, the output current and the output voltage of the system when the phase-locked loop outputs the dynamics;
Figure BDA0003768065830000089
and
Figure BDA00037680658300000810
stable values of the d-axis positive sequence component of the system negative sequence grid-connected voltage, the output current and the output voltage are obtained;
Figure BDA00037680658300000811
and
Figure BDA00037680658300000812
stable values of q-axis positive sequence components of the system negative sequence grid-connected voltage, the output current and the output voltage are obtained;
b2 Substituting formula (2) into formula (5) to calculate formula (6):
Figure BDA00037680658300000813
b3 Subtract the compensation term at the output of the negative sequence current loop
Figure BDA00037680658300000814
And
Figure BDA00037680658300000815
subtracting the compensation term at the input of the negative-sequence current loop
Figure BDA00037680658300000816
Respectively eliminating negative sequence grid-connected voltage of phase-locked loop output dynamic pair system obtained in B2)
Figure BDA00037680658300000817
Output current
Figure BDA00037680658300000818
And an output voltage
Figure BDA00037680658300000819
Dynamic interference of (2). Wherein
Figure BDA00037680658300000820
Figure BDA00037680658300000821
Figure BDA00037680658300000822
Figure BDA00037680658300000823
The vector expression form of the system negative sequence grid-connected voltage, the output current and the output voltage is adopted;
Figure BDA00037680658300000824
the vector expression form of the stable values of the system negative sequence grid-connected voltage, the output current and the output voltage is adopted.
The results of the implementation of step A4) and step B3) together constitute the control object of the present invention.
Description of the effects of the invention:
fig. 4 shows a comparison diagram of simulation waveforms of the grid-connected converter when a small signal stability enhancement control strategy is present or absent in the case of an asymmetric voltage drop fault. U shape gabc For grid-connected converter system grid-connected point three-phase voltage, I gabc And outputting three-phase current for the grid-connected converter system. In the figure, the two-phase voltages of the system a and the system b drop when 1.5 s-2.5 s, and the phase voltage of the system c is kept constant. Wherein (a) and (b) are three-phase voltage and output of grid-connected point when small signal stability enhancement control strategy is not adoptedAnd (d) is a waveform diagram when a small signal stability enhancement control strategy is applied. It can be seen from the figure that when a small signal stability enhancement control strategy is not adopted, the small signal instability phenomenon occurs in the system during the fault period, and the small signal stability and the fault ride-through success rate of the grid-connected converter system are reduced. After the small signal stability enhancement control strategy is adopted, the small signal stability of the system during the fault period is effectively improved, the small signal instability phenomenon is avoided, and the fault ride-through success rate is improved.
In summary, the invention provides a small signal stability enhancement control strategy for a grid-connected converter under the asymmetric voltage drop fault of a weak grid, and the strategy has the following beneficial effects: the stability of the small signal of the system during the asymmetric voltage drop fault is enhanced, the phenomenon of small signal instability possibly occurring during the fault is avoided, and the success rate of fault ride-through is improved.
Finally, it should be noted that the above-mentioned examples of the present invention are only examples for illustrating the present invention, and are not intended to limit the embodiments of the present invention. Although the present invention has been described in detail with reference to preferred embodiments, it will be apparent to those skilled in the art that other variations and modifications can be made based on the above description. It is not exhaustive here for all embodiments. All obvious changes and modifications of the present invention are within the scope of the present invention.

Claims (1)

1. The small signal stability enhancement control strategy of the grid-connected converter under the weak grid asymmetric voltage drop fault is characterized in that: the influence of disturbance caused by a phase-locked loop under the asymmetric voltage drop fault on a positive sequence control system and a negative sequence control system of the grid-connected converter is respectively compensated, so that the small signal stability of the system during the asymmetric voltage drop fault is enhanced;
(A) Compensating the influence of disturbance caused by a phase-locked loop under the asymmetric voltage drop fault on a grid-connected converter positive sequence control system, wherein the specific control steps are as follows:
a1 ) is pressedThe dynamic delta theta of the phase-locked loop output is calculated by the formula (1) and the formula (2) pll+
Figure FDA0003768065820000011
Figure FDA0003768065820000012
In the formula, G N (s) and G PI_PLL (s) a frequency doubling trap transfer function and a PI controller transfer function respectively applied in the phase locked loop,
Figure FDA0003768065820000013
ω 0 =200πrad/s,ξ=0.707,
Figure FDA0003768065820000014
k p and k i Proportional coefficient and integral coefficient of PI controller; g PLL (s) is the transfer function of the phase locked loop;
Figure FDA0003768065820000015
the stable value of the positive sequence component of the grid-connected voltage of the system is obtained;
Figure FDA0003768065820000016
is the dynamic of the q-axis component of the positive sequence voltage of the grid-connected point, and is formed by a positive sequence current loop
Figure FDA0003768065820000017
The difference between the actual value and 0;
a2 Output dynamic delta theta of phase locked loop pll+ To system d-axis positive sequence grid-connected voltage
Figure FDA0003768065820000018
Output current
Figure FDA0003768065820000019
And an output voltage
Figure FDA00037680658200000110
System q-axis positive sequence grid-connected voltage
Figure FDA00037680658200000111
Output current
Figure FDA00037680658200000112
And an output voltage
Figure FDA00037680658200000113
Is calculated as in equation (3):
Figure FDA00037680658200000114
in the formula (I), the compound is shown in the specification,
Figure FDA00037680658200000115
and
Figure FDA00037680658200000116
expressing the dynamics of the positive sequence grid-connected voltage, the output current and the output voltage of the d axis of the system when the phase-locked loop does not consider the output dynamics;
Figure FDA00037680658200000117
and
Figure FDA00037680658200000118
expressing the dynamics of the q-axis positive sequence grid-connected voltage, the output current and the output voltage of the system when the phase-locked loop outputs the dynamics;
Figure FDA00037680658200000119
and
Figure FDA00037680658200000120
representing the dynamics of the positive sequence grid-connected voltage, the output current and the output voltage of a system d axis when the phase-locked loop outputs the dynamics;
Figure FDA00037680658200000121
and
Figure FDA00037680658200000122
representing the dynamics of the q-axis positive sequence grid-connected voltage, the output current and the output voltage of the system when the phase-locked loop outputs the dynamics;
Figure FDA00037680658200000123
and
Figure FDA00037680658200000124
a stable value of a d-axis positive sequence component of the grid-connected voltage, the output current and the output voltage is a system positive sequence grid-connected voltage;
Figure FDA00037680658200000125
and
Figure FDA00037680658200000126
the stable values of the q-axis positive sequence component of the system positive sequence grid-connected voltage, the output current and the output voltage are obtained;
a3 Substituting formula (2) into formula (3) to calculate formula (4):
Figure FDA0003768065820000021
a4 Subtract the compensation term at the output of the positive sequence current loop
Figure FDA0003768065820000022
And
Figure FDA0003768065820000023
in the positive-sequence current loopInput subtracting compensation term
Figure FDA0003768065820000024
Respectively eliminating the positive sequence grid-connected voltage of the phase-locked loop output dynamic pair system obtained in A3)
Figure FDA0003768065820000025
Output current
Figure FDA0003768065820000026
And an output voltage
Figure FDA0003768065820000027
Dynamic interference of (2); wherein
Figure FDA0003768065820000028
Figure FDA0003768065820000029
Figure FDA00037680658200000210
The vector expression form of the positive sequence grid-connected voltage, the output current and the output voltage of the system is adopted;
Figure FDA00037680658200000211
the vector expression form of the stable values of the positive sequence grid-connected voltage, the output current and the output voltage of the system is adopted;
(B) The method is used for compensating the influence of disturbance on a grid-connected converter negative sequence control system caused by a phase-locked loop under the asymmetric voltage drop fault, and comprises the following specific control steps:
b1 Output dynamic delta theta of phase locked loop pll+ Negative sequence grid-connected voltage for system d axis
Figure FDA00037680658200000212
Output current
Figure FDA00037680658200000213
And an output voltage
Figure FDA00037680658200000214
System q-axis negative sequence grid-connected voltage
Figure FDA00037680658200000215
Output current
Figure FDA00037680658200000216
And an output voltage
Figure FDA00037680658200000217
Is calculated according to equation (5):
Figure FDA00037680658200000218
in the formula (I), the compound is shown in the specification,
Figure FDA00037680658200000219
and
Figure FDA00037680658200000220
expressing the dynamics of the negative sequence grid-connected voltage, the output current and the output voltage of the system d-axis when the phase-locked loop outputs the dynamics;
Figure FDA00037680658200000221
and
Figure FDA00037680658200000222
expressing the dynamics of the q-axis negative sequence grid-connected voltage, the output current and the output voltage of the system when the phase-locked loop outputs the dynamics;
Figure FDA00037680658200000223
and
Figure FDA00037680658200000224
representing the dynamics of the negative sequence grid-connected voltage, the output current and the output voltage of a system d shaft when the phase-locked loop outputs the dynamics;
Figure FDA00037680658200000225
and
Figure FDA00037680658200000226
representing the dynamics of the q-axis negative sequence grid-connected voltage, the output current and the output voltage of the system when the phase-locked loop outputs the dynamics;
Figure FDA0003768065820000031
and
Figure FDA0003768065820000032
stable values of the d-axis positive sequence component of the system negative sequence grid-connected voltage, the output current and the output voltage are obtained;
Figure FDA0003768065820000033
and
Figure FDA0003768065820000034
stable values of q-axis positive sequence components of the system negative sequence grid-connected voltage, the output current and the output voltage are obtained;
b2 Substituting formula (2) into formula (5) to calculate formula (6):
Figure FDA0003768065820000035
b3 Subtract the compensation term at the output of the negative sequence current loop
Figure FDA0003768065820000036
And
Figure FDA0003768065820000037
subtracting a compensation term at the input of the negative sequence current loop
Figure FDA0003768065820000038
Respectively eliminating negative sequence grid-connected voltage of phase-locked loop output dynamic pair system obtained in B2)
Figure FDA0003768065820000039
Output current
Figure FDA00037680658200000310
And an output voltage
Figure FDA00037680658200000311
Dynamic interference of (2); wherein
Figure FDA00037680658200000312
Figure FDA00037680658200000313
Figure FDA00037680658200000314
The vector expression form of the system negative sequence grid-connected voltage, the output current and the output voltage is adopted;
Figure FDA00037680658200000315
the vector expression form of the stable values of the system negative sequence grid-connected voltage, the output current and the output voltage is adopted.
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