CN115205099A

CN115205099A - Image data transmission method and device and electronic equipment

Info

Publication number: CN115205099A
Application number: CN202210573879.3A
Authority: CN
Inventors: 谢梓敏
Original assignee: Vivo Mobile Communication Co Ltd
Current assignee: Vivo Mobile Communication Co Ltd
Priority date: 2022-05-24
Filing date: 2022-05-24
Publication date: 2022-10-18
Also published as: WO2023226845A1

Abstract

The application discloses an image data transmission method, an image data transmission device and electronic equipment, and belongs to the technical field of communication. Acquiring image data format information; determining an address offset according to the image data format information; acquiring first address information of each transmission of image data; and transmitting the image data according to the first address information and the address offset of each transmission, wherein when the image data of one line is transmitted, the first address of the line is added with the address offset to jump to the first address of the next line, and the image data of the next line is transmitted.

Description

Image data transmission method and device and electronic equipment

Technical Field

The application belongs to the technical field of communication, and particularly relates to an image data transmission method and device and electronic equipment.

Background

In some scenarios, the image processing module processes the image data in units of pixel blocks as needed, and the image data collected by the camera is transmitted and stored in rows. When an Advanced eXtensible Interface (AXI) is used to transport image data, the first address of each burst transfer needs to be set in a way of storing data in a memory line by line, but at the same time, the necessary adjustment needs to be performed according to the format of a required data block.

In a mode, it is assumed that data of 8 clocks is burst-transferred at a time, which is equivalent to data of 64 pixels in one line being read at a time, and the data are stored in a continuous section starting from a specified address, but this mode needs to prepare an extra data storage space, backup the data of 64 pixels in each line being read, and convert the data into 8 × 8 data blocks for processing; in another mode, it is assumed that only 1 clock of data is processed in one burst transfer, which is equivalent to reading 8 pixels of data in one row at a time, and then sending the storage address of the next row of data through the address channel to continue reading the data of 8 pixels in the next row, but this mode needs to send the address information multiple times to read the data of 8 pixels required by each row, thereby forming an 8 × 8 data block, and the overall transfer efficiency is too low.

Therefore, when the existing image data block is transmitted, the problem of low transmission efficiency exists under the condition of not increasing the buffer memory space.

Disclosure of Invention

The embodiment of the application aims to provide an image data transmission method, an image data transmission device and electronic equipment, which can solve the problem of low transmission efficiency under the condition of not increasing a cache storage space when the existing image data block is transmitted.

In a first aspect, an embodiment of the present application provides an image data transmission method, where the method includes:

acquiring image data format information;

determining an address offset according to the image data format information;

acquiring first address information of each transmission of image data;

and transmitting the image data according to the first address information and the address offset of each transmission, wherein when the image data of one line is transmitted, the first address of the line is added with the address offset to jump to the first address of the next line and transmit the image data of the next line.

In a second aspect, an embodiment of the present application provides an image data transmission apparatus, including:

the first acquisition module is used for acquiring image data format information;

the first determining module is used for determining the address offset according to the image data format information;

the second acquisition module is used for acquiring the first address information of each transmission of the image data;

and the transmission module is used for transmitting the image data according to the first address information and the address offset of each transmission, wherein when one line of image data is transmitted, the first address of the line is added with the address offset to jump to the first address of the next line and transmit the next line of image data.

In a third aspect, an embodiment of the present application provides an electronic device, which includes a processor and a memory, where the memory stores a program or instructions executable on the processor, and the program or instructions, when executed by the processor, implement the steps of the image data transmission method according to the first aspect.

In a fourth aspect, the present application provides a readable storage medium, on which a program or instructions are stored, which when executed by a processor implement the steps of the image data transmission method according to the first aspect.

In a fifth aspect, an embodiment of the present application provides a chip, where the chip includes a processor and a communication interface, where the communication interface is coupled to the processor, and the processor is configured to execute a program or instructions to implement the image data transmission method according to the first aspect.

In a sixth aspect, the present application provides a computer program product, which is stored in a storage medium and executed by at least one processor to implement the image data transmission method according to the first aspect.

In the embodiment of the application, image data format information is acquired; determining an address offset according to the image data format information; acquiring first address information of each transmission of image data; and transmitting the image data according to the first address information and the address offset of each transmission, wherein the first address of the line is added with the address offset after each line of image data is transmitted so as to jump to the first address of the next line and transmit the next line of image data. Therefore, by determining the address offset, the transmission address of the next line of image data can be automatically jumped to according to the first address information and the address offset during transmission, so that the continuous transmission of multiple lines of image data is realized, and the transmission efficiency of the image data block can be improved without increasing the storage space for caching.

Drawings

Fig. 1a is a schematic diagram of an AXI bus transmitting image data with different burst transmission lengths according to an embodiment of the present application;

fig. 1b is a second schematic diagram of an AXI bus according to an embodiment of the present application, which transmits image data with different burst transmission lengths;

fig. 2 is an exemplary diagram of image processing from top left to bottom right in units of 8 × 8 pixel blocks according to an embodiment of the present application;

fig. 3 is an exemplary diagram illustrating transmission and storage of image data of a camera in a unit of a line according to an embodiment of the present application;

FIG. 4 is a diagram illustrating JPEG image compression processed in units of 8 x 8 pixel blocks according to an embodiment of the present application;

fig. 5 is an exemplary diagram of skipping an AXI bus in each line for image data transmission to meet the format requirement of a pixel block according to an embodiment of the present application;

FIG. 6 is a flowchart of an image data transmission method provided in an embodiment of the present application;

figure 7 is a schematic diagram of an AXI address space mapping module provided by an embodiment of the present application in a data stream;

fig. 8 is a schematic diagram of an AXI address space mapping module according to an embodiment of the present application;

fig. 9 is a diagram illustrating an example of continuously reading 8 rows of image data according to AXI address information by address mapping according to an embodiment of the present application;

FIG. 10 is a schematic diagram of an image data transmission apparatus according to an embodiment of the present application;

fig. 11 is a schematic block diagram of an electronic device according to an embodiment of the present application;

fig. 12 is a schematic hardware structure diagram of an electronic device according to an embodiment of the present application.

Detailed Description

Technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived from the embodiments in the present application by a person skilled in the art, are within the scope of protection of the present application.

The terms first, second and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that embodiments of the application may be practiced otherwise than as shown or described herein and the terms "first," "second," and the like are used generically and do not limit the number of terms to which they may be applied, e.g., the first term may refer to one or more than one term. Further, in the specification and claims, "and/or" means at least one of the connected objects, the character "/" generally means a relationship that preceding and succeeding related objects are an "or".

In order to make the embodiments of the present application clearer, the following briefly introduces the technical background of the embodiments of the present application with reference to several examples:

in the process of image processing, the image processing chip needs to process image data in the form of image data blocks in some scenes. For example, fig. 2 is an example of processing from the top left to the bottom right of an image in units of 8 × 8 data blocks.

And the image data collected by the Camera is transmitted by taking each line of data as a unit according to the Camera Serial Interface 2 (CSI-2) specification. When image data transmitted from the camera is stored in the memory, the image data is generally stored line by line according to a mode suggested by a specification, and a next line is stored after one line of data is stored completely. For example, in fig. 3, the data of the whole line of the first line is processed first, then the data of the next line is processed, and then the data of the third line is processed, and the processing is performed sequentially from top left to bottom right line by line.

In the process of processing the image data by the image processing chip, the image data can be transmitted and processed between different modules and between the modules and the memory according to needs.

The AXI bus is a widely used bus protocol for data transfer between the chip's internal processing modules and memory. When an image data block is transferred between an image processing module and a memory, an AXI bus is often used to transfer data. For example, image data is read from the memory and sent to the image processing module for processing, or image data output by the image processing module is written into the memory.

The AXI bus has an address channel that specifies a head address of a memory to be accessed, and a data channel that sequentially writes or reads data from the head address set by the address channel. Under the burst transmission mode, data of a plurality of clock cycles can be transmitted on the data channel, and the data transmission efficiency is improved.

Among them, a Joint Photographic Experts Group (JPEG) image processing module is an example of processing image data according to a data block, JPEG is a widely used still image compression standard, and in the standard mode, as shown in fig. 4, processing of a compressed image is performed block by block from the top left to the bottom right of an image with 8 × 8 pixel blocks as a unit. The color space YCbCr may also be a pixel block unit of 16 × 8 (YCbCr =4 2) or 16 × 16 (YCbCr = 4. Of course, the method mentioned in this application is not only applicable to JPEG, but also applicable to all modules that need to process data according to image data blocks.

When the AXI bus is used to transport image data, the head address of each burst transfer needs to be set in a manner of storing data in a memory in a line, but at the same time, needs to be adjusted as necessary according to the format of a required data block. In the following, an 8 × 8 data block is taken as an example, and other data blocks may be processed in a similar manner.

For example, when processing the 8 × 8 data block in the upper left corner in fig. 5, the AXI bus must first read the 8 pixels of data starting from column 1 in row 1, then jump-transfer the 8 pixels of data starting from column 1 in row 2, and so on until the 8 pixels of data starting from column 1 in row 8 are transferred. When the 8 pixel data of the 1 st to 8 th lines are all transmitted, the data transmission of the 8 × 8 pixel block is completed.

There are various specifications of pixel depth of image data such as 8, 10, 12, 14, 16, and the like. The data bit width of the AXI data channel is currently 64 or 128 bits, and burst transmission can perform data transmission of 4, 8, 16, and so on clocks.

Fig. 1a and 1b are simple exemplary diagrams when AXI reads image data. Taking the pixel depth of the image data as 8 bit depth as an example, the data of 8 pixels in a row is 64 bits at this time. Assuming that the data bit width of AXI is 64 bits, then 8 bits deep, 8 pixels per line of image data is transferred, requiring only 1 clock of transfer to be performed per burst transfer. AXI in fig. 1a burst transfers 8 clocks of data at a time, which is equivalent to reading 64 pixels of data in a row at a time, which are stored in consecutive intervals starting at a specified address; while the burst transfer in fig. 1b only processes 1 clock of data at a time, which is equivalent to reading 8 pixels of data in one row at a time, and then sending the storage address of the next row of data through the address channel to continue reading the data of the next row of 8 pixels.

From the examples of fig. 1a and 1b, it can be known that multiple data can be read by one burst transmission in the method of fig. 1a, which can improve the efficiency of AXI data transmission, but an extra data storage space needs to be prepared, the read data of 64 pixels per line is backed up, and then converted into 8 × 8 data blocks to be sent to the image processing module for processing. If the method in fig. 1b is used, only 8 pixels of data in each row are read in each burst transmission, and the 8 pixels of data required in each row are read by sending address information multiple times, so as to form an 8 × 8 data block, but at this time, each burst transmission only needs to transmit one clock cycle and address information needs to be transmitted each time, and the overall transmission efficiency is too low.

According to the sequence of the image data block during processing and storing in the memory and the transmission characteristics of the AXI address and the data channel, the embodiment of the application provides a scheme for efficiently transmitting the image data block, so that the aim of improving the transmission efficiency of the image data block is fulfilled while the storage space for caching is not increased.

The image data transmission method provided by the embodiment of the present application is described in detail below with reference to the accompanying drawings through specific embodiments and application scenarios thereof.

Referring to fig. 6, fig. 6 is a flowchart of an image data transmission method according to an embodiment of the present application, and as shown in fig. 6, the method includes the following steps:

step 601, obtaining image data format information.

The embodiment of the application can be applied to a scene of transmitting the image data block on the AXI bus.

In the embodiment of the application, the conversion of the address mapping space can be performed when the memory is actually accessed according to the first address information specified by the AXI address channel, and after the pixel data required by one line of data is read, the address is jumped to the address of the next line of data to continuously read the pixel data required by the next line, so that the data of the data block required by image data processing is continuously read.

Specifically, as shown in fig. 7, an AXI address space mapping module may be added between the AXI bus data transmission processing module and the memory, and when the AXI bus data transmission processing module accesses the memory, the address space mapping is performed, so as to continuously read data of a data block required by the image processing module. The internal structure diagram and the data flow information of the AXI address space mapping module may be as shown in fig. 8.

To implement the mapping of the address space, image data format information may be first obtained to determine an address offset according to the image data format information. Specifically, relevant image data format information, such as information of the size of the transferred image data block, the pixel depth, the number of pixels per line, and the like, can be acquired at the time of initial configuration.

For example, when the application layer performs initialization configuration on the relevant modules including the image processing module, the AXI address space mapping module also obtains the image data format information, including the size of the image data block, the data type, the pixel depth, the number of pixels per line, the address space for storing each pixel component per line, and the like.

Step 602, determining an address offset according to the image data format information.

The AXI address mapping module can calculate the clock number required for completing the transmission of the pixel data required by each line and the address offset of the image data of each line in the memory according to the obtained image data format information, namely, the address required to be jumped when jumping to the next line after the transmission of the pixel number required by each line. In addition, the Y/Cb/Cr components may be similarly processed by component depending on the type of image data.

Optionally, the image data format information includes a pixel depth and a number of pixels per line;

the step 602 includes:

and determining the address offset according to the product of the pixel depth and the number of pixels in each row.

That is, in one embodiment, the image data format information includes a pixel depth and a number of pixels per line, and the address offset may be determined according to a product of the pixel depth and the number of pixels per line.

For example, if the image pixel depth is 8 bits, the image has 128 pixels per line, the data of each pixel component is stored in a designated address space, and the pixels of each line are stored continuously, the data amount of each pixel component per line can be determined to be 8 bits × 128 pixels =1024 bits, and thus the address offset can be determined to be 1024 bits.

Thus, according to the embodiment, the address offset can be quickly determined based on the product of the pixel depth and the number of pixels in each row under the condition that the pixels in each row are continuously stored, and further, the continuous transmission of image data in a plurality of rows is realized.

Optionally, the image data format information includes address space information occupied by each row of pixels;

the determining an address offset according to the image data format information includes:

determining the size of the address space of each line according to the address space information occupied by the pixels of each line;

and determining the size of the address space of each line as the address offset.

In another embodiment, the image data format information may include address space information occupied by each row of pixels, that is, when the pixels of different rows of each component are not uninterruptedly stored in a continuous address interval, but specify an address space of each row, an address offset may be directly determined according to the size of the address space of each row.

For example, the pixels of different rows of each component are not stored continuously in a 1024-bit continuous address interval, but each row is assigned with an address space of 2048 bits, so that each row occupies only the first 1024 bits of the assigned 2048-bit address space, and when jumping to the next row for transmission, the 2048-bit offset needs to be added, i.e., the address offset can be determined to be 2048 bits.

Thus, according to the embodiment, under the condition that the pixels of each row are not stored continuously, the address offset can be determined based on the size of the address space occupied by the pixels of each designated row, and then the continuous transmission of image data of a plurality of rows can be realized.

And step 603, acquiring the first address information of each transmission of the image data.

In this step, the AXI address space mapping module may fetch the first address of each burst transfer from the AXI bus address channel, including reading or writing memory data to memory. It should be noted that, in the embodiment of the present application, data of one or more clock cycles may be transmitted at a time, one image data block includes multiple lines of data, transmission of one line of data requires one or more clock cycles, and the number of times required to complete transmission of one image data block is correspondingly different according to the number of clock cycles transmitted at a time. When the clock period number of one transmission can finish transmitting one image data block, only one burst transmission is needed to transmit one image data block, and when the clock period number of one transmission can only finish transmitting a plurality of lines in one image data block, the burst transmission is needed to transmit one image data block for a plurality of times.

Optionally, before the step 603, the method further includes:

determining the clock period number of each transmission processing of the image data;

the step 603 includes:

determining the transmission times required for transmitting one image data block according to the clock period number, the size of the image data block in the image data format information and the bit width of transmission data;

and acquiring the first address information of each transmission in the transmission times.

In one embodiment, the number of transmission times required for transmitting one image data block may be determined according to the number of clock cycles of each burst transmission, the size of the image data block, and the bit width of the transmission data, and the first address information of each transmission may be obtained based on the number of transmission times.

Specifically, the number of clock cycles of each burst transfer process of the AXI may be determined, which may be generally preset by a system, and then the number of data lines that can be transferred in one burst transfer may be determined according to the number of clock cycles of one transfer process, size information of the image data block, and bit width of the transfer data, so as to calculate the number of transfer times required for transferring one image data block.

For example, assuming that the image data block size is 8 × 8, the axi and the data bit width of the memory are both 64 bits, and the image pixel depth is 8 bits, 64 bits of data are processed every clock cycle, which corresponds to a data amount of 8 pixels, that is, one clock cycle can process one line of data. If AXI handles 4 clock cycles per burst transfer, then 4 lines of data can be transferred at a time, requiring 2 transfers of an 8 x 8 block of image data. Thus, starting from the first address specified by the first burst transfer, the data of 8 pixels of the specified row is transferred in the first clock cycle, then the first address is added with a 1024-bit offset, the data of 8 pixels of the next row is read, and so on, the respective 8 pixels of the 4-line data are read. After that, the AXI sends the first address of the fifth row through the address channel again, starts the second transmission, continues to read the subsequent 4 rows of data, and completes the reading of the 8 × 8 data block.

If AXI processes 8 clock cycles per burst transfer, AXI only needs to send address information once to read 8 lines of data, i.e. only one image data block needs to be transferred once.

Thus, by the embodiment, the transmission times required for transmitting one image data block can be determined, the first address information of each transmission is further acquired, and the smooth transmission of the image data is ensured.

Further, the determining the number of transmission times required for transmitting one image data block according to the number of clock cycles, the size of the image data block in the image data format information, and the bit width of the transmission data includes:

determining the number of pixels processed in each clock period according to the pixel depth, the size of the image data block and the bit width of the transmission data in the image data format information;

and determining the transmission times required for transmitting one image data block according to the pixel number processed in each clock cycle and the clock cycle number.

In this embodiment, the image data format information may include a pixel depth, an image data block size, and a transmission data bit width, so that the number of pixels processed in each clock cycle may be determined according to the pixel depth, the image data block size, and the transmission data bit width, and the number of transmission times required to transmit one image data block may be determined according to the number of pixels processed in each clock cycle and the number of clock cycles of one transmission process.

For example, assuming that the image data block size is 8 × 8, the axi and the data bit width of the memory are 64 bits, the image pixel depth is 8 bits, and 64 bits of data can be processed every clock cycle, which corresponds to a data amount of 8 pixels, that is, one clock cycle can process one line of data. If AXI processes 4 clock cycles per burst transfer, then 4 lines of data can be transferred at a time, requiring 2 transfers of an 8 x 8 block of image data.

If the image pixel depth is 16 bits, then 64 bits of data per clock is equivalent to a data size of 4 pixels, and then 8 pixels of data per line would require 2 clock cycles to complete. If AXI handles 4 clock cycles per burst transfer, only 2 lines of data can be transferred at a time, and 4 transfers of an 8 x 8 block of image data are required.

Thus, with this embodiment, the number of transmissions required to transmit one image data block can be determined more accurately.

And step 604, transmitting image data according to the first address information and the address offset of each transmission, wherein when one line of image data is transmitted, the first address of the line is added with the address offset to jump to the first address of the next line and transmit the next line of image data.

In this step, the image data transfer module in the AXI address space mapping module transfers image data according to the memory address specified by the address space mapping.

Specifically, in this embodiment of the present application, when actually accessing the memory, address space mapping is performed according to the characteristics of the processed image data block, instead of the default continuous increment manner of the AXI bus, after processing the pixel data required by the current line from the first address, the address of the next line is skipped according to the address offset (that is, the address of the next line = the start address of the previous line + the address offset of the data of the line), the pixel data required by the next line is continuously processed, and the processing is performed line by line until all the transmission clocks of one burst transmission are completed. And then, according to the first address information and the address offset of the next transmission, similar line-by-line processing is carried out until the data of one image data block is transmitted.

Optionally, the step 604 includes:

transmitting image data of a jth line where the first address information is located according to the first address information transmitted for the ith time, wherein i is an integer greater than or equal to 1, and j is a positive integer;

adding the address offset to the first address information transmitted for the ith time to obtain the first address information of a j +1 th line;

transmitting the image data of the j +1 th line according to the first address information of the j +1 th line;

and when the image data of one line is transmitted, adding the address offset to the first address of the line, and starting the transmission of the image data of the next line until the ith transmission is completed.

That is, when image data is transmitted according to the first address information and the address offset of each transmission, for the ith burst transmission, the image data of the line where the first address information is located may be transmitted according to the first address information of the ith transmission, after the transmission of the line of image data is completed, the first address of the ith transmission may be added with the address offset, and the transmission may be shifted to the transmission of the image data of the next line, and so on, after the transmission of one line of image data is completed, the address of the line is added with the address offset, and the image data of the next line is transmitted until the ith transmission is completed. Under the condition that the ith transmission is not the last transmission, the first address information of the (i + 1) th transmission can be acquired, and the (i + 1) th transmission is completed in a manner similar to the ith transmission until the transmission of one image data block is completed.

Thus, with this embodiment, it can be ensured that each image data transfer is completed in order.

It should be noted that, for a scene that needs to transmit a plurality of image data blocks, transmission of each image data block may be sequentially completed according to the transmission manner of one image data block described in the embodiment of the present application.

Assuming that the size of an image data block is 8 × 8, the axi and the data bit width of the memory are 64 bits, the image has a depth of 8 bits, each line of the image has 128 pixels, the data of each pixel component is stored in a designated address space, and the pixels of each line are stored continuously. At this time, 64 bits of data are processed every clock cycle, corresponding to a data amount of 8 pixels. The amount of data per pixel component line is 8 bits × 128 pixels =1024 bits.

If AXI processes 4 clock cycles per burst transfer, the data for 8 pixels of a given row is transferred in the first clock cycle starting with the specified head address, then the head address is added with a 1024-bit offset, the data for 8 pixels of the next row is read, and so on for each 8 pixels of the 4 rows of data. After that, the AXI sends the first address of the fifth row through the address channel again, and continues to read the subsequent 4 rows of data, thereby completing the reading of the 8 × 8 data block.

If AXI processes 8 clock cycles per burst transfer, then AXI only needs to send address information once to read 8 rows of data.

If the depth of the image is 16 bits in the above conditions, and other conditions are not changed, the 64-bit data processed by each clock is only equivalent to the data amount of 4 pixels, and then the data of 8 pixels in each row needs 2 clocks to be processed.

If the pixels of different rows of each component are stored not in a continuous 1024-bit address space, but rather in a 2048-bit address space, under the above conditions, each row will occupy only the first 1024 bits of the specified 2048-bit address space, and thus a 2048-bit offset will need to be added when jumping to the next row.

It should be noted that the actual address mapping control can be adjusted in more combinations according to the system requirements, but the idea of address mapping to implement jump by row to read the required data block unit is consistent. The conditions of the right edge, the lower edge and the like of the image are not additionally described, and the system can be automatically adjusted as required during implementation. If the image processing module and the AXI bus are in an asynchronous clock relationship, the data cache required for the middle clock domain crossing processing is not described herein.

The difference between the embodiments of the present application and the prior art is described with reference to fig. 9, which is an exemplary diagram of processing an 8 × 8 data block, where AXI and the data bit width of the memory are both 64 bits, and the image is 8 bits deep, and data is read 8 clock cycles at a time in a burst transfer. In the example of fig. 9, starting with the address of the first row, AXI will by default read the address incrementally, sequentially, reading the data of the first row of 64 pixels. In the example of fig. 9, after the data of 8 pixels in the first row is read, the next clock cycle jumps to the address of the second row to read 8 pixels in the second row through address mapping processing, and so on, 8 pixels in 8 rows of data are read, so that an 8 × 8 data block is formed, and thus, only one burst transmission is needed to complete the processing of one 8 × 8 data block, and the transmission efficiency is greatly improved.

According to the embodiment of the application, the AXI address space mapping module is added between the AXI bus data transmission processing module and the memory, and the address space mapping is carried out when the AXI bus processing module accesses the memory, so that the data of the data block required by image processing can be continuously read, and the purpose of improving the transmission efficiency of the image data block transmitted based on the AXI bus is achieved while the storage space for caching is not increased.

The image data transmission method in the embodiment of the application acquires image data format information; determining an address offset according to the image data format information; acquiring first address information of each transmission of image data; and transmitting image data according to the first address information and the address offset which are transmitted each time, wherein when one line of image data is transmitted, the first address of the line is added with the address offset to jump to the first address of the next line and transmit the next line of image data. Therefore, by determining the address offset, the transmission address of the next line of image data can be automatically jumped to according to the first address information and the address offset during transmission, so that continuous transmission of multiple lines of image data is realized, and the transmission efficiency of the image data block can be improved without increasing the storage space for caching.

In the image data transmission method provided by the embodiment of the application, the execution subject can be image data transmissionDevice for measuring the position of a moving object. In the embodiment of the present application, an image data transmission method executed by an image data transmission device is taken as an example, and the image data transmission device provided in the embodiment of the present application is described.

Referring to fig. 10, fig. 10 is a schematic structural diagram of an image data transmission device according to an embodiment of the present application, and as shown in fig. 10, the image data transmission device 1000 includes:

a first obtaining module 1001, configured to obtain format information of image data;

a first determining module 1002, configured to determine an address offset according to the image data format information;

a second obtaining module 1003, configured to obtain first address information of each transmission of image data;

a transmission module 1004, configured to transmit image data according to the first address information and the address offset for each transmission, where after each line of image data is transmitted, the first address of the line is used to add the address offset to jump to the first address of the next line, so as to transmit the next line of image data.

the first determining module 1002 is configured to determine the address according to a product of the pixel depth and the number of pixels in each row.

the first determining module 1002 includes:

the first determining unit is used for determining the size of the address space of each line according to the address space information occupied by the pixels of each line;

a second determining unit, configured to determine the size of the address space of each row as the address offset.

Optionally, the image data transmission apparatus 1000 further includes:

the second determining module is used for determining the clock period number of each transmission processing of the image data;

the second obtaining module 1003 includes:

a third determining unit, configured to determine the number of transmission times required to transmit one image data block according to the number of clock cycles, the size of the image data block in the image data format information, and a bit width of transmission data;

and the acquisition unit is used for acquiring the first address information of each transmission in the transmission times.

Optionally, the third determining unit includes:

the first determining subunit is configured to determine, according to the pixel depth in the image data format information, the size of the image data block, and the bit width of the transmission data, the number of pixels processed in each clock cycle;

and the second determining subunit is used for determining the transmission times required for transmitting one image data block according to the pixel number processed in each clock cycle and the clock cycle number.

Optionally, the transmission module 1004 includes:

the first transmission unit is used for transmitting the image data of the jth line where the first address information is located according to the ith transmission first address information, wherein i is an integer larger than or equal to 1, and j is a positive integer;

the second transmission unit is used for adding the address offset to the first address information transmitted for the ith time to obtain the first address information of a j +1 th line;

The image data transmission device in the embodiment of the application acquires image data format information; determining an address offset according to the image data format information; acquiring first address information of each transmission of image data; and transmitting the image data according to the first address information and the address offset of each transmission, wherein when the image data of one line is transmitted, the first address of the line is added with the address offset to jump to the first address of the next line and transmit the image data of the next line. Therefore, by determining the address offset, the transmission address of the next line of image data can be automatically jumped to according to the first address information and the address offset during transmission, so that continuous transmission of multiple lines of image data is realized, and the transmission efficiency of image data blocks can be improved without increasing the storage space for caching.

The image data transmission device in the embodiment of the present application may be an electronic device, or may be a component in an electronic device, such as an integrated circuit or a chip. The electronic device may be a terminal, or may be other devices besides a terminal. The electronic Device may be, for example, a Mobile phone, a tablet Computer, a notebook Computer, a palm top Computer, a vehicle-mounted electronic Device, a Mobile Internet Device (MID), an Augmented Reality (AR)/Virtual Reality (VR) Device, a robot, a wearable Device, an Ultra-Mobile Personal Computer (UMPC), a netbook or a Personal Digital Assistant (PDA), and the like, and may also be a server, a Network Attached Storage (NAS), a Personal Computer (PC), a Television (Television, TV), a teller machine, a self-service machine, and the like, and the embodiments of the present application are not particularly limited.

The image data transmission device in the embodiment of the present application may be a device having an operating system. The operating system may be an Android (Android) operating system, an ios operating system, or other possible operating systems, and embodiments of the present application are not particularly limited.

The image data transmission device provided in the embodiment of the present application can implement each process implemented in the method embodiment of fig. 6, and is not described here again to avoid repetition.

Optionally, as shown in fig. 11, an electronic device 1100 is further provided in an embodiment of the present application, and includes a processor 1101 and a memory 1102, where the memory 1102 stores a program or an instruction that can be executed on the processor 1101, and when the program or the instruction is executed by the processor 1101, the steps of the embodiment of the image data transmission method are implemented, and the same technical effects can be achieved, and are not repeated here to avoid repetition.

It should be noted that the electronic device in the embodiment of the present application includes the mobile electronic device and the non-mobile electronic device described above.

Fig. 12 is a schematic hardware structure diagram of an electronic device implementing an embodiment of the present application.

The electronic device 1200 includes, but is not limited to: radio frequency unit 1201, network module 1202, audio output unit 1203, input unit 1204, sensors 1205, display unit 1206, user input unit 1207, interface unit 1208, memory 1209, and processor 1210.

Those skilled in the art will appreciate that the electronic device 1200 may further comprise a power source (e.g., a battery) for supplying power to the various components, and the power source may be logically connected to the processor 1210 via a power management system, so as to implement functions of managing charging, discharging, and power consumption via the power management system. The electronic device structure shown in fig. 12 does not constitute a limitation of the electronic device, and the electronic device may include more or less components than those shown, or combine some components, or arrange different components, and thus, the description is not repeated here.

Wherein, the processor 1210 is configured to:

acquiring image data format information;

determining an address offset according to the image data format information;

acquiring first address information of each transmission of image data;

the processor 1210 is further configured to determine the address offset according to a product of the pixel depth and the number of pixels per row.

a processor 1210 further configured to:

determining the size of the address space of each row as the address offset.

Optionally, the processor 1210 is further configured to:

and determining the transmission times required for transmitting one image data block according to the number of pixels processed in each clock cycle and the number of clock cycles.

Optionally, the processor 1210 is further configured to:

transmitting image data of a jth line where first address information is located according to the first address information transmitted at the ith time, wherein i is an integer larger than or equal to 1, and j is a positive integer;

The electronic equipment in the embodiment of the application acquires image data format information; determining an address offset according to the image data format information; acquiring first address information of each transmission of image data; and transmitting the image data according to the first address information and the address offset of each transmission, wherein when the image data of one line is transmitted, the first address of the line is added with the address offset to jump to the first address of the next line and transmit the image data of the next line. Therefore, by determining the address offset, the method can automatically jump to the transmission address of the next line of image data according to the first address information and the address offset during transmission, thereby realizing continuous transmission of multiple lines of image data and improving the transmission efficiency of image data blocks without increasing the storage space for caching.

It should be understood that, in the embodiment of the present application, the input Unit 1204 may include a Graphics Processing Unit (GPU) 12041 and a microphone 12042, and the Graphics Processing Unit 12041 processes image data of still pictures or videos obtained by an image capturing device (such as a camera) in a video capturing mode or an image capturing mode. The display unit 1206 may include a display panel 12061, and the display panel 12061 may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like. The user input unit 1207 includes at least one of a touch panel 12071 and other input devices 12072. A touch panel 12071, also referred to as a touch screen. The touch panel 12071 may include two parts, a touch detection device and a touch controller. Other input devices 12072 may include, but are not limited to, a physical keyboard, function keys (e.g., volume control keys, on-off keys, etc.), a trackball, a mouse, and a joystick, which are not described in detail herein.

The memory 1209 may be used to store software programs as well as various data. The memory 1209 may mainly include a first storage area storing programs or instructions and a second storage area storing data, wherein the first storage area may store an operating system, application programs or instructions (such as a sound playing function, an image playing function, etc.) required for at least one function, and the like. Further, the memory 1209 may include volatile memory or nonvolatile memory, or the memory 1209 may include both volatile and nonvolatile memory. The non-volatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable PROM (EEPROM), or a flash Memory. The volatile Memory may be a Random Access Memory (RAM), a Static Random Access Memory (Static RAM, SRAM), a Dynamic Random Access Memory (Dynamic RAM, DRAM), a Synchronous Dynamic Random Access Memory (Synchronous DRAM, SDRAM), a Double Data Rate Synchronous Dynamic Random Access Memory (Double Data Rate SDRAM, ddr SDRAM), an Enhanced Synchronous SDRAM (ESDRAM), a Synchronous Link DRAM (SLDRAM), and a Direct Memory bus RAM (DRRAM). Memory 1209 in the embodiments of the subject application include, but are not limited to, these and any other suitable types of memory.

Processor 1210 may include one or more processing units; optionally, the processor 1210 integrates an application processor, which mainly handles operations related to the operating system, user interface, and application programs, and a modem processor, which mainly handles wireless communication signals, such as a baseband processor. It is to be appreciated that the modem processor described above may not be integrated into processor 1210.

The embodiment of the present application further provides a readable storage medium, where a program or an instruction is stored on the readable storage medium, and when the program or the instruction is executed by a processor, the program or the instruction implements each process of the above-mentioned embodiment of the image data transmission method, and can achieve the same technical effect, and in order to avoid repetition, details are not repeated here.

The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read only memory ROM, a random access memory RAM, a magnetic or optical disk, and the like.

The embodiment of the present application further provides a chip, where the chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is configured to run a program or an instruction to implement each process of the above-mentioned image data transmission method embodiment, and can achieve the same technical effect, and in order to avoid repetition, details are not repeated here.

It should be understood that the chips mentioned in the embodiments of the present application may also be referred to as a system-on-chip, or a system-on-chip.

Embodiments of the present application provide a computer program product, where the program product is stored in a storage medium, and the program product is executed by at least one processor to implement the processes of the foregoing image data transmission method embodiments, and can achieve the same technical effects, and in order to avoid repetition, details are not repeated here.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising," does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Further, it should be noted that the scope of the methods and apparatus in the embodiments of the present application is not limited to performing the functions in the order illustrated or discussed, but may include performing the functions in a substantially simultaneous manner or in a reverse order, depending on the functionality involved, e.g., the methods described may be performed in an order different than that described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

Through the above description of the embodiments, those skilled in the art will clearly understand that the above embodiment method can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the present application may be embodied in the form of a computer software product stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk), and including instructions for enabling a terminal (e.g., mobile phone, computer, server, or network device) to execute the methods according to the embodiments of the present application.

While the present embodiments have been described with reference to the accompanying drawings, it is to be understood that the present invention is not limited to the above-described embodiments, which are intended to be illustrative rather than restrictive, and that various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope of the present invention as defined by the appended claims.

Claims

1. An image data transmission method, comprising:

acquiring image data format information;

determining an address offset according to the image data format information;

acquiring first address information of each transmission of image data;

and transmitting the image data according to the first address information and the address offset of each transmission, wherein when the image data of one line is transmitted, the first address of the line is added with the address offset to jump to the first address of the next line, and the image data of the next line is transmitted.

2. The method of claim 1, wherein the image data format information includes pixel depth and number of pixels per line;

3. The method of claim 1, wherein the image data format information includes address space information occupied by each row of pixels;

determining the size of the address space of each row as the address offset.

4. The method of claim 1, wherein before obtaining the first address information for each transmission of image data, the method further comprises:

the acquiring first address information of each transmission of the image data comprises:

determining the transmission times required for transmitting one image data block according to the clock periodicity, the size of the image data block in the image data format information and the bit width of transmission data;

5. The method of claim 4, wherein determining the number of transmissions required to transmit a block of image data based on the number of clock cycles and the block size and bit width of transmitted data in the image data format information comprises:

6. The method according to any one of claims 1 to 5, wherein the transmitting image data according to the first address information of each transmission and the address offset comprises:

transmitting image data of a jth line where the ith transmission first address information is located according to the ith transmission first address information, wherein i is an integer larger than or equal to 1, and j is a positive integer;

and adding the address offset to the first address of the line after the image data of one line is transmitted, and starting the image data transmission of the next line until the ith transmission is completed.

7. An image data transmission apparatus, characterized by comprising:

8. The image data transmission apparatus according to claim 7, wherein the image data format information includes a pixel depth and a number of pixels per line;

the first determining module is used for determining the address according to the product of the pixel depth and the number of pixels in each row.

9. The image data transmission apparatus according to claim 7, wherein the image data format information includes address space information occupied by each line of pixels;

the first determining module includes:

10. The image data transmission apparatus according to claim 7, characterized in that the image data transmission apparatus further comprises:

the second acquisition module includes:

11. The image data transmission apparatus according to claim 10, wherein the third determination unit includes:

and the second determining subunit is used for determining the transmission times required for transmitting one image data block according to the pixel number processed in each clock cycle and the clock cycles.

12. The image data transmission device according to any one of claims 7 to 11, wherein the transmission module includes:

the first transmission unit is used for transmitting the image data of the jth line where the first address information is located according to the first address information transmitted at the ith time, wherein i is an integer larger than or equal to 1, and j is a positive integer;

13. An electronic device comprising a processor and a memory, the memory storing a program or instructions executable on the processor, the program or instructions when executed by the processor implementing the steps of the image data transmission method according to any one of claims 1 to 6.

14. A readable storage medium, characterized in that the readable storage medium stores thereon a program or instructions which, when executed by a processor, implement the steps of the image data transmission method according to any one of claims 1 to 6.

15. A chip comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, and wherein the processor is configured to execute a program or instructions to implement the steps of the image data transmission method according to any one of claims 1 to 6.