CN115202562A

CN115202562A - Data parallel writing method and data storage system

Info

Publication number: CN115202562A
Application number: CN202110398629.6A
Authority: CN
Inventors: 侯冠宇; 傅子瑜
Original assignee: Acer Inc
Current assignee: Acer Inc
Priority date: 2021-04-12
Filing date: 2021-04-12
Publication date: 2022-10-18

Abstract

The invention provides a data parallel writing method and a data storage system. The method comprises the following steps: evaluating data write performance of the first memory device and the second memory device; determining a first unit write data size of the first memory device and a second unit write data size of the second memory device according to the data write performance, wherein the first unit write data size is different from the second unit write data size; and instructing the first memory device and the second memory device to perform parallel data writing according to the first unit write data amount and the second unit write data amount. Therefore, the parallel data writing efficiency of a data storage system comprising a plurality of memory devices can be improved.

Description

Data parallel writing method and data storage system

Technical Field

The present invention relates to a data parallel writing technology for a memory device, and more particularly, to a data parallel writing method and a data storage system.

Background

As technology advances, the types and versions of memory devices are continually becoming more new. When users install different models or versions of memory devices on the same motherboard for simultaneous use, even though the individual data writing performance of each memory device is good, the parallel data writing performance of the memory devices may not be improved or even slightly reduced due to the operational incompatibility between the memory devices.

Disclosure of Invention

The invention provides a data parallel writing method and a data storage system, which can improve the parallel data writing efficiency of the data storage system comprising a plurality of memory devices.

The embodiment of the invention provides a data parallel writing method which is used for a data storage system. The data storage system includes a first memory device and a second memory device. The data parallel writing method comprises the following steps: evaluating data write performance of the first memory device and the second memory device; determining a first unit write data amount of the first memory device and a second unit write data amount of the second memory device according to the data write performance, wherein the first unit write data amount is different from the second unit write data amount; and instructing the first memory device and the second memory device to perform parallel data writing according to the first unit write data amount and the second unit write data amount.

An embodiment of the present invention further provides a data storage system, which includes a host system, a first memory device and a second memory device. The first memory device is connected to the host system via a first connection interface. The second memory device is connected to the host system via a second connection interface. The host system is used for evaluating the data writing efficiency of the first memory device and the second memory device. The host system is further configured to determine a first unit write data size of the first memory device and a second unit write data size of the second memory device according to the data write performance. The first unit write data amount is different from the second unit write data amount. The host system is further configured to instruct the first memory device and the second memory device to perform parallel data writing according to the first unit write data amount and the second unit write data amount.

Based on the above, after evaluating the respective data writing performances of the first memory device and the second memory device in the data storage system in real time, a first unit writing data amount of the first memory device and a second unit writing data amount of the second memory device can be determined, and the first unit writing data amount is different from the second unit writing data amount. Then, the first memory device and the second memory device are instructed to perform parallel data writing according to the first unit writing data amount and the second unit writing data amount, so that the parallel data writing efficiency of a data storage system comprising a plurality of memory devices can be improved.

Drawings

FIG. 1 is a schematic diagram of a data storage system shown in accordance with an embodiment of the present invention;

FIGS. 2A and 2B are schematic diagrams illustrating evaluation of data write performance of a first memory device according to an embodiment of the invention;

FIGS. 3A and 3B are schematic diagrams illustrating evaluation of data write performance of a second memory device according to an embodiment of the invention;

FIG. 4 is a schematic diagram illustrating a first memory device and a second memory device performing parallel data writing based on a preset unit writing data amount according to an embodiment of the present invention;

FIG. 5 is a diagram illustrating a first memory device and a second memory device performing parallel data writing according to a dynamically determined unit write data size according to an embodiment of the present invention;

fig. 6 is a flowchart illustrating a data parallel writing method according to an embodiment of the present invention.

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

FIG. 1 is a schematic diagram of a data storage system shown in accordance with an embodiment of the present invention. Referring to fig. 1, a data storage system 10 includes a host system 11 and a memory storage system 12. The host system 11 may store data to the memory storage system 12 or read data from the memory storage system 12. For example, the host system 11 may be any system that substantially cooperates with the memory storage system 12 to store data, such as a computer system, a Digital camera, a video camera, a communication device, an audio player, a video player, a tablet computer, and the like, and the memory storage system 12 may be various nonvolatile memory devices, such as a usb disk, a memory card, a Solid State Drive (SSD), a Secure Digital (SD) card, a Compact Flash (CF) card, or an embedded storage device.

In one embodiment, the host system 11 may include a processor 111, a connection interface 112 (1), a connection interface 112 (2), and an input/output (I/O) device 113. The processor 111 is electrically connected to the connection interface 112 (1), the connection interface 112 (2), and an input/output (I/O) device 113. The processor 111 may be responsible for the overall or partial operation of the host system 11. For example, the Processor 111 may include a Central Processing Unit (CPU), or other Programmable general purpose or special purpose microprocessor, digital Signal Processor (DSP), programmable controller, application Specific Integrated Circuit (ASIC), programmable Logic Device (PLD), or other similar Device or combination thereof.

The connection interfaces 112 (1) and 112 (2) are used to connect the host system 11 to the memory storage system 12. For example, the connection interfaces 112 (1) and 112 (2) may be electrically connected to the memory storage system 12 via the

channels

101 and 102, respectively. The processor 111 can access the memory storage system 12 via the connection interfaces 112 (1) and 112 (2) (or the channels 101 and 102). The input/output (I/O) device 113 may include any output/output interface required by the implementation, such as a network interface card, a keyboard (or touch pad), a screen and/or a speaker, etc.

In one embodiment, the connection interfaces 112 (1) and 112 (2) conform to a connection interface standard such as Peripheral Component Interconnect Express (PCI Express). In addition, the connection interfaces 112 (1) and 112 (2) also conform to the NVM Express (NVMe) specification.

In one embodiment, memory storage system 12 includes

memory devices

121 and 122. Memory device 121 is also referred to as a first memory device. Memory device 122 is also referred to as a second memory device. The memory device 121 is electrically connected to the connection interface 112 (1) through the channel 101. The memory device 122 is electrically connected to the connection interface 112 (2) via the channel 102. It is noted that in one embodiment, the memory storage system 12 may also include more memory devices. In addition, in one embodiment, the memory storage system 12 is also referred to as a Redundant Array of Independent Disks (RAID) storage system.

In one embodiment, memory device 121 includes a memory module (not shown) and a memory controller (not shown). The memory module is used for storing data written by the host system 11. The memory controller is electrically connected to the memory module and is configured to access the memory module according to an instruction from the host system 11, for example, to perform data reading, writing or erasing on the memory module.

In one embodiment, the memory modules in the memory device 121 may include Single Level Cell (SLC) NAND type flash memory modules (i.e., flash memory modules in which one memory Cell can store 1 bit), two Level Cell (MLC) NAND type flash memory modules (i.e., flash memory modules in which one memory Cell can store 2 bits), three Level Cell (TLC) NAND type flash memory modules (i.e., flash memory modules in which one memory Cell can store 3 bits), and/or four Level Cell (Quad Level Cell, QLC) NAND type flash memory modules (i.e., flash memory modules in which one memory Cell can store 4 bits).

In one embodiment, the memory cells in the memory module store data with a change in threshold voltage. For example, the memory module may include a plurality of physical units therein. Each physical unit may include a plurality of storage units. For example, a physical unit may include one or more physical pages, one or more physical blocks, or one or more other memory management units. Memory cells belonging to the same physical page can be programmed simultaneously to store data. Memory cells belonging to the same physical block can be erased simultaneously to clear data. In one embodiment, the memory module is also referred to as a flash memory module and/or the memory controller is also referred to as a flash memory controller. In addition, the memory device 122 can be the same as or similar to the memory device 121, and is not described herein again.

In one embodiment, both

memory devices

121 and 122 support NVMe access operations. Processor 111 issues control commands via

channels

101 and 102 to access

memory devices

121 and 122 in parallel. For example, when data is to be stored, the processor 111 may issue write commands to the

memory devices

121 and 122 via the

channels

101 and 102, respectively, to instruct the

memory devices

121 and 122 to perform parallel data writing. In parallel data writing,

memory devices

121 and 122 may store data from host system 11 in parallel into respective memory modules of

memory devices

121 and 122. Alternatively, when data is to be read, the processor 111 may issue read commands to the

memory devices

121 and 122 through the

channels

101 and 102, respectively, to instruct the

memory devices

121 and 122 to perform parallel data reading. In parallel data reading,

memory devices

121 and 122 can read data from respective memory modules of

memory devices

121 and 122 in parallel and transmit the data to host system 11. In one embodiment, the processor 111 may also access the

memory devices

121 and 122 through a control interface or a driver interface.

In one embodiment, the processor 111 may evaluate the respective data writing performances of the

memory devices

121 and 122. This data write performance may reflect the data write speed of each of the

memory devices

121 and 122 when storing data from the host system 11. The processor 111 can determine the unit write data size (also referred to as a first unit write data size) of the memory device 121 and the unit write data size (also referred to as a second unit write data size) of the memory device 122 according to the evaluated data write performance. It is noted that the first unit write data amount may be different from the second unit write data amount. Thereafter, the processor 111 may instruct the

memory devices

121 and 122 to perform parallel data writing according to the first unit writing data amount and the second unit writing data amount.

In one embodiment, the processor 111 can detect the data writing bandwidth (also referred to as a first data writing bandwidth) of the memory device 121 and the data writing bandwidth (also referred to as a second data writing bandwidth) of the memory device 122 in real time. Then, the processor 111 can evaluate the respective data writing performances of the

memory devices

121 and 122 according to the first data writing bandwidth and the second data writing bandwidth. For example, the first data write bandwidth and the second data write bandwidth may reflect and positively correlate to the data write speed of the

respective memory devices

121 and 122, respectively.

FIGS. 2A and 2B are schematic diagrams illustrating evaluation of data write performance of a first memory device according to an embodiment of the invention. Referring to FIG. 2A, in one embodiment, the processor 111 sends a test signal TS (1) to the memory device 121 via the channel 101. The test signal TS (1) carries a test write command (also referred to as a first test write command). The memory device 121 may receive the test signal TS (1) and perform a data write operation according to the test signal TS (1) to store the data indicated by the first test write instruction. After completing the data write operation, the memory device 121 can reply with the response signal RS (1) through the channel 101. The response signal RS (1) may be used to notify the processor 111 that the write operation corresponding to the test signal TS (1) (or the first test write command) has been completed.

Referring to fig. 2B, it is assumed that the processor 111 sends the test signal TS (1) at a time point T1 (1) and receives the response signal RS (1) at a later time point T1 (2). The processor 111 may obtain a response time (also referred to as a first response time) of the memory device 121 with respect to the test signal TS (1) (or the first test write instruction) according to the time difference Δ TR (1) between the time points T1 (1) and T1 (2). The processor 111 may detect a data write bandwidth of the memory device 121 and/or a data write performance of the memory device 121 according to the first response time (or Δ TR (1)). For example, if the first response time (or Δ TR (1)) is shorter, the processor 111 may determine that the data writing bandwidth of the memory device 121 is larger and/or the data writing performance of the memory device 121 is better. In an embodiment, the processor 111 may also actually calculate the data writing bandwidth of the memory device 121 according to the first response time (or Δ TR (1)).

FIGS. 3A and 3B are schematic diagrams illustrating evaluation of data write performance of a second memory device according to an embodiment of the invention. Referring to fig. 3A, in one embodiment, the processor 111 can send a test signal TS (2) to the memory device 122 through the channel 102. The test signal TS (2) carries a test write command (also referred to as a second test write command). The memory device 122 may receive the test signal TS (2) and perform a data write operation according to the test signal TS (2) to store the data indicated by the second test write instruction. After completing the data write operation, the memory device 122 can reply with the response signal RS (2) through the channel 102. The response signal RS (2) may be used to notify the processor 111 that the write operation corresponding to the test signal TS (2) (or the second test write command) has been completed.

Referring to fig. 3B, it is assumed that the processor 111 sends the test signal TS (2) at a time point T2 (1) and receives the response signal RS (2) at a later time point T2 (2). The processor 111 may obtain a response time (also referred to as a second response time) of the memory device 122 for the test signal TS (2) (or the second test write instruction) according to the time difference Δ TR (2) between the time points T2 (1) and T2 (2). The processor 111 may detect the data write bandwidth of the memory device 122 and/or the data write performance of the memory device 122 according to the second response time (or Δ TR (2)). For example, if the second response time (or Δ TR (2)) is shorter, the processor 111 may determine that the data write bandwidth of the memory device 122 is larger and/or the data write performance of the memory device 122 is better. In an embodiment, the processor 111 may also actually calculate the data write bandwidth of the memory device 122 according to the second response time (or Δ TR (2)).

In one embodiment, assume that connection interface 112 (1) (or memory device 121) conforms to the PCIe Gen4 specification and connection interface 112 (2) (or memory device 122) conforms to the PCIe Gen 3 specification. Therefore, in an embodiment, the first response time (or Δ TR (1)) is shorter than the second response time (or Δ TR (2)), the data write bandwidth of the memory device 121 is greater than the data write bandwidth of the memory device 122, and/or the data write performance of the memory device 121 is higher than the data write performance of the memory device 122. However, in another embodiment, the connection interfaces 112 (1) and 112 (2) may also conform to other connection interface standards, and the invention is not limited thereto.

In an embodiment, the processor 111 may determine the first unit write data amount and the second unit write data amount according to a ratio of the first data write bandwidth to the second data write bandwidth. For example, assume that the detected first data write bandwidth and the second data write bandwidth are 5000MB/s and 3000MB/s, respectively. The processor 111 may obtain a ratio of the first data write bandwidth to the second data write bandwidth of about 1.67. In an embodiment, the ratio of the first data writing bandwidth to the second data writing bandwidth may also be replaced by the ratio of the first response time (or Δ TR (1)) to the second response time (or Δ TR (2)). The processor 111 can determine the first unit write data amount and the second unit write data amount according to the ratio. For example, after inputting the ratio (e.g. 1.67) of the first data write bandwidth and the second data write bandwidth into an equation or a lookup table, the processor 111 may determine the first unit write data amount as 128K and the second unit write data amount as 64K according to the output of the equation or the lookup table. Thereafter, the processor 111 may instruct the

memory devices

121 and 122 to perform parallel data writing according to the first unit writing data amount (e.g., 128K) and the second unit writing data amount (e.g., 6K).

Fig. 4 is a schematic diagram illustrating the first and second memory devices performing parallel data writing based on a preset unit writing data amount according to an embodiment of the present invention. Referring to fig. 4, in an embodiment, the first unit write data size and the second unit write data size are both a predetermined value without dynamically adjusting the first unit write data size and the second unit write data size. For example, the preset value may be 64K. When the

memory devices

121 and 122 perform parallel DATA writing, the DATA (1) and DATA (2) can be written into the

memory devices

121 and 122 in parallel between time points T3 (0) to T3 (2). The DATA amount of DATA (1) corresponds to the first unit write DATA amount, the DATA amount of DATA (2) corresponds to the second unit write DATA amount, and the first unit write DATA amount and the second unit write DATA amount are both 64K.

It is noted that the data writing performance of the memory device 121 is assumed to be higher than that of the memory device 122 (e.g., the data writing bandwidth of the memory device 121 is about 1.67 times that of the memory device 122). Thus, in the embodiment of FIG. 4, based on the predetermined unit write DATA amount, the writing of the 64K DATA DATA (2) by the memory device 122 is completed at about the time point T3 (2), while the writing of the DATA DATA (1) by the memory device 121 is completed earlier at the time point T3 (1). During the time range Δ T (idle) between the time points T3 (1) and T3 (2), the memory device 121 with higher data writing performance is in an idle state. In other words, the bandwidth resources of the memory device 121 with higher data writing performance will be wasted in the time range Δ T (idle).

After time point T3 (2),

memory devices

121 and 122 may continue to perform the next parallel data write. For example, between time points T3 (2) to T3 (4), DATA (3) and DATA (4) corresponding to a predetermined unit writing DATA amount (e.g., 64K) may be written in parallel into the

memory devices

121 and 122, and so on. It is noted that in some cases, if parallel data writing as shown in fig. 4 is performed based on a predetermined unit write data amount for a long time, the individual data writing performance of the memory devices may be slowed down in addition to the ideal parallel data writing performance of the memory devices.

FIG. 5 is a diagram illustrating a first memory device and a second memory device performing parallel data writing according to a dynamically determined unit write data size according to an embodiment of the present invention. Referring to fig. 5, in an embodiment, the first unit write data amount and the second unit write data amount may be dynamically determined according to the first data write bandwidth and the second data write bandwidth. For example, assuming that a ratio of the first data write bandwidth to the second data write bandwidth is about 1.67, the first unit write data amount and the second unit write data amount may be configured to be 128K and 64K, respectively. It should be noted that the first unit write data amount and the second unit write data amount can be adjusted according to practical requirements, and the invention is not limited thereto.

According to the dynamically configured first and second unit write DATA amounts, when the

memory devices

121 and 122 perform parallel DATA writing, the DATA (1) (also referred to as first DATA) and DATA (2) (also referred to as second DATA) can be written into the

memory devices

121 and 122 in parallel between time points T4 (0) to T4 (2). Wherein the DATA amount of DATA (1) corresponds to a first unit write DATA amount (e.g., 128K), and the DATA amount of DATA (2) corresponds to a second unit write DATA amount (e.g., 64K).

Compared to the embodiment of fig. 4, before the memory device 122 completes writing the DATA (2) at the time point T4 (2), although the memory device 121 may still complete writing the DATA (1) earlier than the time point T4 (1), the time length of the time range Δ T (idle)' between the time points T4 (1) and T4 (2) may be significantly less than the time range Δ T (idle) between the time points T3 (1) and T3 (2) of fig. 4.

Furthermore, after time point T4 (2),

memory devices

121 and 122 may continue to perform the next parallel data write. For example, between time points T4 (2) to T4 (4), DATA (3) and DATA (4) corresponding to different unit write DATA amounts may be written in parallel into the

memory devices

121 and 122, and so on.

In other words, in the embodiment of fig. 5, by writing more data (i.e., the first unit write data amount is greater than the second unit write data amount) into the memory device 121 with higher data writing performance in a single parallel data writing, the time that the memory device 121 is in an idle state (i.e., Δ T (idle)' is less than Δ T (idle)) can be effectively reduced. Thereby, the bandwidth resource utilization of the memory device 122 and/or the system performance of the entire data storage system can be improved.

In one embodiment, after the

memory devices

121 and 122 perform at least one parallel data write according to the dynamically configured first unit write data amount and the second unit write data amount, the data amount of the data stored in the memory device 121 is larger than the data amount of the data stored in the memory device 122. Taking fig. 5 as an example, in each parallel data write, the data amount of the data written to the memory device 121 may be 2 times or other multiples of the data amount of the data written to the memory device 122. Thus, in one embodiment, when the memory devices 121 and/or 122 are idle, the processor 111 can instruct the

memory devices

121 and 122 to perform a data transfer operation to balance the data amount of both the

memory devices

121 and 122.

In one embodiment, after the

memory devices

121 and 122 perform at least one parallel data write according to the dynamically configured first unit write data amount and the second unit write data amount, the processor 111 may instruct the

memory devices

121 and 122 to perform a data transfer operation, so as to copy a portion of data (also referred to as third data) in the memory device 121 into the memory device 122 for storage, and remove the third data in the memory device 121.

In one embodiment, in the data transfer operation, the processor 111 can send a read command to the memory device 121 via the channel 101 to instruct the memory device 121 to read the third data and transmit the third data to the host system 11. Then, processor 111 may send a write command to memory device 122 via channel 102 to instruct memory device 122 to store third data previously read from memory device 121 into memory device 122. Further, processor 111 may send a delete instruction to memory device 121 via channel 101 to instruct memory device 121 to delete the third data that has been copied into memory device 122.

In one embodiment, in response to the data movement operation, the processor 111 may modify a Flash Translation Layer (FTL) table or similar management table. The modified FTL table or similar management table may reflect that the third data has been moved from the memory device 121 to the memory device 122 (e.g., from at least one memory address originally located in the memory device 121 to at least one memory address in the memory device 122). Thereafter, the processor 111 can normally access the moved third data from the memory device 122 according to the FTL table or the like management table.

Fig. 6 is a flowchart illustrating a data parallel writing method according to an embodiment of the invention. Referring to fig. 6, in step S601, data write performance of the first memory device and the second memory device is evaluated. In step S602, a first unit write data amount of the first memory device and a second unit write data amount of the second memory device are determined according to the data write performance. The first unit write data amount is different from the second unit write data amount. In step S603, the first memory device and the second memory device are instructed to perform parallel data writing according to the first unit write data amount and the second unit write data amount.

However, the steps in fig. 6 have been described in detail above, and are not described again here. It is to be noted that, the steps in fig. 6 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the method of fig. 6 may be used with the above exemplary embodiments, or may be used alone, and the invention is not limited thereto.

In summary, the embodiments of the present invention provide a method for dynamically allocating an appropriate amount of unit write data to different memory devices according to the difference of data write performance of the memory devices in the same data storage system (or RAID storage system). Therefore, the parallel data writing performance of the data storage system (or the RAID storage system) can be improved.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data parallel writing method is used for a data storage system, the data storage system comprises a first memory device and a second memory device, and the data parallel writing method comprises the following steps:

evaluating data write performance of the first memory device and the second memory device;

determining a first unit write data size of the first memory device and a second unit write data size of the second memory device according to the data write performance, wherein the first unit write data size is different from the second unit write data size; and

instructing the first memory device and the second memory device to perform parallel data writing according to the first unit write data amount and the second unit write data amount.

2. The method of claim 1, wherein the step of evaluating the data writing performance of the first and second memory devices comprises:

detecting a first data write bandwidth of the first memory device and a second data write bandwidth of the second memory device; and

evaluating the data write performance of the first memory device and the second memory device according to the first data write bandwidth and the second data write bandwidth.

3. The data parallel writing method according to claim 2, wherein the step of detecting the first data writing bandwidth of the first memory device and the second data writing bandwidth of the second memory device comprises:

sending a first test write command to the first memory device;

detecting the first data write bandwidth of the first memory device according to a first response time of the first memory device to the first test write instruction;

sending a second test write command to the second memory device; and

detecting the second data write bandwidth of the second memory device according to a second response time of the second memory device to the second test write instruction.

4. The method of claim 2, wherein determining the first unit write data amount of the first memory device and the second unit write data amount of the second memory device according to the data write performance comprises:

and determining the first unit write data volume and the second unit write data volume according to the ratio of the first data write bandwidth to the second data write bandwidth.

5. The data parallel writing method according to claim 1, wherein in the parallel data writing, first data and second data are written in parallel into the first memory device and the second memory device, a data amount of the first data agrees with the first unit writing data amount, and a data amount of the second data agrees with the second unit writing data amount.

6. The data parallel writing method according to claim 1, further comprising:

after the parallel data writing is executed, the first memory device and the second memory device are instructed to execute data moving operation, so that third data in the first memory device are copied to the second memory device to be stored, and the third data in the first memory device are removed.

7. A data storage system, comprising:

a host system;

a first memory device connected to the host system via a first connection interface; and

a second memory device connected to the host system via a second connection interface,

wherein the host system is configured to evaluate data write performance of the first memory device and the second memory device,

the host system is further configured to determine a first unit write data amount of the first memory device and a second unit write data amount of the second memory device according to the data write performance, wherein the first unit write data amount is different from the second unit write data amount, and the first unit write data amount is different from the second unit write data amount

The host system is further configured to instruct the first memory device and the second memory device to perform parallel data writing according to the first unit write data amount and the second unit write data amount.

8. The data storage system of claim 7, wherein the operation of evaluating the data write performance of the first memory device and the second memory device comprises:

9. The data storage system according to claim 7, wherein in the parallel data writing, first data and second data are written in parallel into the first memory device and the second memory device, a data amount of the first data agrees with the first unit write data amount, and a data amount of the second data agrees with the second unit write data amount.

10. The data storage system of claim 7, wherein the first connection interface conforms to a PCIe Gen4 specification and the second connection interface conforms to a PCIe Gen 3 specification.