CN115202193B - Method and device for realizing amplitude limiting reset of digital integrator - Google Patents
Method and device for realizing amplitude limiting reset of digital integrator Download PDFInfo
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Abstract
The application belongs to the technical field of flight control, and particularly relates to a method and a device for realizing amplitude limiting reset of a digital integrator. The method is characterized in that whether the output of the last-beat integrator is larger than or equal to the upper limit UPlim of the integrator and whether the output of the last-beat integrator is smaller than or equal to the lower limit LOWlim of the integrator is judged, so that the output of the last-beat integrator is set, meanwhile, the input of the last-beat integrator is compared with 0, and the corrected input of the last-beat integrator are set. The application has the advantages of flexible use, dynamic amplitude limiting and resetting at any time, can cover all integrators applied to the flight control laws, and does not need to increase hardware cost.
Description
Technical Field
The application belongs to the technical field of flight control, and particularly relates to a method and a device for realizing amplitude limiting reset of a digital integrator.
Background
An integrator is a control means often used in flight control laws, and can eliminate control deviation when there is disturbance or uncertainty in control parameters. In the flight control law, integral control is generally used to implement no-static-difference control of normal overload in the air phase or no-static-difference tracking of the down-slip line in the landing phase (the integrator does not work in the rest of the phases). However, if the integrator is left to integrate all the time, there is a problem that the integrator output is overrun, and there is also a need to consider the problem of resetting by the integrator that is not used. If the integrator output is not limited and the integrator is reset, the output will be abnormal, and the effect of eliminating deviation cannot be realized.
Disclosure of Invention
In order to solve the problems, the application mainly aims at the problems of amplitude limiting and resetting of the digital integrator, and designs a method and a device for realizing the amplitude limiting and resetting of the digital integrator based on the action principle of the integrator.
The first aspect of the present application provides a method for implementing clipping reset of a digital integrator, which mainly includes:
step S1, obtaining a reset signal reset, an integrator input x, an integrator output initial value out0, an integrator upper limit UPlim, an integrator lower limit LOWlim and a calculation period st;
Step S2, judging whether the reset signal reset is0, if so, setting the output of the integrator of the current beat to be 0, if the reset signal reset is changed from 0 to 1, setting the output out of the integrator of the current beat to be the output initial value out0 of the integrator, setting the input x_pre of the integrator of the current beat to be the input x of the integrator of the current beat, and setting the output out_pre of the integrator of the current beat to be the output initial value out0 of the integrator;
Step S3, when the reset signal reset is other conditions, determining whether the output out_pre of the last beat of integrator is greater than or equal to the upper limit UPlim of the integrator, if yes, setting the corrected output out_pre_modified of the last beat of integrator as the upper limit UPlim of the integrator, and performing the following determination: if the input x of the current-beat integrator is larger than zero, setting the corrected input x_pre_corrected of the last-beat integrator and the corrected input x_corrected of the current-beat integrator to zero; otherwise, the corrected last beat of integrator input x_pre_modified and the corrected own beat of integrator input x_modified are set as the last beat of integrator input x_pre and the own beat of integrator input x;
Step S4, if the output out_pre of the last beat of integrator is smaller than the upper limit UPlim of integrator, then determine whether the output out_pre of the last beat of integrator is smaller than or equal to the lower limit LOWlim of integrator, if yes, set the output out_pre_modified of the last beat of integrator after correction as the lower limit LOWlim of integrator, and perform the following determination: if the input x of the current-beat integrator is smaller than zero, setting the corrected input x_pre_corrected of the last-beat integrator and the corrected input x_corrected of the current-beat integrator to zero; otherwise, the corrected last beat of integrator input x_pre_modified and the corrected own beat of integrator input x_modified are set as the last beat of integrator input x_pre and the own beat of integrator input x;
Step S5, if the last beat integrator output out_pre is between the integrator upper limit UPlim and the integrator lower limit LOWlim, the corrected last beat integrator output out_pre_modified, the corrected last beat integrator input x_pre_modified and the corrected own beat integrator input x_modified are respectively set as the last beat integrator output out_pre, the last beat integrator input x_pre and the own beat integrator input x;
Step S6, calculating the output out of the integrator of the current beat, updating the input x_pre of the integrator of the previous beat and the output out_pre of the integrator of the previous beat into the input x of the integrator of the current beat and the output out of the integrator of the current beat respectively, and repeating the steps S2 to S6.
Preferably, in step S6, the output out of the beat integrator is calculated by using a bilinear transform discretization method.
Preferably, the output out of the beat integrator is:
the second aspect of the present application provides a digital integrator clipping reset implementation apparatus, mainly comprising:
The initialization module is used for acquiring a reset signal reset, an integrator input x, an integrator output initial value out0, an integrator upper limit UPlim, an integrator lower limit LOWlim and a calculation period st;
The reset signal judging module is used for judging whether the reset signal reset is 0, if so, setting the output of the integrator of the current beat to be 0, if the reset signal reset is changed from 0 to 1, setting the output out of the integrator of the current beat to be an initial output value out0 of the integrator, setting the input x_pre of the integrator of the current beat to be the input x of the integrator of the current beat, and setting the output out_pre of the integrator of the current beat to be the initial output value out0 of the integrator;
The upper limit control module is configured to determine whether the last-beat integrator output out_pre is greater than or equal to the upper integrator limit UPlim when the reset signal reset is in other cases, if so, set the corrected last-beat integrator output out_pre_modified as the upper integrator limit UPlim, and perform the following determination: if the input x of the current-beat integrator is larger than zero, setting the corrected input x_pre_corrected of the last-beat integrator and the corrected input x_corrected of the current-beat integrator to zero; otherwise, the corrected last beat of integrator input x_pre_modified and the corrected own beat of integrator input x_modified are set as the last beat of integrator input x_pre and the own beat of integrator input x;
The lower limit control module is configured to determine whether the last-beat integrator output out_pre is less than or equal to the lower integrator limit LOWlim if the last-beat integrator output out_pre is less than the upper integrator limit UPlim, and if so, set the corrected last-beat integrator output out_pre_modified as the lower integrator limit LOWlim, and perform the following determination: if the input x of the current-beat integrator is smaller than zero, setting the corrected input x_pre_corrected of the last-beat integrator and the corrected input x_corrected of the current-beat integrator to zero; otherwise, the corrected last beat of integrator input x_pre_modified and the corrected own beat of integrator input x_modified are set as the last beat of integrator input x_pre and the own beat of integrator input x;
The data transfer module is configured to set the corrected previous-beat integrator output out_pre_modified, the corrected previous-beat integrator input x_pre_modified, and the corrected current-beat integrator input x_modified as the previous-beat integrator output out_pre, the previous-beat integrator input x_pre, and the current-beat integrator input x, respectively, if the previous-beat integrator output out_pre is between the integrator upper limit UPlim and the integrator lower limit LOWlim;
The integrating and updating module is used for calculating the output out of the integrator of the current beat, and updating the input x_pre of the integrator of the previous beat and the output out_pre of the integrator of the previous beat into the input x of the integrator of the current beat and the output out of the integrator of the current beat respectively.
Preferably, in the integrating and updating module, a bilinear transformation discretization method is adopted to calculate the output out of the beat integrator.
Preferably, the output out of the beat integrator is:
The application has the advantages of flexible use, dynamic amplitude limiting and resetting at any time, can cover all integrators applied to the flight control laws, and does not need to increase hardware cost.
Drawings
Fig. 1 is a flow chart of a preferred embodiment of the digital integrator clipping reset implementation method of the present application.
Fig. 2 is a schematic diagram of integrator input x variation in accordance with a preferred embodiment of the present application.
FIG. 3 is a diagram illustrating a change of the reset signal according to the embodiment of FIG. 2.
Fig. 4 is a schematic diagram showing the upper and lower limits of the integrator and the corresponding integrator output variation according to the embodiment of fig. 2.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application become more apparent, the technical solutions in the embodiments of the present application will be described in more detail with reference to the accompanying drawings in the embodiments of the present application. In the drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The described embodiments are some, but not all, embodiments of the application. The embodiments described below by referring to the drawings are exemplary and intended to illustrate the present application and should not be construed as limiting the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to fall within the scope of the present application. Embodiments of the present application will be described in detail below with reference to the accompanying drawings.
The first aspect of the present application provides a method for implementing clipping reset of a digital integrator, as shown in fig. 1, mainly including:
Step S1, a reset signal reset, an integrator input x, an integrator output initial value out0, an integrator upper limit UPlim, an integrator lower limit LOWlim, and a calculation period st are acquired. The output of the digital integrator clipping reset implementation method is the integrator output out. Next, each calculation cycle performs the following calculation:
Step S2, judging whether the reset signal reset is0, if so, setting the output of the integrator of the current beat to be 0, if the reset signal reset is changed from 0 to 1, setting the output out of the integrator of the current beat to be the output initial value out0 of the integrator, setting the input x_pre of the integrator of the current beat to be the input x of the integrator of the current beat, and setting the output out_pre of the integrator of the current beat to be the output initial value out0 of the integrator;
Step S3, when the reset signal reset is other conditions, determining whether the output out_pre of the last beat of integrator is greater than or equal to the upper limit UPlim of the integrator, if yes, setting the corrected output out_pre_modified of the last beat of integrator as the upper limit UPlim of the integrator, and performing the following determination: if the input x of the current-beat integrator is larger than zero, setting the corrected input x_pre_corrected of the last-beat integrator and the corrected input x_corrected of the current-beat integrator to zero; otherwise, the corrected last beat of integrator input x_pre_modified and the corrected own beat of integrator input x_modified are set as the last beat of integrator input x_pre and the own beat of integrator input x;
Step S4, if the output out_pre of the last beat of integrator is smaller than the upper limit UPlim of integrator, then determine whether the output out_pre of the last beat of integrator is smaller than or equal to the lower limit LOWlim of integrator, if yes, set the output out_pre_modified of the last beat of integrator after correction as the lower limit LOWlim of integrator, and perform the following determination: if the input x of the current-beat integrator is smaller than zero, setting the corrected input x_pre_corrected of the last-beat integrator and the corrected input x_corrected of the current-beat integrator to zero; otherwise, the corrected last beat of integrator input x_pre_modified and the corrected own beat of integrator input x_modified are set as the last beat of integrator input x_pre and the own beat of integrator input x;
Step S5, if the last beat integrator output out_pre is between the integrator upper limit UPlim and the integrator lower limit LOWlim, the corrected last beat integrator output out_pre_modified, the corrected last beat integrator input x_pre_modified and the corrected own beat integrator input x_modified are respectively set as the last beat integrator output out_pre, the last beat integrator input x_pre and the own beat integrator input x;
Step S6, calculating the output out of the integrator of the current beat, updating the input x_pre of the integrator of the previous beat and the output out_pre of the integrator of the previous beat into the input x of the integrator of the current beat and the output out of the integrator of the current beat respectively, and repeating the steps S2 to S6.
In some alternative embodiments, in step S6, the beat integrator output out is calculated using a bilinear transform discretization method.
In some alternative embodiments, the beat integrator output out is:
The effects of the present application will be described in further detail below by way of specific examples. The main verification has the following aspects: 1. verifying the clipping function of the digital integrator on the integrator upper limit UPlim (variable) and the integrator lower limit LOWlim (variable); 2. the reset function of the digital integrator is verified. Referring to fig. 2-4, in fig. 2, the reset signal reset changes from 0 to 1 (indicating that the integrator is beginning to operate) at 3 seconds, from 1 to 0 (indicating that the integrator is stopped) at 15 seconds, and from 0 to 1 again (indicating that the integrator is beginning to operate again) at 17 seconds. In fig. 3, the integrator input x changes from initial 1 to-9 at 13 seconds, 11 at 25 seconds, and 0 at 27 seconds. In this embodiment, the initial value out0 of the integrator is 10, and the calculation period st is 0.0125 seconds. In fig. 4, the integrator upper limit UPlim is changed from initial 12 to 15 at 6 th seconds (the integrator output upper limit is changed); the integrator lower limit LOWlim is changed from initial-10 to-15 at 22 seconds (changing the integrator output lower limit). The change condition of the output value of the integrator in fig. 4 can be seen that the output value of the integrator always fluctuates within the upper limit and the lower limit of the integrator and has the effect of resetting to 0, so that the implementation method of the amplitude limiting reset of the integrator provided by the application is flexible to use and realizes the functions of dynamic amplitude limiting and resetting at any time.
The second aspect of the present application provides a digital integrator clipping reset implementation apparatus corresponding to the above method, mainly including:
The initialization module is used for acquiring a reset signal reset, an integrator input x, an integrator output initial value out0, an integrator upper limit UPlim, an integrator lower limit LOWlim and a calculation period st;
The reset signal judging module is used for judging whether the reset signal reset is 0, if so, setting the output of the integrator of the current beat to be 0, if the reset signal reset is changed from 0 to 1, setting the output out of the integrator of the current beat to be an initial output value out0 of the integrator, setting the input x_pre of the integrator of the current beat to be the input x of the integrator of the current beat, and setting the output out_pre of the integrator of the current beat to be the initial output value out0 of the integrator;
The upper limit control module is configured to determine whether the last-beat integrator output out_pre is greater than or equal to the upper integrator limit UPlim when the reset signal reset is in other cases, if so, set the corrected last-beat integrator output out_pre_modified as the upper integrator limit UPlim, and perform the following determination: if the input x of the current-beat integrator is larger than zero, setting the corrected input x_pre_corrected of the last-beat integrator and the corrected input x_corrected of the current-beat integrator to zero; otherwise, the corrected last beat of integrator input x_pre_modified and the corrected own beat of integrator input x_modified are set as the last beat of integrator input x_pre and the own beat of integrator input x;
The lower limit control module is configured to determine whether the last-beat integrator output out_pre is less than or equal to the lower integrator limit LOWlim if the last-beat integrator output out_pre is less than the upper integrator limit UPlim, and if so, set the corrected last-beat integrator output out_pre_modified as the lower integrator limit LOWlim, and perform the following determination: if the input x of the current-beat integrator is smaller than zero, setting the corrected input x_pre_corrected of the last-beat integrator and the corrected input x_corrected of the current-beat integrator to zero; otherwise, the corrected last beat of integrator input x_pre_modified and the corrected own beat of integrator input x_modified are set as the last beat of integrator input x_pre and the own beat of integrator input x;
The data transfer module is configured to set the corrected previous-beat integrator output out_pre_modified, the corrected previous-beat integrator input x_pre_modified, and the corrected current-beat integrator input x_modified as the previous-beat integrator output out_pre, the previous-beat integrator input x_pre, and the current-beat integrator input x, respectively, if the previous-beat integrator output out_pre is between the integrator upper limit UPlim and the integrator lower limit LOWlim;
The integrating and updating module is used for calculating the output out of the integrator of the current beat, and updating the input x_pre of the integrator of the previous beat and the output out_pre of the integrator of the previous beat into the input x of the integrator of the current beat and the output out of the integrator of the current beat respectively.
In some alternative embodiments, the integration and update module calculates the output out of the beat integrator using a bilinear transform discretization method.
In some alternative embodiments, the beat integrator output out is:
While the application has been described in detail in the foregoing general description and with reference to specific embodiments thereof, it will be apparent to one skilled in the art that modifications and improvements can be made thereto. Accordingly, such modifications or improvements may be made without departing from the spirit of the application and are intended to be within the scope of the application as claimed.
Claims (6)
1. A method for implementing clipping reset of a digital integrator, comprising:
step S1, obtaining a reset signal reset, an integrator input x, an integrator output initial value out0, an integrator upper limit UPlim, an integrator lower limit LOWlim and a calculation period st;
Step S2, judging whether the reset signal reset is0, if so, setting the output of the integrator of the current beat to be 0, if the reset signal reset is changed from 0 to 1, setting the output out of the integrator of the current beat to be the output initial value out0 of the integrator, setting the input x_pre of the integrator of the current beat to be the input x of the integrator of the current beat, and setting the output out_pre of the integrator of the current beat to be the output initial value out0 of the integrator;
Step S3, when the reset signal reset is other conditions, determining whether the output out_pre of the last beat of integrator is greater than or equal to the upper limit UPlim of the integrator, if yes, setting the corrected output out_pre_modified of the last beat of integrator as the upper limit UPlim of the integrator, and performing the following determination: if the input x of the current-beat integrator is larger than zero, setting the corrected input x_pre_corrected of the last-beat integrator and the corrected input x_corrected of the current-beat integrator to zero; otherwise, the corrected last beat of integrator input x_pre_modified and the corrected own beat of integrator input x_modified are set as the last beat of integrator input x_pre and the own beat of integrator input x;
Step S4, if the output out_pre of the last beat of integrator is smaller than the upper limit UPlim of integrator, then determine whether the output out_pre of the last beat of integrator is smaller than or equal to the lower limit LOWlim of integrator, if yes, set the output out_pre_modified of the last beat of integrator after correction as the lower limit LOWlim of integrator, and perform the following determination: if the input x of the current-beat integrator is smaller than zero, setting the corrected input x_pre_corrected of the last-beat integrator and the corrected input x_corrected of the current-beat integrator to zero; otherwise, the corrected last beat of integrator input x_pre_modified and the corrected own beat of integrator input x_modified are set as the last beat of integrator input x_pre and the own beat of integrator input x;
Step S5, if the last beat integrator output out_pre is between the integrator upper limit UPlim and the integrator lower limit LOWlim, the corrected last beat integrator output out_pre_modified, the corrected last beat integrator input x_pre_modified and the corrected own beat integrator input x_modified are respectively set as the last beat integrator output out_pre, the last beat integrator input x_pre and the own beat integrator input x;
Step S6, calculating the output out of the integrator of the current beat, updating the input x_pre of the integrator of the previous beat and the output out_pre of the integrator of the previous beat into the input x of the integrator of the current beat and the output out of the integrator of the current beat respectively, and repeating the steps S2 to S6.
2. The method for implementing clipping reset of a digital integrator according to claim 1, wherein in step S6, a bilinear transform discretization method is used to calculate the output out of the beat integrator.
3. The method for implementing clipping reset of a digital integrator as claimed in claim 2, wherein the output out of the beat integrator is:
4. a digital integrator clipping reset implementation apparatus, comprising:
The initialization module is used for acquiring a reset signal reset, an integrator input x, an integrator output initial value out0, an integrator upper limit UPlim, an integrator lower limit LOWlim and a calculation period st;
The reset signal judging module is used for judging whether the reset signal reset is 0, if so, setting the output of the integrator of the current beat to be 0, if the reset signal reset is changed from 0 to 1, setting the output out of the integrator of the current beat to be an initial output value out0 of the integrator, setting the input x_pre of the integrator of the current beat to be the input x of the integrator of the current beat, and setting the output out_pre of the integrator of the current beat to be the initial output value out0 of the integrator;
The upper limit control module is configured to determine whether the last-beat integrator output out_pre is greater than or equal to the upper integrator limit UPlim when the reset signal reset is in other cases, if so, set the corrected last-beat integrator output out_pre_modified as the upper integrator limit UPlim, and perform the following determination: if the input x of the current-beat integrator is larger than zero, setting the corrected input x_pre_corrected of the last-beat integrator and the corrected input x_corrected of the current-beat integrator to zero; otherwise, the corrected last beat of integrator input x_pre_modified and the corrected own beat of integrator input x_modified are set as the last beat of integrator input x_pre and the own beat of integrator input x;
The lower limit control module is configured to determine whether the last-beat integrator output out_pre is less than or equal to the lower integrator limit LOWlim if the last-beat integrator output out_pre is less than the upper integrator limit UPlim, and if so, set the corrected last-beat integrator output out_pre_modified as the lower integrator limit LOWlim, and perform the following determination: if the input x of the current-beat integrator is smaller than zero, setting the corrected input x_pre_corrected of the last-beat integrator and the corrected input x_corrected of the current-beat integrator to zero; otherwise, the corrected last beat of integrator input x_pre_modified and the corrected own beat of integrator input x_modified are set as the last beat of integrator input x_pre and the own beat of integrator input x;
The data transfer module is configured to set the corrected previous-beat integrator output out_pre_modified, the corrected previous-beat integrator input x_pre_modified, and the corrected current-beat integrator input x_modified as the previous-beat integrator output out_pre, the previous-beat integrator input x_pre, and the current-beat integrator input x, respectively, if the previous-beat integrator output out_pre is between the integrator upper limit UPlim and the integrator lower limit LOWlim;
The integrating and updating module is used for calculating the output out of the integrator of the current beat, and updating the input x_pre of the integrator of the previous beat and the output out_pre of the integrator of the previous beat into the input x of the integrator of the current beat and the output out of the integrator of the current beat respectively.
5. The digital integrator clipping reset implementation apparatus of claim 4 wherein the integration and update module computes the beat integrator output out using a bilinear transform discretization method.
6. The method for implementing clipping reset of a digital integrator of claim 5, wherein the output out of the beat integrator is:
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| KR100198151B1 (en) * | 1996-07-29 | 1999-06-15 | 추호석 | Integral limit type anti-windup controller |
| DE19854750A1 (en) * | 1998-11-27 | 2000-05-31 | Heidenhain Gmbh Dr Johannes | Method and circuit arrangement for determining an optimal gain of the integrator of a speed controller |
| US6693572B1 (en) * | 2003-02-04 | 2004-02-17 | Motorola, Inc. | Digital tuning scheme for continuous-time sigma delta modulation |
| CN113625545B (en) * | 2021-08-08 | 2023-07-21 | 中国航空工业集团公司沈阳飞机设计研究所 | Longitudinal instruction control method and device suitable for inner loop proportional integral control |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101968628A (en) * | 2010-09-08 | 2011-02-09 | 华北电力大学 | Saturated self-adjusting controller for time-varying delay uncertain system |
| CN107728464A (en) * | 2017-09-25 | 2018-02-23 | 国网山东省电力公司电力科学研究院 | Boiler optimization control system and method based on integral parameter dynamic adjustment |
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