CN115200433B - High-integration electronic detonator chip and system - Google Patents
High-integration electronic detonator chip and system Download PDFInfo
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- CN115200433B CN115200433B CN202210895194.0A CN202210895194A CN115200433B CN 115200433 B CN115200433 B CN 115200433B CN 202210895194 A CN202210895194 A CN 202210895194A CN 115200433 B CN115200433 B CN 115200433B
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F42—AMMUNITION; BLASTING
- F42C—AMMUNITION FUZES; ARMING OR SAFETY MEANS THEREFOR
- F42C19/00—Details of fuzes
- F42C19/08—Primers; Detonators
- F42C19/12—Primers; Detonators electric
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F42—AMMUNITION; BLASTING
- F42C—AMMUNITION FUZES; ARMING OR SAFETY MEANS THEREFOR
- F42C19/00—Details of fuzes
- F42C19/08—Primers; Detonators
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/34—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering
- H02J7/345—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering using capacitors as storage or buffering devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/06—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J2207/00—Indexing scheme relating to details of circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J2207/50—Charging of capacitors, supercapacitors, ultra-capacitors or double layer capacitors
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Air Bags (AREA)
Abstract
The application provides a high-integration electronic detonator chip and a system, comprising: the power-on circuit comprises a rectifier bridge, a low-voltage linear voltage stabilizer LDO, a reference voltage circuit, a charge-discharge circuit, a charge pump, an oscillator circuit, a power-on reset circuit, a digital logic circuit, a communication circuit, an electrified erasable programmable read-only memory, a power tube and a pull-down resistor; the digital logic circuit is respectively connected with the oscillator circuit, the communication circuit, the power-on reset circuit, the charge-discharge circuit, the charged erasable programmable read-only memory, the charge pump, the power tube and the pull-down resistor; the rectifier bridge, the low-voltage linear voltage stabilizer, the reference voltage circuit and the charge pump are connected in sequence; the power-on reset circuit is also connected with the low-voltage linear voltage stabilizer and the reference voltage circuit; the rectifier bridge is connected with the charge-discharge circuit. Compared with some multi-chip sealing schemes, the single-chip scheme provided by the application has the advantages of higher integration level, simplicity in packaging, higher yield and higher cost performance.
Description
Technical Field
The application relates to the technical field of electronic detonators, in particular to a high-integration electronic detonator chip and a high-integration electronic detonator system.
Background
The digital electronic detonator is mainly applied to the blasting industry, is different from the traditional industrial detonator, and has the basic principle that the electronic detonator chip is used for controlling the blasting process, wherein the electronic detonator chip is arranged inside the digital electronic detonator, can perform safety certification through a detonator user identification code UID and a detonation password, and has the special integrated circuits with functions of online roll calling scanning, high-voltage charging of an energy storage capacitor, accurate delay control, starting of a firing switch for detonation and the like.
Compared with the traditional industrial detonator, the digital electronic detonator has relatively high cost due to the special electronic detonator chip and some devices at the periphery of the chip, and the relatively high price of the digital electronic detonator enables customers of a plurality of detonator factories to maintain a certain reserved attitude and needs an electronic detonator chip with higher cost performance to meet the demands of the customers although the blasting performance and effect of the digital electronic detonator are widely accepted gradually.
Patent document CN111595212a (application number: CN202010384396. X) discloses a communication demodulation circuit of an electronic detonator, an electronic detonator chip, an electronic detonator system, the communication demodulation circuit comprising: the device comprises a second field effect transistor, a third field effect transistor, a resistive element, a rectifier and a digital signal output unit; the second grid electrode of the second field effect transistor is coupled with the third grid electrode of the third field effect transistor; the second drain electrode and the second grid electrode of the second field effect transistor are coupled to the first cable; the second source electrode of the second field effect transistor and the third source electrode of the third field effect transistor are commonly grounded; the third drain electrode of the third field effect transistor and the first end of the resistive element are coupled to a first electric coupling point; a second end of the resistive element is coupled with a power supply VDD; the first electric coupling point is coupled with the digital signal output unit.
The current digital electronic detonator chip has relatively low integration level, and is provided with a chip which is not integrated with a rectifier bridge stack and a firing switch, and an independent bridge stack circuit and a firing switch are added on a detonator module; the integrated bridge stack and the ignition switch are also arranged, but an analog chip and a digital chip are adopted for single flow, and then a multi-chip sealing is adopted, and the cost of an actual chip and the packaging cost are not low although the integrated bridge stack and the ignition switch are seen as a single chip; the main control chip is designed by adopting an analog-digital mixed high-voltage process, and then is sealed with a bridge pile or a firing switch, so that the same packaging cost is high, and the yield is low. It is also rare to truly implement a complete single process single chip scheme.
Disclosure of Invention
Aiming at the defects in the prior art, the application aims to provide an electronic detonator chip and a system with high integration level.
The high-integration electronic detonator chip provided by the application comprises:
rectifier bridge: rectifying A, B alternating current power supply to direct current power supply VDD/GND;
low voltage linear regulator LDO: the conversion from a high-voltage power supply to a low-voltage power supply is realized, and the output low voltage is used as a digital power supply for an oscillator circuit, a digital logic circuit, a communication circuit and an EEPROM;
reference voltage circuit: the reference voltages REF1, REF2 and REF3 required by the power-on reset circuit and the programmable low-voltage linear voltage regulator are generated and are respectively used for the LDO, the power-on reset circuit and the charge pump;
and a charge-discharge circuit: the device comprises a current limiting resistor and a charging and discharging tube, so as to realize the charging and discharging management of the energy storage capacitor;
charge pump: the low voltage REF3 output based on the reference voltage is boosted, and the output high voltage is used for controlling the grid electrode of the power tube, so that the on-resistance of the power tube is reduced;
an oscillator circuit: providing a stable clock CLK for the digital logic circuit;
a power-on reset circuit: a circuit of a full-chip reset signal POR generated after the electronic detonator chip is electrified, wherein the effective level of the POR signal is low level;
digital logic circuit: completing external communication of the electronic detonator chip and internal state conversion and delay control of the chip;
communication circuit: writing the two bus signals into the data to finish the internal digital logic signals of the detonator chip, and realizing A, B short circuit to provide feedback current when the two buses read the data from the detonator chip;
charged erasable programmable read-only memory: the user identification code UID, the detonation password, the delay value and other user configuration information are used for storing the detonator;
a power tube: when the grid control signal FIRE is effective, the MOS tube is opened, the energy on the energy storage capacitor is released, and the ignition resistor is heated, so that the medicine head on the ignition resistor is detonated;
pull-down resistor: the power tube is used for pulling down the grid electrode of the power tube and controlling the power tube to be closed;
the digital logic circuit is respectively connected with the oscillator circuit, the communication circuit, the power-on reset circuit, the charge-discharge circuit, the charged erasable programmable read-only memory, the charge pump, the power tube and the pull-down resistor; the rectifier bridge, the low-voltage linear voltage stabilizer, the reference voltage circuit and the charge pump are connected in sequence; the power-on reset circuit is also connected with the low-voltage linear voltage stabilizer and the reference voltage circuit; the rectifier bridge is connected with the charge-discharge circuit.
Preferably, the rectifier bridge includes four diodes D1 to D4, D1, D2 as ESD bleeder protection tubes of pin a, and D3, D4 as ESD bleeder protection tubes of pin B.
The high-integration electronic detonator system provided by the application comprises:
an exploder: performing detonation control on the electronic detonator module;
an electronic detonator module: comprises an electronic detonator chip, and the detonation of the finished explosive head is controlled by an exploder.
Preferably, the electronic detonator module comprises current limiting resistors R1, R2: the detonator is used for limiting the current on the bus, and is connected with the electronic detonator chip after being connected with the current limiting resistors R1 and R2 through the A, B bus.
Preferably, the electronic detonator module comprises a TVS/ESD tube: the TVS tube/ESD tube is connected in parallel between the A, B bus and the current limiting resistors R1 and R2.
Preferably, the electronic detonator module comprises a filter capacitor C1: the filter capacitor C1 is used for filtering the power module in the electronic detonator chip and is connected with the electronic detonator chip.
Preferably, the electronic detonator module comprises a communication capacitor C2: and the communication capacitor C2 is used for supplementing electricity to the electronic detonator chip when the electronic detonator chip is read by the exploder, and is connected with the electronic detonator chip.
Preferably, the electronic detonator module comprises an energy storage capacitor C: the energy storage capacitor C is connected with the electronic detonator chip.
Preferably, the electronic detonator module comprises a firing resistor R: and the ignition resistor R is connected with the electronic detonator chip and the energy storage capacitor C.
Preferably, a 36V bi-directional TVS tube or bi-directional ESD tube is used to accommodate the polarity-free A, B bus and the 32V maximum operating voltage characteristics of the electronic detonator module.
Compared with the prior art, the application has the following beneficial effects:
1. the application utilizes the characteristic that the structure of the rectifier bridge circuit and the structure of the chip pin electrostatic ESD discharging passage circuit are similar, and adopts the circuit structure which combines the rectifier bridge circuit and the chip pin electrostatic ESD discharging passage circuit into one, so that the extra area of the chip is not increased basically;
2. the application designs a special Charge Pump (Charge Pump) to improve the overdrive voltage of the power tube used as an ignition switch, so that the area of the power tube is minimized on the premise of realizing the same on-resistance of the power tube, the cost of a chip is saved, and the reliable ignition of an electronic detonator is ensured;
3. the electronic detonator chip integrates the rectifier bridge stack and the ignition switch through a single-chip scheme, so that the number of components on the electronic detonator module is reduced, and the overall material cost of the module and the welding cost in production are greatly reduced;
4. compared with some multi-chip sealing schemes, the single-chip scheme has higher integration level, simple packaging and higher yield, and can obtain higher cost performance.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, given with reference to the accompanying drawings in which:
FIG. 1 is a circuit diagram of a system;
FIG. 2 is a diagram of the internal circuitry of the chip;
FIG. 3 is a circuit diagram of a rectifier bridge;
fig. 4 is a diagram of an electrostatic ESD discharge circuit.
Detailed Description
The present application will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the present application, but are not intended to limit the application in any way. It should be noted that variations and modifications could be made by those skilled in the art without departing from the inventive concept. These are all within the scope of the present application.
Examples:
the electronic detonator chip is realized by adopting an ASIC (Application Specific Integrated Circuit application specific integrated circuit) mode of an analog-digital hybrid high-voltage technology, and a rectifier bridge and an ignition switch are integrated on a single chip. Meanwhile, through an innovative circuit structure, a bridge pile circuit for rectifying and an ESD electrostatic discharge passage of the A, B two paths of input/output pins are integrated; a Charge Pump (Charge Pump) is designed to increase the overdrive voltage of the power tube as an ignition switch, so that the low on-resistance of the power tube is ensured, and the reliable ignition of the electronic detonator is ensured.
A system circuit diagram, as in fig. 1.
An exploder: and (5) completing the detonation control of the electronic detonator module.
An electronic detonator module: the device consists of an electronic detonator chip, current limiting resistors R1 and R2, a TVS tube/ESD tube, a filter capacitor C1, a communication capacitor C2, an ignition resistor R and an energy storage capacitor C, and is controlled by an exploder to explode a finished explosive head.
Filter capacitance: and the capacitor is used for filtering the power module in the electronic detonator chip.
Communication capacitance: and the capacitor is used for supplementing electricity to the chip when the electronic detonator chip reads the data of the electronic detonator chip by the exploder.
Energy storage capacitor: for powering the electronic detonator chip after the chip has entered a delay and for providing energy to heat the firing resistor upon initiation.
Firing resistor: generally, a bridge wire resistor or a patch metal resistor is used for igniting and igniting the powder head. Typically a few ohms.
Current limiting resistor R1/R2: for limiting the current on the bus, the value of R is typically less than 2K ohms.
TVS/ESD tube: the transient high-voltage suppression tube (Transient Voltage Suppressors)/electrostatic discharge tube (Electro-Static discharge) can be used for suppressing electrostatic signals or high-frequency interference signals, and a proper device is selected for use according to practical application scenes, and a 36V bidirectional TVS tube or a bidirectional ESD tube is adopted in the application so as to adapt to the characteristics of no polarity of a A, B bus and the maximum operating voltage of a module of 32V.
The internal circuit structure of the chip is shown in fig. 2.
Rectifier bridge: in the figure, four diodes D1 to D4 (the actual circuit may be diodes or MOS transistors) are used as both ESD bleeder protection transistors for rectifying A, B ac power to dc power VDD/GND, and also D1 and D2 are used as ESD bleeder protection transistors for pin a and D3 and D4 are used as ESD bleeder protection transistors for pin B.
Low voltage linear voltage regulator (LDO): the conversion from a high-voltage power supply to a low-voltage power supply is realized. The output low voltage is used mainly as a digital power supply for oscillators, digital logic circuits, communication circuits and EEPROMs.
Reference voltage circuit: some reference voltages REF1, REF2, REF3 required for the power-on reset circuit and the programmable low voltage linear voltage regulator are generated for the LDO, the power-on reset circuit and the charge pump, respectively.
And a charge-discharge circuit: the device comprises a current limiting resistor and a charging and discharging tube, and realizes the charging and discharging management of the energy storage capacitor.
Charge pump: the voltage is boosted to 4.8V high voltage based on the low voltage REF3 (1.2V) output by the reference voltage, and the output high voltage is used for controlling the grid electrode of the power tube, so that the on-resistance of the power tube is reduced.
An oscillator circuit: the digital logic circuit is provided with a stable clock CLK, which is typically above 100K.
POR power-on reset circuit: and a circuit of a full-chip reset signal POR generated after the electronic detonator chip is electrified, wherein the effective level of the POR signal is low level.
Digital logic circuit: and the logic circuit for external communication and internal state conversion and delay control of the electronic detonator chip is completed.
EEPROM: and the charged erasable programmable read-only memory is used for storing the user identification code UID, the detonation password, the delay value and other user configuration information of the detonator.
Communication circuit: writing the two bus signals into the data to convert the data into the digital logic signals in the detonator chip, and shorting A, B to provide feedback current when the two buses read the data from the detonator chip.
A power tube: and when the grid control signal FIRE is effective, the MOS tube is opened, the energy on the energy storage capacitor is released, and the ignition resistor is heated, so that the medicine head on the ignition resistor is detonated.
Energy storage capacitor: for powering the electronic detonator chip after the chip has entered a delay and for providing energy to heat the firing resistor upon initiation.
Firing resistor: generally, a bridge wire resistor or a patch metal resistor is used for igniting and igniting the powder head. Typically a few ohms.
Pull-down resistor: the pull-down resistor for pulling down the grid of the power tube by default and controlling the power tube to be closed is typically several M ohms.
Rectifier bridge/electrostatic ESD bleeder circuits as shown in fig. 3 and 4.
The circuit can be realized by adopting a diode or a MOS (metal oxide semiconductor) tube, and the application mainly combines the diode and the MOS tube into a whole, so that the area of the circuit is reduced by nearly half.
In electronic detonator applications, the NMOS power transistor operates in the linear region when turned on, and its on-resistance is calculated as follows:
wherein u is n Is the mobility of the current carrier, C ox Capacitance of gate oxide layer per unit area, V GS -V TH Commonly referred to as overdrive voltage, it can be seen from the above equation that once the process is selected, u n 、C ox Is determined, the on-resistance of the power tube is only related to the width-to-length ratio (W/L) of the tube and the overdrive voltage V GS -V TH Related to the following.
In theory, the power tube always has a minimum communication length (L) in design, and by increasing the width (W), the width-to-length ratio can be increased to reduce the on-resistance, but the area (w×l) of the power tube can be increased in the same ratio, and the lower on-resistance cannot be obtained simply by increasing the width of the power tube due to the limitation of the chip cost.
But by increasing overdrive voltage V GS -V TH That is, by increasing the gate voltage of the power transistor, a lower on-resistance can be obtained.
In generalThe same size power tube, the gate electrode adopts 4.8V compared with 3V, can reduce the on-resistance by nearly half: (3-0.7)/(4.8-0.7) =0.56. Meanwhile, because the grid voltage resistance of the MOS tube is limited and is usually 5-6V, 4.8V is selected as 4 times voltage of the charge pump to drive the power tube.
In the description of the present application, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application.
Those skilled in the art will appreciate that the systems, apparatus, and their respective modules provided herein may be implemented entirely by logic programming of method steps such that the systems, apparatus, and their respective modules are implemented as logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc., in addition to the systems, apparatus, and their respective modules being implemented as pure computer readable program code. Therefore, the system, the apparatus, and the respective modules thereof provided by the present application may be regarded as one hardware component, and the modules included therein for implementing various programs may also be regarded as structures within the hardware component; modules for implementing various functions may also be regarded as being either software programs for implementing the methods or structures within hardware components.
The foregoing describes specific embodiments of the present application. It is to be understood that the application is not limited to the particular embodiments described above, and that various changes or modifications may be made by those skilled in the art within the scope of the appended claims without affecting the spirit of the application. The embodiments of the application and the features of the embodiments may be combined with each other arbitrarily without conflict.
Claims (10)
1. A high integration electronic detonator chip, comprising:
rectifier bridge: rectifying A, B alternating current power supply to direct current power supply VDD/GND;
low voltage linear regulator LDO: the conversion from a high-voltage power supply to a low-voltage power supply is realized, and the output low voltage is used as a digital power supply for an oscillator circuit, a digital logic circuit, a communication circuit and an EEPROM;
reference voltage circuit: the reference voltages REF1, REF2 and REF3 required by the power-on reset circuit and the programmable low-voltage linear voltage regulator are generated and are respectively used for the LDO, the power-on reset circuit and the charge pump;
and a charge-discharge circuit: the device comprises a current limiting resistor and a charging and discharging tube, so as to realize the charging and discharging management of the energy storage capacitor;
charge pump: the low voltage REF3 output based on the reference voltage is boosted, and the output high voltage is used for controlling the grid electrode of the power tube, so that the on-resistance of the power tube is reduced;
an oscillator circuit: providing a stable clock CLK for the digital logic circuit;
a power-on reset circuit: a circuit of a full-chip reset signal POR generated after the electronic detonator chip is electrified, wherein the effective level of the POR signal is low level;
digital logic circuit: completing external communication of the electronic detonator chip and internal state conversion and delay control of the chip;
communication circuit: writing the two bus signals into the data to finish the internal digital logic signals of the detonator chip, and realizing A, B short circuit to provide feedback current when the two buses read the data from the detonator chip;
charged erasable programmable read-only memory: the user identification code UID, the detonation password, the delay value and other user configuration information are used for storing the detonator;
a power tube: when the grid control signal FIRE is effective, the MOS tube is opened, the energy on the energy storage capacitor is released, and the ignition resistor is heated, so that the medicine head on the ignition resistor is detonated;
pull-down resistor: the power tube is used for pulling down the grid electrode of the power tube and controlling the power tube to be closed;
the digital logic circuit is respectively connected with the oscillator circuit, the communication circuit, the power-on reset circuit, the charge-discharge circuit, the charged erasable programmable read-only memory, the charge pump, the power tube and the pull-down resistor; the rectifier bridge, the low-voltage linear voltage stabilizer, the reference voltage circuit and the charge pump are connected in sequence; the power-on reset circuit is also connected with the low-voltage linear voltage stabilizer and the reference voltage circuit; the rectifier bridge is connected with the charge-discharge circuit.
2. The high integration electronic detonator chip of claim 1 wherein the rectifier bridge comprises four diodes D1-D4, D1, D2 as ESD bleed protection tubes for pin a and D3, D4 as ESD bleed protection tubes for pin B.
3. A high-integration electronic detonator system using the high-integration electronic detonator chip of claim 1 or 2, comprising:
an exploder: performing detonation control on the electronic detonator module;
an electronic detonator module: comprises an electronic detonator chip, and the detonation of the finished explosive head is controlled by an exploder.
4. The high-integrity electronic detonator system of claim 3 wherein the electronic detonator module comprises current limiting resistors R1, R2: the detonator is used for limiting the current on the bus, and is connected with the electronic detonator chip after being connected with the current limiting resistors R1 and R2 through the A, B bus.
5. The high integration electronic detonator system of claim 4 wherein the electronic detonator module comprises a TVS/ESD tube: the TVS tube/ESD tube is connected in parallel between the A, B bus and the current limiting resistors R1 and R2.
6. The high-integration electronic detonator system of claim 5 wherein the electronic detonator module comprises a filter capacitor C1: the filter capacitor C1 is used for filtering the power module in the electronic detonator chip and is connected with the electronic detonator chip.
7. The high-integration electronic detonator system of claim 6 wherein the electronic detonator module comprises a communication capacitor C2: and the communication capacitor C2 is used for supplementing electricity to the electronic detonator chip when the electronic detonator chip is read by the exploder, and is connected with the electronic detonator chip.
8. The high-integration electronic detonator system of claim 7 wherein the electronic detonator module comprises an energy storage capacitor C: the energy storage capacitor C is connected with the electronic detonator chip.
9. The high-integrity electronic detonator system of claim 8 wherein the electronic detonator module comprises a firing resistor R: and the ignition resistor R is connected with the electronic detonator chip and the energy storage capacitor C.
10. The high integration electronic detonator system of claim 5 wherein 36V bi-directional TVS or bi-directional ESD tubes are used to accommodate the polarity-free A, B bus and the 32V maximum operating voltage characteristics of the electronic detonator module.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210895194.0A CN115200433B (en) | 2022-07-26 | 2022-07-26 | High-integration electronic detonator chip and system |
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| CN202210895194.0A CN115200433B (en) | 2022-07-26 | 2022-07-26 | High-integration electronic detonator chip and system |
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| CN115200433B true CN115200433B (en) | 2023-08-15 |
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| CN115200433A (en) | 2022-10-18 |
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