CN115190024A - Basic unit of multi-topology structure bus and topology structure - Google Patents

Basic unit of multi-topology structure bus and topology structure Download PDF

Info

Publication number
CN115190024A
CN115190024A CN202210595914.1A CN202210595914A CN115190024A CN 115190024 A CN115190024 A CN 115190024A CN 202210595914 A CN202210595914 A CN 202210595914A CN 115190024 A CN115190024 A CN 115190024A
Authority
CN
China
Prior art keywords
module
many
path
arbitration module
arbitration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202210595914.1A
Other languages
Chinese (zh)
Other versions
CN115190024B (en
Inventor
游胜
原德鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yusur Technology Co ltd
Original Assignee
Yusur Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yusur Technology Co ltd filed Critical Yusur Technology Co ltd
Priority to CN202210595914.1A priority Critical patent/CN115190024B/en
Publication of CN115190024A publication Critical patent/CN115190024A/en
Application granted granted Critical
Publication of CN115190024B publication Critical patent/CN115190024B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/12—Discovery or management of network topologies
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Bus Control (AREA)

Abstract

The invention provides a basic unit of a multi-topology structure bus and a topology structure, wherein the basic unit of the multi-topology structure bus comprises an arbitration module and a processing module, the processing module is connected with the arbitration module, and the arbitration module is a many-to-one arbitration module or a one-to-many arbitration module; the output end of the many-to-one arbitration module is provided with an output path, the input end of the many-to-one arbitration module is provided with an input path, and the input path is provided with interface parameters for establishing connection with the input path; the input end of the one-to-many arbitration module is provided with an input path, the output end of the one-to-many arbitration module is provided with an output path, and each output path is provided with interface parameters for establishing connection with the output path; the input end and the output end of the processing module are connected with the many-to-one arbitration module or the one-to-many arbitration module, and a processor inside the processing module is used for processing data transmitted from the input end of the processing module based on the interface parameters of the input path or the output path.

Description

Basic unit of multi-topology structure bus and topology structure
Technical Field
The invention relates to the technical field of data transmission, in particular to a basic unit of a multi-topology structure bus and a topology structure.
Background
The data transmission quantity is larger and larger, the terminal interaction situation is more and more complex, and the topological structure of the bus is more and more frequently changed due to the change of the number and the form of the terminals.
When a topological structure is changed in the prior art, the conventional topological structure is generally required to be reconstructed, in order to meet the requirements of convenience in cascade expansion and high transmission efficiency of various topological structures provided for a bus by application, the topological structure is troublesome to change when the conventional bus meets the structure of the transmission efficiency, the structural design needs to be carried out again for later topological structure change, the development cost is high, and the maintenance is inconvenient; and the topological structure is easy to change, the transmission efficiency is poor, and the performance requirement is difficult to meet.
Disclosure of Invention
In view of the above, embodiments of the present invention provide a base unit of a multi-topology bus, which obviates or mitigates one or more of the disadvantages of the related art.
One aspect of the present invention provides a basic unit of a multi-topology bus, which includes an arbitration module and a processing module, wherein the processing module is connected to the arbitration module, and the arbitration module is a many-to-one arbitration module or a one-to-many arbitration module;
the output end of the many-to-one arbitration module is provided with an output path, the input end of the many-to-one arbitration module is provided with at least one input path, and each input path is provided with interface parameters for establishing connection with the input path;
the input end of the one-to-many arbitration module is provided with an input path, the output end of the one-to-many arbitration module is provided with at least one output path, and each output path is provided with interface parameters for establishing connection with the output path;
the input end and the output end of the processing module are connected with a many-to-one arbitration module or a one-to-many arbitration module, the input end and the output end of the processing module are connected with the many-to-one arbitration module or the one-to-many arbitration module, a processor used for processing input data is preset in the processing module based on interface parameters of an input path or an output path, and the processor is used for processing data transmitted from the input end of the processing module and transmitting the data to the output end of the processing module.
By adopting the scheme, the input end and the output end of the processing module are connected with a many-to-one arbitration module or a one-to-many arbitration module, the input path of the many-to-one arbitration module is provided with interface parameters for establishing connection with the input path, the output path of the one-to-many arbitration module is provided with interface parameters for establishing connection with the output path, the connection between the input path and the output path can be established based on the interface parameters, the connection between a plurality of basic units is established, and a topological structure is established.
In some embodiments of the present invention, a first cache module is preset in the many-to-one arbitration module, and when data is transferred into the many-to-one arbitration module, it is determined whether a processing module located downstream of the many-to-one arbitration module is in a working state, and if not, the data is output downstream; if so, caching the data in the first cache module until the processing module finishes all clock processing cycles and outputting the data downstream.
In some embodiments of the present invention, when there is cache data in a first cache module of the many-to-one arbitration module, the many-to-one arbitration module sends an indication signal of a first state to an input path of the many-to-one arbitration module, so that an upstream module connected to the input path stops sending data to the many-to-one arbitration module.
In some embodiments of the present invention, the many-to-one arbitration module is provided with a path analysis module, when data is input to the many-to-one arbitration module, path information is generated based on an input path, and the many-to-one arbitration module analyzes the path information to obtain the input path of the input data.
In some embodiments of the present invention, when the path information has multiple bits, the multi-bit path information is decomposed, and multiple input paths simultaneously incoming are determined based on the decomposed path information.
In some embodiments of the present invention, the one-to-many arbitration module includes a route decoding module, data incoming from an input path of the one-to-many arbitration module is input to the route decoding module, and the route decoding module decodes route information in the incoming data and determines an output path accessed by the data based on a decoding result.
In some embodiments of the present invention, the one-to-many arbitration module includes a second cache module, which is configured to cache data of a certain output path in the second cache module, determine whether an indication signal of a first state exists in the output path of the data, and if so, wait for the indication signal of the first state to change to a second state, and import the data from the second cache module to the output path; if not, directly importing the data from the second cache module to the output path.
In some embodiments of the present invention, when there is cache data in the second cache module of the one-to-many arbitration module, the one-to-many arbitration module sends an indication signal of the first state to the input path of the one-to-many arbitration module, so that an upstream module connected to the input path stops sending data to the one-to-many arbitration module.
One aspect of the present invention provides a topology comprising a plurality of the above-mentioned basic units and an arbitration module, the arbitration module being connected between the basic units, an input path of the arbitration unit being connected to an output of an upstream basic unit, and an output path of the arbitration unit being connected to an input of a downstream basic unit.
In some embodiments of the present invention, if the arbitration module between the base units is a many-to-one arbitration module, each input path of the many-to-one arbitration module is connected to the output end of the upstream base unit; if the arbitration module between the basic units is a one-to-many arbitration module, each output path of the one-to-many arbitration module is connected with the input end of the downstream basic unit.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and drawings.
It will be appreciated by those skilled in the art that the objects and advantages that can be achieved with the present invention are not limited to what has been particularly described hereinabove, and that the above and other objects that can be achieved with the present invention will be more clearly understood from the following detailed description.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principle of the invention.
FIG. 1 is a schematic diagram of a first embodiment of a base unit of a multi-topology bus of the present invention;
FIG. 2 is a schematic diagram of a second embodiment of a base unit of a multi-topology bus in accordance with the present invention;
FIG. 3 is a schematic diagram of a third embodiment of a base unit of a multi-topology bus in accordance with the present invention;
FIG. 4 is a block diagram of a one-to-many arbitration module according to the present invention;
FIG. 5 is a block diagram of a many-to-one arbitration module according to the present invention;
FIG. 6 is a schematic diagram of a cross-connect approach;
fig. 7 is a schematic diagram of another cross-connection mode.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the following embodiments and the accompanying drawings. The exemplary embodiments and descriptions of the present invention are provided to explain the present invention, but not to limit the present invention.
It should be noted that, in order to avoid obscuring the present invention with unnecessary details, only the structures and/or processing steps closely related to the scheme according to the present invention are shown in the drawings, and other details not so relevant to the present invention are omitted.
It should be emphasized that the term "comprises/comprising" when used herein, is taken to specify the presence of stated features, elements, steps or components, but does not preclude the presence or addition of one or more other features, elements, steps or components.
It is also noted that, unless otherwise specified, the term "coupled" is used herein to refer not only to a direct connection, but also to an indirect connection with an intermediate.
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the drawings, the same reference numerals denote the same or similar parts, or the same or similar steps.
The data transmission quantity in the current network is larger and larger, the terminal interaction situation is more and more complex, and the topological structure of the bus is more and more frequently changed due to the change of the number and the form of the terminals. Under the limitation of the bus working frequency and the data bit width, higher and higher requirements are put forward on the total bandwidth and the transmission efficiency of the bus. The existing bus implementation mode is difficult to meet the requirements of easy change of the topology structure of the bus and high transmission efficiency, and the requirements of various application scenes on the bus can be met only by adopting a new framework and an implementation mode.
In order to solve the above problems, as shown in fig. 1-3, the present invention provides a basic unit of a multi-topology bus, which includes an arbitration module and a processing module, wherein the processing module is connected to the arbitration module, and the arbitration module is a many-to-one arbitration module or a one-to-many arbitration module;
the output end of the many-to-one arbitration module is provided with an output path, the input end of the many-to-one arbitration module is provided with at least one input path, and each input path is provided with interface parameters for establishing connection with the input path;
the input end of the one-to-many arbitration module is provided with an input path, the output end of the one-to-many arbitration module is provided with at least one output path, and each output path is provided with interface parameters for establishing connection with the output path;
by adopting the scheme, in order to solve the problems of inflexible topology change, low transmission efficiency and the like of the conventional bus structure, the bus is composed of two different arbitration units in different interconnection modes; the two units are respectively: many-to-one arbitration module and one-to-many arbitration module, the flexibility of topology change is improved.
The flexible support to the topological structure can support the multistage cascade, only the basic unit of the bus needs to adopt different interconnection modes, the development time can be effectively reduced, and the maintenance and the update of the bus are convenient.
The input end and the output end of the processing module are connected with a many-to-one arbitration module or a one-to-many arbitration module, the input end and the output end of the processing module are connected with the many-to-one arbitration module or the one-to-many arbitration module, a processor used for processing input data is preset in the processing module based on interface parameters of an input path or an output path, and the processor is used for processing data transmitted from the input end of the processing module and transmitting the data to the output end of the processing module.
In some embodiments of the present invention, the processor may be a hardware processing chip or a preset processing program.
In some embodiments of the present invention, the input end of the processing module may be connected to a many-to-one arbitration module, and may also be connected to a one-to-many arbitration module, and the input path or the output path of the many-to-one arbitration module and the one-to-many arbitration module are both provided with interface parameters.
By adopting the scheme, the input end and the output end of the processing module are connected with a many-to-one arbitration module or a one-to-many arbitration module, the input path of the many-to-one arbitration module is provided with interface parameters for establishing connection with the input path, the output path of the one-to-many arbitration module is provided with interface parameters for establishing connection with the output path, the connection between the input path and the output path can be established based on the interface parameters, the connection between a plurality of basic units is established, and a topological structure is established.
In some embodiments of the present invention, a first cache module is preset in the many-to-one arbitration module, and when data is transmitted to the many-to-one arbitration module, it is determined whether a processing module located downstream of the many-to-one arbitration module is in a working state, and if not, the data is output downstream; if so, caching the data in the first cache module until the processing module finishes all clock processing cycles and outputting the data downstream.
In some embodiments of the present invention, when there is cache data in a first cache module of the many-to-one arbitration module, the many-to-one arbitration module sends an indication signal of a first state to an input path of the many-to-one arbitration module, so that an upstream module connected to the input path stops sending data to the many-to-one arbitration module.
The upstream module connected to the input path may be a many-to-one arbitration module, or a one-to-many arbitration module.
In some embodiments of the present invention, if an arbitration module is connected downstream of the many-to-one arbitration module, it is determined whether an indication signal in a first state exists in an output path of the data, and if so, the data is led into the output path by waiting for the indication signal in the first state to change to a second state; if not, directly importing the data to the output path.
In some embodiments of the present invention, when the indication signal is in the first state, it indicates that the path to which the signal is output is in a busy state, and when the indication signal is in the second state, it indicates that the path to which the signal is output is in an idle state.
In some embodiments of the present invention, the many-to-one arbitration module is provided with a path analysis module, and when data is input to the many-to-one arbitration module, path information is generated based on the input path, and the many-to-one arbitration module analyzes the path information to obtain the input path of the input data.
In some embodiments of the present invention, if the many-to-one arbitration module includes 4 input paths, when the path information is 0001, it indicates that the input path is coming from the 1 st input path; when the path information is 0100, it indicates that the path is incoming from the 3 rd input path.
In some embodiments of the present invention, when the path information has multiple bits, the multi-bit path information is decomposed, and multiple input paths simultaneously incoming are determined based on the decomposed path information.
In some embodiments of the present invention, if the many-to-one arbitration module includes 4 input paths, when the path information is 0101, i.e. there are multiple bits in the path information, the multi-bit path information 0101 is decomposed into 0100 and 0001.
In some embodiments of the present invention, data in a path corresponding to path information with a smaller value is preferentially transmitted.
Then the incoming from the 1 st input path is illustrated; when the path information is 0100, it indicates that the path is incoming from the 3 rd input path.
As shown in fig. 5, the input port of the many-to-one arbitration module occupies the bus for data transmission according to the principle of first request and first response, and as long as the input port has a new bus request, the corresponding bit position 1 of the port request record table is used, and this function is completed by the request record module; and then, the new request record table is put into an information fifo buffer for storage.
In order to process the condition that a plurality of ports simultaneously request, reading data in the information fifo, sending the data into a bit searching module for processing, and sequentially decomposing the request recording data into a plurality of data only with 1bit as 1 from low order to high order; the split data is written into the ordering fifo according to the sequence from small to large.
When the transmission judging module judges that the last transmission is finished or the current transmission is interrupted unexpectedly, port request data is read from the sequencing fifo, which bit is 1 is judged, and the port selecting module gives a corresponding port data transmission response.
In the many-to-one bus arbitration module, an output port is unique, routing signals do not need to be used for routing selection, but source numbers transmitted along with the routing need to be transmitted out in an original mode, and it is guaranteed that after a bus load terminal receives the source number signals, routing information signals can be directly assigned to serve as routing information for sending original route return data according to the source number signals, and therefore the source number setting needs to meet the working requirements of the routing information during reverse direction transmission.
In some embodiments of the present invention, the one-to-many arbitration module includes a route decoding module, data incoming from an input path of the one-to-many arbitration module is input to the route decoding module, and the route decoding module decodes route information in the incoming data and determines an output path accessed by the data based on a decoding result.
In some embodiments of the present invention, the one-to-many arbitration module includes a second cache module, which is configured to cache data of a certain output path in the second cache module, determine whether an indication signal of a first state exists in the output path of the data, and if so, wait for the indication signal of the first state to change to a second state, and import the data from the second cache module to the output path; if not, directly importing the data from the second cache module to the output path.
In order to meet the requirements of multiple topological structures provided for the bus by application, the cascade expansion is convenient, the transmission efficiency is high, the topological structure is troublesome to change when the existing bus meets the structure of the transmission efficiency, the structural design needs to be carried out again for later topological structure change, the development cost is high, and the maintenance is inconvenient. The topological structure is easy to change, the transmission efficiency is not high, and the performance requirement is difficult to meet. The reason why the bus system with easily changed topology has low transmission efficiency is caused by too long interval time between two transmissions. If the processing time between two transmissions can be shortened, the transmission idle time can be greatly reduced, and the transmission efficiency is improved. In the current bus scheme of the variable topology mechanism, the reason that the interval between two times of processing transmission is large is that the next time of transmission of routing information is processed only when the last transmission is completed, if the processing of the next time of transmission of routing information is completed in advance under the condition of meeting the bus time sequence requirement, namely the routing information is preprocessed before the current transmission is completed, the next transmission can be started only by reading the next time of transmission of routing information when the current transmission is completed, and the transmission efficiency is greatly improved;
in the scheme, the routing information in the transmitted data is preferentially decoded, the output path of the data access is determined based on the decoding result, the routing information is obtained in advance, and when the channel is idle, the next transmission can be immediately started, so that the transmission efficiency is greatly improved.
In order to solve the problem of transmission efficiency, the routing information transmitted by the next bus is preprocessed in advance, and when the current transmission is finished, the preprocessed routing information is directly acquired to start the next transmission. The idle time of transmission is effectively reduced, and the bus efficiency is improved.
In some embodiments of the present invention, when there is cache data in the second cache module of the one-to-many arbitration module, the one-to-many arbitration module sends an indication signal of the first state to the input path of the one-to-many arbitration module, so that an upstream module connected to the input path stops sending data to the one-to-many arbitration module.
The upstream module connected to the input path may be a many-to-one arbitration module, or a one-to-many arbitration module.
As shown in fig. 4, the input routing information signal of the one-to-many arbitration module performs port decoding in the routing decoding, and each stage of arbitration uses the corresponding information group decoding in the routing information to generate port routing data with only 1bit being 1. The routing data and the external input data are written into the fifo buffer together under the control of the write control module.
When the read control module judges that no transmission is currently performed or transmission is immediately finished, a read enable signal is sent to a fifo buffer, the fifo buffer sends corresponding port selection information to the port selection module for port selection, and meanwhile, read data of the input port and the like are kept by the data latch module and are ready for being output externally.
In some embodiments of the present invention, a single-stage one-to-many arbitration has no more than 16 output ports, and if the number is larger, the single-stage one-to-many arbitration is implemented by adopting a plurality of one-to-many cascades.
And (3) selecting a route: according to the number of arbitration stages with one-to-many numbers on the bus, the bits of the routing information are divided into corresponding groups according to the high and low bits, the group with the highest bit corresponds to the first-stage arbitration routing information, and the group with the lowest bit corresponds to the last-stage arbitration routing information. If there is a broadcast request, all bits are positioned at position 1, which requires that the value of the routing information does not correspond to any port number. If there is no broadcast requirement, corresponding port numbers can be corresponded according to the values when all bits are at position 1.
By adopting the scheme, the one-to-many arbitration module and the many-to-one arbitration module in the scheme are provided with the first cache module or the second cache module, so that data can be cached, the blockage caused when the main line is occupied is prevented, and the processing efficiency is improved.
One aspect of the present invention provides a topology comprising a plurality of the above-mentioned basic units and an arbitration module, the arbitration module being connected between the basic units, an input path of the arbitration unit being connected to an output of an upstream basic unit, and an output path of the arbitration unit being connected to an input of a downstream basic unit.
In some embodiments of the present invention, if the arbitration module between the base units is a many-to-one arbitration module, each input path of the many-to-one arbitration module is connected to the output end of the upstream base unit; if the arbitration module between the basic units is a one-to-many arbitration module, each output path of the one-to-many arbitration module is connected with the input end of the downstream basic unit.
The bus formed by interconnecting the one-to-many bus arbitration units and the many-to-one bus arbitration units can form different topological structures according to requirements, and is convenient to cascade, so that the overall development workload of the bus of each topological structure is reduced, and the maintenance work is simple. The transmission efficiency is also higher, and each time one-stage cascade connection is added, the bus idle period is only increased by one clock period.
In some embodiments of the present invention, the arbitration modules between the base units may be multiple, that is, there is a cascade of multiple stages of arbitration modules;
two stagesE.g. a first stage having a number of output ports and a second stage having b number of ports, 2 n-1 <a<＝2 n ,2 m-1 <b<＝2 m And if the bit width of the input routing information is m + n, the high n bits are used as the first-stage routing judgment signal, and the low m bits are used as the second-stage routing signal to judge the second-stage routing information. The one-to-many cascade processing mode with more stages is the same.
When one-to-many cascade connection is carried out, the most important thing is the processing of the selection of the route, if no broadcasting requirement exists, the number of the ports except the first level is made to be the integral power of 2; if there is a broadcast requirement, the number of ports except the first stage is an integral power of 2, and is reduced by one, so that the bit width of the routing signal can be reduced. In the multi-stage broadcasting, bit positions of routing signals are all set to be 1.
When many-to-one cascade is carried out, each stage carries out independent arbitration judgment according to the request signal of the input port, and the multi-stage cascade is not influenced.
In a two-level cross-connect of many-to-many and many-to-one, the routing of the second level is not affected by the first level, regardless of which form is used as the first level. The cross-connection of the PxQ can be divided into basic units from left to right and from right to left as shown in FIGS. 6 and 7, and the basic units are formed by different connection modes.
As shown in FIG. 6, the left-to-right direction is composed of P1 to Q arbitration units as the first stage and Q P to 1 arbitration units. As shown in FIG. 7, the right-to-left direction is composed of Q1-to-P arbitration units as the first level and P Q-to-1 arbitration units. Performing next-stage expansion on the rear stage of the cross-connected structure, and performing one-to-many cascade connection or many-to-one cascade connection; any extension of the cascade is only affected by the form of the arbitration unit at the upper stage.
Those of ordinary skill in the art will appreciate that the various illustrative components, systems, and methods described in connection with the embodiments disclosed herein may be implemented as hardware, software, or combinations of both. Whether this is done in hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention. When implemented in hardware, it may be, for example, an electronic circuit, an Application Specific Integrated Circuit (ASIC), suitable firmware, plug-in, function card, or the like. When implemented in software, the elements of the invention are the programs or code segments used to perform the required tasks. The program or code segments may be stored in a machine-readable medium or transmitted by a data signal carried in a carrier wave over a transmission medium or a communication link.
It is to be understood that the invention is not limited to the specific arrangements and instrumentality described above and shown in the drawings. A detailed description of known methods is omitted herein for the sake of brevity. In the above embodiments, several specific steps are described and shown as examples. However, the method processes of the present invention are not limited to the specific steps described and illustrated, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps, after comprehending the spirit of the present invention.
Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments and/or in combination with or instead of the features of the other embodiments in the present invention.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made to the embodiment of the present invention by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. The basic unit of the multi-topology structure bus is characterized in that the basic unit of the multi-topology structure bus comprises an arbitration module and a processing module, wherein the processing module is connected with the arbitration module, and the arbitration module is a many-to-one arbitration module or a one-to-many arbitration module;
the output end of the many-to-one arbitration module is provided with an output path, the input end of the many-to-one arbitration module is provided with at least one input path, and each input path is provided with interface parameters for establishing connection with the input path;
the input end of the one-to-many arbitration module is provided with an input path, the output end of the one-to-many arbitration module is provided with at least one output path, and each output path is provided with interface parameters for establishing connection with the output path;
the input end and the output end of the processing module are connected with a many-to-one arbitration module or a one-to-many arbitration module, the input end and the output end of the processing module are connected with the many-to-one arbitration module or the one-to-many arbitration module, a processor used for processing input data is preset in the processing module based on interface parameters of an input path or an output path, and the processor is used for processing data transmitted from the input end of the processing module and transmitting the data to the output end of the processing module.
2. The basic unit of the multi-topology structure bus according to claim 1, wherein a first cache module is preset in the multi-to-one arbitration module, when data is input into the multi-to-one arbitration module, whether a processing module located downstream of the multi-to-one arbitration module is in a working state is determined, and if not, the data is output downstream; if yes, caching the data in the first caching module until the processing module completes all clock processing cycles, and outputting the data downstream.
3. The infrastructure element of a multi-topology bus according to claim 2, wherein when there is cache data in a first cache module of the many-to-one arbitration module, the many-to-one arbitration module sends an indication signal of the first status to the input path of the many-to-one arbitration module, so that an upstream module connected to the input path stops sending data to the many-to-one arbitration module.
4. The infrastructure element of a multi-topology bus according to claim 1, wherein the many-to-one arbitration module is provided with a path analysis module, when data is input to the many-to-one arbitration module, path information is generated based on an input path, and the many-to-one arbitration module analyzes the path information to obtain the input path of the input data.
5. The base unit of a multi-topology bus according to claim 4, wherein when said path information has a plurality of bits, then the multi-bit path information is decomposed, and a plurality of input paths incoming at the same time are determined based on the decomposed path information.
6. The infrastructure element of the multi-topology bus according to claim 1, wherein the one-to-many arbitration module includes a routing decoding module, and data incoming from an input path of the one-to-many arbitration module is input to the routing decoding module, and the routing decoding module decodes routing information in the incoming data and determines an output path for accessing the data based on a decoding result.
7. The basic unit of the multi-topology structure bus according to claim 3, wherein the one-to-many arbitration module includes a second buffer module, which buffers the data of the determined output path into the second buffer module, determines whether the output path of the data has the indication signal of the first state, and waits for the indication signal of the first state to change into the second state if the output path of the data has the indication signal of the first state, and imports the data from the second buffer module into the output path; if not, directly importing the data from the second cache module to the output path.
8. The infrastructure element of claim 7, wherein when there is cache data in the second cache module of the one-to-many arbitration module, the one-to-many arbitration module sends a first status indication signal to the input path of the one-to-many arbitration module to cause an upstream module connected to the input path to stop sending data to the one-to-many arbitration module.
9. A topology, characterized in that it comprises a plurality of base units according to any of claims 1-8 and an arbitration module, said arbitration module being connected between the base units, the input path of said arbitration unit being connected to the output of an upstream base unit and the output path of said arbitration unit being connected to the input of a downstream base unit.
10. The topology of claim 9, wherein if the arbitration module between the base units is a many-to-one arbitration module, each input path of the many-to-one arbitration module is connected to an output of an upstream base unit; if the arbitration module between the basic units is a one-to-many arbitration module, each output path of the one-to-many arbitration module is connected with the input end of the downstream basic unit.
CN202210595914.1A 2022-05-30 2022-05-30 Basic unit of multi-topology structure bus and topology structure Active CN115190024B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210595914.1A CN115190024B (en) 2022-05-30 2022-05-30 Basic unit of multi-topology structure bus and topology structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210595914.1A CN115190024B (en) 2022-05-30 2022-05-30 Basic unit of multi-topology structure bus and topology structure

Publications (2)

Publication Number Publication Date
CN115190024A true CN115190024A (en) 2022-10-14
CN115190024B CN115190024B (en) 2023-03-28

Family

ID=83513122

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210595914.1A Active CN115190024B (en) 2022-05-30 2022-05-30 Basic unit of multi-topology structure bus and topology structure

Country Status (1)

Country Link
CN (1) CN115190024B (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5053942A (en) * 1988-11-01 1991-10-01 The Regents Of The University Of California Bit-sliced cross-connect chip having a tree topology of arbitration cells for connecting memory modules to processors in a multiprocessor system
WO1997004542A2 (en) * 1995-07-19 1997-02-06 Fujitsu Network Communications, Inc Multipoint-to-point arbitration in a network switch
US20060282605A1 (en) * 2005-06-10 2006-12-14 David Avishai High-speed internal bus architecture for an integrated circuit
CN110049529A (en) * 2019-03-08 2019-07-23 佛山市云米电器科技有限公司 A kind of optimal path referee method of ad hoc network wireless technology
CN110460546A (en) * 2019-08-15 2019-11-15 电子科技大学 A kind of collecting method based on network-on-chip

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5053942A (en) * 1988-11-01 1991-10-01 The Regents Of The University Of California Bit-sliced cross-connect chip having a tree topology of arbitration cells for connecting memory modules to processors in a multiprocessor system
WO1997004542A2 (en) * 1995-07-19 1997-02-06 Fujitsu Network Communications, Inc Multipoint-to-point arbitration in a network switch
US20060282605A1 (en) * 2005-06-10 2006-12-14 David Avishai High-speed internal bus architecture for an integrated circuit
CN110049529A (en) * 2019-03-08 2019-07-23 佛山市云米电器科技有限公司 A kind of optimal path referee method of ad hoc network wireless technology
CN110460546A (en) * 2019-08-15 2019-11-15 电子科技大学 A kind of collecting method based on network-on-chip

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
张锦林: "NoC中主要技术的研究与实现" *
张锦林: "NoC中主要技术的研究与实现", 《中国新技术新产品》 *

Also Published As

Publication number Publication date
CN115190024B (en) 2023-03-28

Similar Documents

Publication Publication Date Title
JP2571655B2 (en) Protocol conversion mechanism, switching network and computer system
US7609688B2 (en) Serialized bus communication and control architecture
CN115190024B (en) Basic unit of multi-topology structure bus and topology structure
US6275498B1 (en) Extended PHY addressing
CN113177015B (en) Frame header-based serial port communication method and serial port chip
US6006283A (en) System and method for managing information exchanges in a disk interface chip
CN102355394A (en) Method and device for performing data transmission control for a plurality of paths of controller area network (CAN) buses
CN1507285A (en) Method of realizing router chip of group exchange network with FPGA device
JP2007538452A (en) Turbo decoder input reordering
RU175049U1 (en) COMMUNICATION INTERFACE DEVICE SpaceWire
CN113132231B (en) TTE exchange system and method supporting time slice moving and application
US8392733B2 (en) Network apparatus
US11467989B2 (en) Serial transmission system and serial transmission method
CN117951070B (en) Cross switch module, multi-core interconnection chip, transaction processing method and product
CN113225161B (en) 5G terminal PDCCH MIMO detection accelerator and design method
US6529991B1 (en) Ordering mechanism, ordering method and computer program product for implementing PCI peer to functions
JP3389610B2 (en) Parallel processing system and data transfer method
CN114747193B (en) Exchange chip
US5905734A (en) Time slot interchanger and digital communications terminal for ISDN D-channel assembly
US7392332B2 (en) Bit rate adaptation in a data processing flow
US6460092B1 (en) Integrated circuit for distributed-type input/output control
JP2576262B2 (en) Information processing device
KR100255382B1 (en) Bus synchronous signal generation method for data bus of ipc network
CN114817113A (en) Method, system, equipment and storage medium for judging SDA data direction
JP4265778B2 (en) Stream data processing method and apparatus

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant