CN115174326B - Burst detection and coherent demodulation device and method for high-speed frequency hopping MSK signal - Google Patents
Burst detection and coherent demodulation device and method for high-speed frequency hopping MSK signal Download PDFInfo
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Abstract
The invention discloses a burst detection and coherent demodulation device and method of a high-speed frequency hopping MSK signal, wherein the device comprises a frequency hopping signal arrival detection module, a frequency offset and initial phase estimation module, a gain adjustment module, a phase-locked loop and bit synchronization module, a bit recovery module and a RAM; the RAM is respectively connected with the frequency hopping signal arrival detection module, the frequency offset and initial phase estimation module, the phase-locked loop and the bit synchronization module, and the phase-locked loop and the bit synchronization module are also respectively connected with the gain adjustment module and the bit recovery module; the input end of the frequency hopping signal reaching detection module is connected with the DDC module. The invention has good anti-noise and anti-frequency deviation capability. The frequency offset and the initial phase of the received signal are estimated by adopting a phase difference correction method based on DFT interpolation, so that the accurate estimation of the frequency offset and the initial phase can be realized. The traditional costas loop is improved, so that the MSK signal phase is locked to 0, pi/2, pi and-pi/2 points, phase jump can be effectively reduced, the signal demodulation stability is improved, and the error rate is reduced.
Description
Technical Field
The invention relates to a burst detection and coherent demodulation device and method for a high-speed (the hopping speed exceeds 500 hops/second) frequency hopping MSK signal in non-cooperative communication, which are mainly used in the communication countermeasure field and aim at real-time detection and interpretation of unknown wireless signals of enemy so as to acquire information.
Background
MSK is used as a constant envelope digital modulation technology, has higher frequency band utilization rate and lower requirement on dynamic range of a power device, so MSK signals are widely used in frequency hopping communication.
For detection of a frequency hopping signal, there are mainly an energy detection method, a correlation detection method, and the like. The energy detection double-window sliding method is widely applied and has small calculated amount, but the problems of incapability of accurately judging the starting position of a signal, poor noise resistance and the like exist. Document Zhang Wenzhu research on synchronization technology in CPM burst transmission system [ D ]: the university of electronics and technology, 2016, uses the synchronization head waveform cross correlation method to detect the frame synchronization position, and the principle is that when the frame synchronization heads are aligned, a correlation peak occurs.
MSK signal demodulation is divided into coherent demodulation and incoherent demodulation, wherein for high-speed frequency hopping MSK demodulation, the problem of long locking time exists in the coherent demodulation realized by a phase-locked loop, and therefore, the MSK signal demodulation cannot be directly applied to MSK frequency hopping demodulation, and therefore, incoherent demodulation is mostly adopted, such as document Gao Wenjie, all-digital demodulator design and realization of high-speed burst communication [ D ]. Nanjing: differential 1bit incoherent demodulation is adopted in Nanjing university of technology 2012.
Therefore, the prior art has defects in high-speed frequency hopping MSK signal demodulation, cannot be applied in engineering, and needs a new signal processing algorithm to realize.
Research on synchronization technology in Zhang Wenzhu CPM burst transmission system [ D ]. Adult: the university of electronic technology, 2016, adopts a synchronization head waveform cross-correlation method to detect the frame synchronization position, in order to meet the detection accuracy in frequency offset, 5 paths of local modulated sequences with frequency offset are preset, 5 paths of local sequences are simultaneously related to a received signal, and finally, one path of the local sequences is selected to be the largest as a detection result.
MSK signal and OQPSK signal have higher similarity, FIG. 1 is a non-data-aided OQPSK signal closed-loop carrier synchronization method: the costas phase-locked loop block diagram adopted in China 201410531403.9[ P.2014-10-10 ], after DDC, is bit synchronized, and then is sent to a square spectrum estimation module, a phase discrimination module and a frequency discrimination module. The literature adopts square spectrum estimation to carry out frequency coarse estimation, and the phase-locked loop comprises a phase detector and a frequency detector, and the error output is the sum of the phase detector and the frequency detector.
In the aspect of MSK signal detection, zhang Wenzhu, research on synchronization technology in CPM burst transmission system [ D ]: the frame synchronization detection aspect of the university of electronic technology, 2016 has the weakness of sensitivity to frequency deviation, when the frequency deviation is large, the correlation peak is completely submerged, because when the frequency deviation exists, the local sequence and the receiving sequence cannot be completely aligned, and the frequency deviation leads to the correlation result not to be direct current but to be complex sine signal.
In the aspect of MSK signal demodulation, a forty-first institute of China electronics and technology group, namely, a non-data-aided OQPSK signal closed-loop carrier synchronization method: the Costas loop phase discriminator of China 201410531403.9[ P ] 2014-10-10 ] does not exclude the influence of critical points on phase discrimination, is easy to cause phase oscillation, and the Costas phase discrimination method is finally locked to the points of pi/4, 3 pi/4, -3 pi/4 and-pi/4, and cannot meet the requirements of phase locking to 0, pi/2, pi and-pi/2.
Research on frequency hopping signal channelized reception and parameter estimation thereof and realization of [ M ]. Nanjing: university of south Beijing, university of Arbitrary, 2016:15-20 adopts a channelized receiver to detect the intermediate frequency signal in real time, the channelized receiver can greatly save FPGA resources, but once fs and the extraction multiple D are determined, the channel bandwidth is also determined, the channelized receiver also has dead zones, namely, a part of frequency bands between two adjacent channels are transition bands of a filter, and the signals cannot be received. If an aliased design is employed, there is overlap of adjacent channels. The scheme adopts 1bit differential demodulation, and the 1bit differential demodulation is insensitive to frequency deviation and phase, but has the problem of high bit error rate.
Li Hui A multi-core DSP design method for frequency hopping signal demodulation [ J ]. Electronic design project, month 1 in 2020: 158-162 adopts real-time detection of frequency hopping signal frequency points, adopts a multi-core DSP to realize 1bit differential demodulation during demodulation, and also has the problem of higher incoherent demodulation error rate.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a high anti-noise and anti-frequency deviation capacity; by adopting the phase difference correction method based on DFT interpolation, the burst detection and coherent demodulation device of the high-speed frequency hopping MSK signal can be realized for accurate estimation of frequency offset and initial phase, and the corresponding burst detection and coherent demodulation method is provided.
The aim of the invention is realized by the following technical scheme: a burst detection and coherent demodulation device of high-speed frequency hopping MSK signals comprises a frequency hopping signal arrival detection module, a frequency offset and initial phase estimation module, a gain adjustment module, a phase-locked loop and bit synchronization module, a bit recovery module and a RAM; the RAM is respectively connected with the frequency hopping signal arrival detection module, the frequency offset and initial phase estimation module, the phase-locked loop and the bit synchronization module, and the phase-locked loop and the bit synchronization module are also respectively connected with the gain adjustment module and the bit recovery module; the input end of the frequency hopping signal reaching detection module is connected with the DDC module.
Further, the frequency hopping signal arrival detection module is used for carrying out baseband modulation on the UW sequence to obtain a new IQ sequence; performing sliding correlation operation on the new IQ sequence and a baseband IQ sequence output by the DDC module, wherein when the two sequences are in sliding alignment, a correlation peak appears, the position of the correlation peak is the starting position of a frequency hopping signal, and the IQ sequence with a certain length is continuously stored from the starting position of the frequency hopping signal and is stored in a RAM to obtain the IQ sequence of the frequency hopping signal;
frequency offset and initial phase estimation module: reading one-jump IQ sequence from RAM, performing de-modulation operation to obtain complex sinusoidal sequence IQ de IQ interpolation method de Frequency estimation and initial phase estimation are carried out to obtain delta f and delta fΔf and +.>Writing into RAM;
gain adjustment module: calculating the average power of the IQ data of each jump in the RAM, and dynamically adjusting the gain factor by using the average power;
phase locked loop and bit synchronization module: fetching one-hop IQ sequences in RAM, Δf andthe IQ sequence is multiplied by gain factor and then sent to phase-locked loop and bit synchronization module, and delta f and +.>As the frequency offset and initial phase of the phase-locked loop, the phase-locked is carried out by adopting a corrected costas phase-identifying methodThe gardner algorithm performs bit synchronization;
and a bit recovery module: and respectively carrying out differential operation on the I and Q sequences output by the phase-locked loop and the bit synchronization module, carrying out differential encoding after combining, recovering original information, comparing the recovered information with the original UW sequence, counting the number of UW error bits, if the number of the error bits exceeds a set threshold, indicating that the frequency hopping detection is false alarm, discarding the demodulation data, and otherwise, outputting the demodulation data.
Further, the phase-locked loop and the bit synchronization adopt two identical modules, and the two modules are crossed to process data; each path of module comprises a bit synchronization initialization unit, a bit synchronization unit, a phase discriminator, a loop filter, a phase generation unit, a DDS and an initial phase initialization unit; the bit synchronization initialization unit reads data from the RAM, the bit synchronization unit is respectively connected with the bit synchronization initialization unit, the DDS, the phase discriminator and the bit recovery module, the loop filter is respectively connected with the phase discriminator and the phase generation unit, the phase generation unit is respectively connected with the DDS and the initial phase initialization unit, and the DDS and the initial phase initialization unit are respectively connected with the RAM.
Another object of the present invention is to provide a burst detection and coherent demodulation method of a high-speed frequency hopping MSK signal, including the steps of:
s1, performing frequency hopping signal arrival detection, wherein the specific detection is as follows: if the UW sequence length is 64 bits and the sampling rate is 4 times of the information rate, the IQ obtained after the UW sequence is subjected to baseband modulation uw Sequence length 256; then pair IQ according to uw The sequence and the baseband signal IQ are subjected to cross-correlation calculation:
where k=1, 2,3, …,256,IQ representation uw Sequence ith value, conj () represents conjugation;
then, modeling corre (k) to obtain a result which is recorded as abs_corre (k);
window sliding calculations are performed on abs_corre (k) using 256 size windows: dividing the abs_corre (k) sliding window intermediate value by the average value in the window to obtain div (k); div (k) is compared with a preset threshold th, if the div (k) exceeds th, the arrival of a frequency hopping signal is detected, k corresponding to the maximum value of abs_corre (k) is taken as a starting position of the frequency hopping signal, an IQ sequence is continuously stored from the starting position of the frequency hopping signal as the frequency hopping signal, and the IQ sequence is stored in a RAM;
s2, carrying out frequency offset and initial phase estimation, wherein the specific implementation method comprises the following steps:
s21, extracting a one-hop IQ sequence from the RAM, and calculating a de-modulation sequence according to the following formula:
IQ (i) refers to the i-th value of the IQ sequence;
s22, willDivided into a group of data, denoted as IQ de1 ；/>Divided into another group of data, denoted as IQ de2 ；
S23, performing DFT on the two groups of data respectively, and marking the results as DFT1 and DFT2;
s24, calculating the maximum corresponding position of any group of modes of DFT1 and DFT2, and marking the maximum corresponding position as j;
s25, calculating phase angles of the j positions of the first group and the second groupAnd->Value range (-pi, pi); and calculates the phase angle difference:
s26, let δ=ΔΦ+2pi k, convert δ into (-pi, pi) range;
s27, dividing delta by 2 pi to obtain normalized delta, wherein the range is [ -0.5,0.5];
s28, calculating frequency offset delta f= (k-delta) fs/N, wherein fs is the sampling rate, and N is the number of DFT conversion points;
s29, calculating an initial phase angle
S3, phase-locked loop and bit synchronization operation, wherein the specific method comprises the following steps:
s31 reading initial phase angle from RAMAnd frequency offset delta f, and initializing a phase generating module as an initial phase of the DDS to finish initial phase correction and frequency correction;
s32, initializing a first sampling point of an IQ sequence by bit synchronization as an optimal sampling point, performing bit synchronization once every two code elements by adopting a gardner algorithm, outputting 3 IQ values, and sending the IQ values to a phase discriminator;
s33, the phase discriminator respectively adopts a corrected costas phase discrimination method to discriminate the phase according to 3 IQ values, then takes the average value of the 3 phases as the phase discrimination output, obtains the phase correction after the output passes through a second-order loop filter of an integral link and a proportional link, and feeds back the phase correction to a phase generator to control the DDS so as to complete the phase locking function;
the concrete implementation method of the corrected costas phase discrimination method comprises the following steps: respectively taking the phases of the I and Q sequences as a horizontal axis and a vertical axis, and taking the same point of the phases as an origin to establish a two-dimensional coordinate system; dividing a region with a slope of +/-0.2 around a straight line with a slope of +/-0.5 into a non-phase discrimination region, and then carrying out phase discrimination by using a costas phase discrimination method;
s34, after the DDS completes the phase locking function, the bit synchronization module outputs synchronous IQ data and sends the synchronous IQ data to the bit recovery module;
s4, carrying out bit recovery: eliminating zero crossing points of the IQ data obtained by the previous module to obtain IQ data without redundant information; respectively judging the I and Q as 0 and 1, respectively performing exclusive OR of front and back bits on the I and Q paths, and then combining the paths; differentially encoding the combined data to recover the original information; and comparing the recovered information with the original UW sequence, counting the number of UW error bits, if the number of the error bits exceeds a set threshold, indicating that the frequency hopping detection is false alarm, discarding the demodulation data, otherwise, outputting the demodulation data.
The beneficial effects of the invention are as follows:
1. the invention uses the correlation detection algorithm to carry out convolution operation on the new IQ sequence obtained after the baseband IQ sequence and the UW sequence are modulated, the multiplication and accumulation are carried out on four items, the accumulation result is modulo, when the two sequences slide and align, the correlation peak appears, so as to detect the arrival of the burst signal, and the point with the maximum correlation peak corresponds to the starting point of the burst frame. The algorithm is applied to burst detection, has good anti-noise and anti-frequency deviation capacity, the frequency deviation can reach 50% of the code element rate, and compared with the common correlation detection (multiplication and accumulation of two terms), the anti-frequency deviation capacity is weaker (less than 10% of the code element rate), and the anti-frequency deviation capacity is obviously improved.
2. The frequency offset and initial phase estimation of the received signal adopts a phase difference correction method based on DFT interpolation, so that the accurate estimation of the frequency offset and the initial phase can be realized, the frequency estimation error is within +/-100 Hz (the frequency estimation has no error under the ideal condition of no noise). Accurate frequency estimation helps to lock the signal fast in coherent demodulation.
3. The traditional costas loop is improved, so that the MSK signal phase is locked to 0, pi/2, pi and-pi/2 points, and the phase estimation is not carried out on the points near pi/4, 3 pi/4, -3 pi/4 and-pi/4, so that the phase jump can be effectively reduced, the demodulation stability is improved, and the bit error rate is reduced.
4. The invention completes burst detection and coherent demodulation of the frequency hopping signal under the condition of unknown frequency hopping sequence, solves the difficult problem of difficult synchronization of blind receiving coherent demodulation of the frequency hopping signal, improves the error code performance, and is beneficial to obtaining enemy information under low signal-to-noise ratio.
Drawings
FIG. 1 is a diagram of a prior art phase locked loop implementation;
fig. 2 is a schematic diagram of a burst detection and coherent demodulation device for a high-speed frequency hopping MSK signal according to the present invention;
FIG. 3 is a schematic diagram of a phase locked loop and bit sync module;
FIG. 4 is a schematic diagram of window slide calculation;
FIG. 5 is a schematic diagram of phase discrimination;
fig. 6 is a locked constellation;
fig. 7 is a graph of bit error rate.
Detailed Description
The technical scheme of the invention is further described below with reference to the accompanying drawings.
As shown in FIG. 2, the burst detection and coherent demodulation device of the high-speed frequency hopping MSK signal comprises a frequency hopping signal arrival detection module, a frequency offset and initial phase estimation module, a gain adjustment module, a phase-locked loop and bit synchronization module, a bit recovery module and a RAM; the RAM is respectively connected with the frequency hopping signal arrival detection module, the frequency offset and initial phase estimation module, the phase-locked loop and the bit synchronization module, and the phase-locked loop and the bit synchronization module are also respectively connected with the gain adjustment module and the bit recovery module; the input end of the frequency hopping signal reaching detection module is connected with the DDC module. The frequency hopping signal arrival detection module is provided with N detection channels, and the N detection channels correspondingly detect N different frequency points, such as N=16, 32 and the like; each detection channel is respectively connected with different frequency point processing units of a DDC (digital down conversion) module, and the input of the DDC module is an intermediate frequency signal.
The frequency hopping signal arrival detection module is used for carrying out baseband modulation on the UW sequence to obtain a new IQ sequence; performing sliding correlation operation on the new IQ sequence and a baseband IQ sequence output by the DDC module, wherein when the two sequences are in sliding alignment, a correlation peak appears, the position of the correlation peak is the starting position of a frequency hopping signal, and the IQ sequence with a certain length is continuously stored from the starting position of the frequency hopping signal and is stored in a RAM to obtain the IQ sequence of the frequency hopping signal;
frequency offset and initial phase estimation module: reading one-jump IQ sequence from RAM, performing de-modulation operation to obtain complex sinusoidal sequence IQ de IQ interpolation method de Frequency estimation and initial phase estimation are carried out to obtain delta f and delta fΔf and +.>Writing into RAM;
gain adjustment module: calculating the average power of the IQ data of each jump in the RAM, and dynamically adjusting the gain factor by using the average power;
phase locked loop and bit synchronization module: fetching one-hop IQ sequences in RAM, Δf andthe IQ sequence is multiplied by gain factor and then sent to phase-locked loop and bit synchronization module, and delta f and +.>As the frequency offset and the initial phase of the phase-locked loop, adopting a corrected costas phase-identifying method to carry out phase locking, and carrying out bit synchronization by a gardner algorithm;
and a bit recovery module: and respectively carrying out differential operation on the I and Q sequences output by the phase-locked loop and the bit synchronization module, carrying out differential encoding after combining, recovering original information, comparing the recovered information with the original UW sequence, counting the number of UW error bits, if the number of the error bits exceeds a set threshold, indicating that the frequency hopping detection is false alarm, discarding the demodulation data, and otherwise, outputting the demodulation data.
The phase-locked loop and the bit synchronization adopt two identical modules, and the two modules are crossed to process data; as shown in fig. 3, each path of module includes a bit synchronization initializing unit, a bit synchronization unit, a phase discriminator, a loop filter, a phase generating unit, a DDS and an initial phase initializing unit; the bit synchronization initialization unit reads data from the RAM, the bit synchronization unit is respectively connected with the bit synchronization initialization unit, the DDS, the phase discriminator and the bit recovery module, the loop filter is respectively connected with the phase discriminator and the phase generation unit, the phase generation unit is respectively connected with the DDS and the initial phase initialization unit, and the DDS and the initial phase initialization unit are respectively connected with the RAM.
A burst detection and coherent demodulation method of a high-speed frequency hopping MSK signal comprises the following steps:
s1, performing frequency hopping signal arrival detection, wherein the specific detection is as follows: if the UW sequence length is 64 bits and the sampling rate is 4 times of the information rate (the code rate of the transmission signal), the IQ obtained by baseband modulation of the UW sequence uw Sequence length 256; then pair IQ according to uw The sequence and the baseband signal IQ are subjected to cross-correlation calculation:
where k=1, 2,3, …,256,IQ representation uw Sequence ith value, conj () represents conjugation;
then, modeling corre (k) to obtain a result as a correlation value, and marking the result as abs_corre (k);
window sliding calculations are performed on abs_corre (k) using 256 size windows, as shown in fig. 4: dividing the abs_corre (k) sliding window intermediate value by the average value in the window to obtain div (k); div (k) is compared with a preset threshold th, if the div (k) exceeds th, the arrival of a frequency hopping signal is detected, k corresponding to the maximum value of abs_corre (k) is taken as a starting position of the frequency hopping signal, an IQ sequence is continuously stored from the starting position of the frequency hopping signal as the frequency hopping signal, and the IQ sequence is stored in a RAM;
s2, carrying out frequency offset and initial phase estimation, wherein the specific implementation method comprises the following steps:
s21, extracting a one-hop IQ sequence from the RAM, and calculating a de-modulation sequence according to the following formula:
IQ (i) refers to the i-th value of the IQ sequence;
s22, willDivided into a group of data, denoted as IQ de1 ；/>Divided into another group of data, denoted as IQ de2 ；
S23, performing DFT on the two groups of data respectively, and marking the results as DFT1 and DFT2;
s24, calculating the maximum corresponding position of any group of modes of DFT1 and DFT2, and marking the maximum corresponding position as j;
s25, calculating phase angles of the j positions of the first group and the second groupAnd->Value range (-pi, pi); and calculates the phase angle difference:
s26, let δ=ΔΦ+2pi k, convert δ into (-pi, pi) range;
s27, dividing delta by 2 pi to obtain normalized delta, wherein the range is [ -0.5,0.5];
s28, calculating frequency offset delta f= (k-delta) fs/N, wherein fs is the sampling rate, and N is the number of DFT conversion points;
s29, calculating an initial phase angle
S3, phase-locked loop and bit synchronization operation, wherein the specific method comprises the following steps:
s31 reading initial phase angle from RAMThe frequency offset delta f is used for initializing a phase generating module as an initial phase of the DDS, completing initial phase correction and frequency correction, and sending corrected IQ to a bit synchronizing module;
s32, initializing a first sampling point of an IQ sequence by bit synchronization as an optimal sampling point, performing bit synchronization once every two code elements by adopting a gardner algorithm, outputting 3 IQ values, and sending the IQ values to a phase discriminator;
s33, the phase discriminator respectively adopts a corrected costas phase discrimination method to discriminate the phase according to 3 IQ values, then takes the average value of the 3 phases as the phase discrimination output, obtains the phase correction after the output passes through a second-order loop filter of an integral link and a proportional link, and feeds back the phase correction to a phase generator to control the DDS so as to complete the phase locking function;
the concrete implementation method of the corrected costas phase discrimination method comprises the following steps: respectively taking the phases of the I and Q sequences as a horizontal axis and a vertical axis, and taking the same point of the phases as an origin to establish a two-dimensional coordinate system; dividing a region with the slope deviation of +/-0.2 around a straight line with the slope of +/-0.5 into a non-phase discrimination region, namely a region between two dividing lines in FIG. 5, and then carrying out phase discrimination by using a costas phase discrimination method; in the figure, the black solid point is an ideal locking point, when the IQ point falls in the "+" area, the phase is indicated to be shifted clockwise, a positive value is output to the loop filter, the DDS phase is increased in a stepping manner, and the phase is corrected to "-"; similarly, when the IQ point falls in the "-" region, indicating that the phase is shifted counterclockwise, outputting a negative value to the loop filter, reducing the DDS phase step, and correcting the phase toward "+"; when IQ falls in a 'phase discrimination free region' far from an ideal point, the sample is greatly influenced by noise and does not participate in phase discrimination, and the anti-noise level is improved through the operation. The actual measurement shows that the slope of the dividing line is about 0.7, and the effect is most obvious.
S34, after the DDS completes the phase locking function, the bit synchronization module outputs synchronous IQ data (represented by an IQ constellation diagram after phase locking, as shown in FIG. 6) and sends the synchronous IQ data to the bit recovery module;
s4, carrying out bit recovery: eliminating zero crossing points of the IQ data obtained by the previous module to obtain IQ data without redundant information; respectively judging the I and Q as 0 and 1, respectively performing exclusive OR of front and back bits on the I and Q paths, and then combining the paths; differentially encoding the combined data to recover the original information; and comparing the recovered information with the original UW sequence, counting the number of UW error bits, if the number of the error bits exceeds a set threshold, indicating that the frequency hopping detection is false alarm, discarding the demodulation data, otherwise, outputting the demodulation data.
The method of the invention can obtain better error code performance under lower signal-to-noise ratio, which is far superior to the MSK incoherent demodulation method under high-speed frequency hopping, and the actual measured performance parameters are as follows:
phase-locked loop locking threshold: e (E) b /N 0 ＝8dB；
Bit error rate:
when E is b /N 0 ＝8dB，BER＝1.5e-3；
When E is b /N 0 ＝9dB，BER＝3.1e-4；
When E is b /N 0 ＝10dB，BER＝5.2e-5；
When E is b /N 0 ＝11dB，BER＝4.0e-6；
The bit error rate graph is shown in fig. 7.
Those of ordinary skill in the art will recognize that the embodiments described herein are for the purpose of aiding the reader in understanding the principles of the present invention and should be understood that the scope of the invention is not limited to such specific statements and embodiments. Those of ordinary skill in the art can make various other specific modifications and combinations from the teachings of the present disclosure without departing from the spirit thereof, and such modifications and combinations remain within the scope of the present disclosure.
Claims (3)
1. The burst detection and coherent demodulation device of the high-speed frequency hopping MSK signal is characterized by comprising a frequency hopping signal arrival detection module, a frequency offset and initial phase estimation module, a gain adjustment module, a phase-locked loop and bit synchronization module, a bit recovery module and a RAM; the RAM is respectively connected with the frequency hopping signal arrival detection module, the frequency offset and initial phase estimation module, the phase-locked loop and the bit synchronization module, and the phase-locked loop and the bit synchronization module are also respectively connected with the gain adjustment module and the bit recovery module; the input end of the frequency hopping signal reaching detection module is connected with the DDC module;
the frequency hopping signal arrival detection module is used for carrying out baseband modulation on the UW sequence to obtain a new IQ sequence; performing sliding correlation operation on the new IQ sequence and a baseband IQ sequence output by the DDC module, wherein when the two sequences are in sliding alignment, a correlation peak appears, the position of the correlation peak is the starting position of a frequency hopping signal, and the IQ sequence with a certain length is continuously stored from the starting position of the frequency hopping signal and is stored in a RAM to obtain the IQ sequence of the frequency hopping signal;
frequency offset and initial phase estimation module: reading one-jump IQ sequence from RAM, performing de-modulation operation to obtain complex sinusoidal sequence IQ de IQ interpolation method de Frequency estimation and initial phase estimation are carried out to obtain delta f and delta fΔf and +.>Writing into RAM;
gain adjustment module: calculating the average power of the IQ data of each jump in the RAM, and dynamically adjusting the gain factor by using the average power;
phase locked loop and bit synchronization module: fetching one-hop IQ sequences in RAM, Δf andthe IQ sequence is multiplied by gain factor and then sent to phase-locked loop and bit synchronization module, and delta f and +.>As the frequency offset and the initial phase of the phase-locked loop, adopting a corrected costas phase-identifying method to carry out phase locking, and carrying out bit synchronization by a gardner algorithm;
and a bit recovery module: and respectively carrying out differential operation on the I and Q sequences output by the phase-locked loop and the bit synchronization module, carrying out differential encoding after combining, recovering original information, comparing the recovered information with the original UW sequence, counting the number of UW error bits, if the number of the error bits exceeds a set threshold, indicating that the frequency hopping detection is false alarm, discarding the demodulation data, and otherwise, outputting the demodulation data.
2. The burst detection and coherent demodulation apparatus of high-speed frequency hopping MSK signal according to claim 1, wherein the phase-locked loop and the bit synchronization adopt two identical modules, and the two modules cross to perform data processing; each path of module comprises a bit synchronization initialization unit, a bit synchronization unit, a phase discriminator, a loop filter, a phase generation unit, a DDS and an initial phase initialization unit; the bit synchronization initialization unit reads data from the RAM, the bit synchronization unit is respectively connected with the bit synchronization initialization unit, the DDS, the phase discriminator and the bit recovery module, the loop filter is respectively connected with the phase discriminator and the phase generation unit, the phase generation unit is respectively connected with the DDS and the initial phase initialization unit, and the DDS and the initial phase initialization unit are respectively connected with the RAM.
3. A burst detection and coherent demodulation method of a high-speed frequency hopping MSK signal, implemented by the apparatus of claim 1 or 2, comprising the steps of:
s1, performing frequency hopping signal arrival detection, wherein the specific detection is as follows: if the UW sequence length is 64 bits and the sampling rate is 4 times of the information rate, the IQ obtained after the UW sequence is subjected to baseband modulation uw The sequence length is as follows: 64×4=256; then pair IQ according to uw The sequence and the baseband signal IQ are subjected to cross-correlation calculation:
where k=1, 2,3, …,256,IQ representation uw Sequence ith value, conj () represents conjugation;
then, modeling corre (k) to obtain a result which is recorded as abs_corre (k);
window sliding calculations are performed on abs_corre (k) using 256 size windows: dividing the abs_corre (k) sliding window intermediate value by the average value in the window to obtain div (k); div (k) is compared with a preset threshold th, if the div (k) exceeds th, the arrival of a frequency hopping signal is detected, k corresponding to the maximum value of abs_corre (k) is taken as a starting position of the frequency hopping signal, an IQ sequence is continuously stored from the starting position of the frequency hopping signal as the frequency hopping signal, and the IQ sequence is stored in a RAM;
s2, carrying out frequency offset and initial phase estimation, wherein the specific implementation method comprises the following steps:
s21, extracting a one-hop IQ sequence from the RAM, and calculating a de-modulation sequence according to the following formula:
IQ (i) refers to the i-th value of the IQ sequence;
s22, willDivided into a group of data, denoted as IQ de1 ；/>Divided into another group of data, denoted as IQ de2 ；
S23, performing DFT on the two groups of data respectively, and marking the results as DFT1 and DFT2;
s24, calculating the maximum corresponding position of any group of modes of DFT1 and DFT2, and marking the maximum corresponding position as j;
s25, calculating phase angles of the j positions of the first group and the second groupAnd->Value range (-pi, pi); and calculates the phase angle difference:
s26, let δ=ΔΦ+2pi k, convert δ into (-pi, pi) range;
s27, dividing delta by 2 pi to obtain normalized delta', wherein the range is [ -0.5,0.5];
s28, calculating frequency offset delta f= (k-delta'). Fs/N, wherein fs is the sampling rate, and N is the number of DFT conversion points;
s29, calculating an initial phase angle
S3, phase-locked loop and bit synchronization operation, wherein the specific method comprises the following steps:
s31 reading initial phase angle from RAMAnd frequency offset delta f, and initializing a phase generating module as an initial phase of the DDS to finish initial phase correction and frequency correction;
s32, initializing a first sampling point of an IQ sequence by bit synchronization as an optimal sampling point, performing bit synchronization once every two code elements by adopting a gardner algorithm, outputting 3 IQ values, and sending the IQ values to a phase discriminator;
s33, the phase discriminator respectively adopts a corrected costas phase discrimination method to discriminate the phase according to 3 IQ values, then takes the average value of the 3 phases as the phase discrimination output, obtains the phase correction after the output passes through a second-order loop filter of an integral link and a proportional link, and feeds back the phase correction to a phase generator to control the DDS so as to complete the phase locking function;
the concrete implementation method of the corrected costas phase discrimination method comprises the following steps: respectively taking the phases of the I and Q sequences as a horizontal axis and a vertical axis, and taking the same point of the phases as an origin to establish a two-dimensional coordinate system; dividing a region with a slope of +/-0.2 around a straight line with a slope of +/-0.5 into a non-phase discrimination region, and then carrying out phase discrimination by using a costas phase discrimination method;
s34, after the DDS completes the phase locking function, the bit synchronization module outputs synchronous IQ data and sends the synchronous IQ data to the bit recovery module;
s4, carrying out bit recovery: eliminating zero crossing points of the IQ data obtained by the previous module to obtain IQ data without redundant information; respectively judging the I and Q as 0 and 1, respectively performing exclusive OR of front and back bits on the I and Q paths, and then combining the paths; differentially encoding the combined data to recover the original information; and comparing the recovered information with the original UW sequence, counting the number of UW error bits, if the number of the error bits exceeds a set threshold, indicating that the frequency hopping detection is false alarm, discarding the demodulation data, otherwise, outputting the demodulation data.
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Denomination of invention: Burst detection and coherent demodulation device and method for high-speed frequency hopping MSK signals Granted publication date: 20230922 Pledgee: Chengdu Rural Commercial Bank Co.,Ltd. Qingyang Branch Pledgor: Chengdu Century Science Park Electronic Co.,Ltd. Registration number: Y2024980002947 |