CN115149956A - Loop control system of integrated capacitor - Google Patents
Loop control system of integrated capacitor Download PDFInfo
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- CN115149956A CN115149956A CN202110340345.1A CN202110340345A CN115149956A CN 115149956 A CN115149956 A CN 115149956A CN 202110340345 A CN202110340345 A CN 202110340345A CN 115149956 A CN115149956 A CN 115149956A
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Abstract
The invention provides a loop control system of an integrated capacitor, which is characterized in that a loop control module, a capacitor control module, an oscillator module, a counter module and a digital-to-analog conversion module are configured, wherein the counter module is used for starting counting after receiving a pulse signal of the oscillator module, determining the increase or decrease of the counting according to a carry or retreat control signal, and finally outputting a digital logic signal with a plurality of bits to the digital-to-analog conversion module. The invention can integrate the traditional external capacitor into the chip, and save the external capacitor on the premise of only increasing a small amount of chip area, so that the overall cost of the circuit system is greatly reduced.
Description
Technical Field
The invention belongs to the field of integrated circuit design and manufacture, and particularly relates to a loop control system of an integrated capacitor.
Background
In many circuit systems, in order to make a circuit normally work, a capacitor is often used to implement various functions such as compensation, delay, voltage stabilization, integration, and the like, sometimes a capacitance value of the capacitor is needed to be very large, and if the capacitor is integrated inside a chip, the capacitor occupies a considerable area, so that a common method is implemented by using a chip external capacitor.
A functional circuit implemented by using an external capacitor is shown in fig. 1, and the working method thereof is illustrated as follows: the loop control system outputs a control signal Ctrl to the capacitance control module according to the circuit requirement by detecting the working state of the system. After detecting the control signal, the capacitance control circuit performs various operations such as charging and discharging on the capacitance, thereby changing the electrical characteristics of the capacitance and outputting a signal COMP to the loop control module. The loop control module detects a change in capacitance and adjusts the loop operating mode or state until the system reaches a steady state. The process of outputting, adjusting, receiving feedback and continuing to adjust the signal is carried out throughout the system.
For the above circuit, the most common operation is shown in fig. 2, when the loop control module detects that the COMP voltage is analyzed and deemed to need to charge the capacitor, the Ctrl signal is controlled to be at a high level, so that the capacitor control module charges the capacitor, and the COMP point potential rises. When the loop control module considers that the capacitor needs to be discharged, the output Ctrl signal is at a low level, so that the capacitor control module discharges the capacitor, and the potential of the COMP point is reduced. The loop control module detects the COMP potential, controls the loop working state, continuously adjusts Ctrl signals, and finally enables the system loop to achieve the purposes of stability and the like.
In general, in order to ensure the safety and stability of a system loop, a capacitance value of a capacitor is required to be large, and if the capacitor is integrated in a chip, a considerable area is occupied, so that a common method is realized by using a capacitor externally connected to the chip. This approach necessarily results in increased system cost.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides a capacitor-integrated loop control system, which is used to solve the problem of the prior art that the capacitor needs to occupy a large chip area.
To achieve the above and other related objects, the present invention provides a loop control system of an integrated capacitor, the loop control system comprising: the circuit comprises a loop control module, a capacitance control module, an oscillator module, a counter module and a digital-to-analog conversion module; the loop control module is used for outputting a first control signal to the capacitance control module by detecting the COMP signal state; the capacitance control module is used for receiving the first control signal and sending a second control signal to the oscillator module to control the working state of the oscillator module, and the capacitance control module also outputs a carry or retreat control signal to the counter module; the oscillator module is used for generating a pulse signal to the counter module according to the second control signal; the counter module is used for starting counting according to the pulse signal, entering a carry counting mode or a back-off counting mode according to the carry or back-off control signal and finally outputting a plurality of bits of digital logic signals to the digital-to-analog conversion module; the digital-to-analog conversion module is used for decoding the received digital logic signals of a plurality of bits to generate a COMP signal, and the COMP signal is returned to the loop control module.
Optionally, the number of bits of the digital logic signal is configured according to the system precision and the system speed.
Optionally, the determining to enter a carry count mode or a back-off count mode according to the carry or back-off control signal further includes: the counter module enters a carry counting mode after receiving a carry control signal, digital logic signals output by the counter module advance by one bit every time when pulse signals are input, the counter module enters a retreat counting mode after receiving retreat control signals, and the logic signals output by the counter module retreat by one bit every time when the pulse signals are input.
Optionally, the digital logic signal output by the counter module is 3 to 16 bits.
Optionally, the digital logic signal output by the counter module is 3 bits, and after the counter module receives the pulse signal each time when receiving the carry control signal, the counter module outputs the digital logic signal sequentially increasing from the lowest bit 000 or any intermediate state in the order of 000, 001, 010, 011, 100, 101, 110, and 111; after the counter module receives the pulse signal every time when receiving the backspace control signal, the counter module outputs digital logic signals which are sequentially decreased from the highest bit 111 or any intermediate state according to the sequence of 111, 110, 101, 100, 011, 010, 001 and 000.
Optionally, after the loop control module controls the carry or the escape control signal to flip, and after the pulse signal is received again, the counter module switches from the current counting mode to the opposite counting mode.
Optionally, the precision of the digital-to-analog conversion module is related to the number of bits of the digital logic signal output by the counter module, and the precision of the digital-to-analog conversion module is improved to make the COMP signal equal to or tend to be equal to the analog potential.
Optionally, the COMP signal output by the digital-to-analog conversion module changes in a staircase-like fluctuation manner with the change of the counting mode of the counter module, and the number of bits of the digital logic signal output by the counter module is increased so that a change curve of the COMP signal is a smooth curve.
Optionally, the loop control module, the capacitance control module, the oscillator module, the counter module, and the digital-to-analog conversion module are all integrated in the same chip.
Optionally, the controlling the operating state of the oscillator module includes: controlling a frequency, duty cycle, or/and on-time parameter of the oscillator module.
As described above, the loop control system of integrated capacitor of the present invention has the following advantages:
the invention provides a loop control system of an integrated capacitor, which is characterized in that a loop control module, a capacitor control module, an oscillator module, a counter module and a digital-to-analog conversion module are configured, wherein the counter module is used for starting counting after receiving a pulse signal of the oscillator module, determining the increase or decrease of the counting according to a carry or retreat control signal, and finally outputting a digital logic signal with a plurality of bits to the digital-to-analog conversion module.
Drawings
Fig. 1 is a schematic structural diagram of a functional circuit implemented by using an external capacitor.
Fig. 2 is a schematic diagram showing a working timing principle of the functional circuit implemented by the external capacitor shown in fig. 1.
Fig. 3 is a schematic structural diagram of a loop control system of an integrated capacitor according to an embodiment of the present invention.
Fig. 4 is a schematic diagram illustrating the operation timing principle of the loop control system of the integrated capacitor according to the embodiment of the present invention.
Description of the element reference
101. Loop control module
102. Capacitance control module
103. Oscillator module
104. Counter module
105. Digital-to-analog conversion module
Detailed Description
The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 3, the present embodiment provides a loop control system of an integrated capacitor, the loop control system including: a loop control module 101, a capacitance control module 102, an oscillator module 103, a counter module 104, and a digital-to-analog conversion module 105. In other embodiments of the present disclosure, the loop control module 101, the capacitance control module 102, the oscillator module 103, the counter module 104, and the digital-to-analog conversion module 105 are all integrated in chip, and the loop control system of this embodiment integrates an external capacitor into the same chip, so that the external capacitor is saved on the premise of only increasing a small chip area, and the overall cost of the circuit system is greatly reduced.
As shown in fig. 3, the loop control module 101 is configured to output a first control signal to the capacitance control module 102 according to a system requirement by detecting a COMP signal state.
As shown in fig. 3, the capacitance control module 102 is connected to the loop control module 101, the oscillator module 103, and the counter module 104, and configured to receive the first control signal of the loop control module 101, send a second control signal to the oscillator module 103, and control a working state of the oscillator module 103, where the capacitance control module 102 further outputs a carry or a back control signal to the counter module 104 according to a system requirement. In other embodiments of the present disclosure, controlling the operating state of the oscillator module 103 includes: the frequency, duty cycle, or/and on-time parameters of the oscillator module 103 are controlled.
As shown in fig. 3, the oscillator module 103 is connected to the counter module 104, and is configured to generate a required pulse signal OSC to the counter module 104 according to the second control signal sent by the capacitance control module 102. For example, the oscillator module 103 may convert dc power into ac power with a certain frequency, so as to generate a pulse signal with a magnitude and a direction that vary with a period.
As shown in fig. 3, the counter module 104 is connected to the digital-to-analog conversion module 105, and configured to start counting according to the pulse signal received by the oscillator module 103, enter a carry counting mode or a back-off counting mode according to the carry or back-off control signal, and finally output a digital logic signal with a plurality of bits to the digital-to-analog conversion module 105.
In other embodiments of the present disclosure, the number of bits of the digital logic signal output by the counter module 104 is configured according to the system precision and the system speed. For example, the digital logic signal output by the counter module 104 is 3 to 16 bits. In other embodiments, the digital logic signal output by the counter module 104 may also be a higher number of bits, and is not limited to the examples listed herein.
In other embodiments of the present disclosure, entering the carry count mode or the escape count mode is determined according to a carry or escape control signal, and the method further includes: the counter module 104 enters a carry counting mode after receiving the carry control signal, the digital logic signal output by the counter module 104 advances by one bit each time when the pulse signal is input, the counter module 104 enters a retreat counting mode after receiving the retreat control signal, and the digital logic signal output by the counter module 104 retreats by one bit each time when the pulse signal is input.
In other embodiments of the present disclosure, the digital logic signal output by the counter module 104 is 3 bits, and after the counter module 104 receives the pulse signal each time when receiving the carry control signal, the counter module outputs the digital logic signal sequentially increasing from the lowest bit 000 or any intermediate state in the order of 000, 001, 010, 011, 100, 101, 110, and 111; when the counter module 104 receives the back-off control signal, after receiving the pulse signal each time, the counter module outputs digital logic signals sequentially decreasing from the highest bit 111 or any intermediate state in the order of 111, 110, 101, 100, 011, 010, 001, 000.
As shown in fig. 3, the digital-to-analog conversion module 105 is connected to the loop control module 101, and configured to decode the received digital logic signal with a plurality of bits to generate a corresponding COMP signal, where the COMP signal is returned to the loop control module 101.
In other embodiments of the present disclosure, for the loop control system of the integrated capacitor in this embodiment, when the loop control module 101 detects a COMP signal voltage, and the voltage is determined to be insufficient through analysis, the capacitance control module 102 outputs a control signal at a high level, the oscillator module 103 starts to operate, generates a required pulse signal according to a system requirement, transmits the pulse signal to the counter module 104 as a clock signal, the counter module 104 carries out carry or back-off processing according to the number of pulses of the pulse signal, and the capacitance control module 102 generates a control signal for carry or back-off counting and transmits the control signal to the counter module 104.
The counter module 104 detects an oscillator pulse signal OSC and a carry or back control signal, and outputs a plurality of digital logic signals, wherein the number of bits can be selected or rejected according to different requirements of system precision, speed and the like. After the counter module 104 receives the carry control signal, the digital logic signal output by the counter module 104 advances by one bit each time when the pulse signal is input, and the digital logic signal output by the counter module 104 retreats by one bit each time when the pulse signal is input after the counter module 104 receives the retreat control signal. Taking the three-bit counter module 104 as an example, when the carry or back control signal is in the carry state, the digital logic signal output by the three-bit counter module after receiving the pulse signal OSC each time can be sequentially incremented from the least significant bit 000 or any intermediate state, and the digital logic signal has the sequence of 000, 001, 010, 011, 100, 101, 110, 111; when the carry or the setback control signal is in the setback state, the digital logic signal output by the pulse signal OSC each time it is received can be sequentially decreased from the highest bit 111 or any intermediate state, and the order of the digital logic signal is 111, 110, 101, 100, 011, 010, 001, 000. For another example, when the counter module 104 is 4 bits, the digital logic signals output by the pulse signal OSC each time it is received when the carry or escape control signal is in the carry state may be sequentially incremented from the lowest bit 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111; when the carry or the depreciation control signal is in the depreciation state, the digital logic signal output by the pulse signal OSC each time is received can be sequentially decreased from the most significant bit 111 or any intermediate state, and the sequence of the digital logic signal is 1111, 1110, 1101, 1100, 1011, 1010, 1001, 1000, 0111, 0110, 0101, 0100, 0011, 0010, 0001 and 0000. After the loop control module 101 controls the carry or the escape control signal to be inverted, and receives the pulse signal again, the counter module 104 switches from the current counting mode to an opposite counting mode, where the counting mode includes a carry counting mode and an escape counting mode, and the carry counting mode and the escape counting mode are opposite counting modes.
The digital-to-analog conversion module 105 receives the digital logic signal sequence output by the counter module 104, decodes the digital logic signal sequence, generates an analog output level COMP signal and feeds the analog output level COMP signal back to the loop control module 101, the precision of the digital-to-analog conversion module 105 is related to the number of bits of the digital logic signal output by the counter module 104, and increasing the number of bits of the digital logic signal sequence output by the counter module 104 can improve the precision of the digital-to-analog conversion module 105, so that the COMP signal is equal to or tends to be equal to the analog potential, and the specific number of bits can be selected according to various requirements such as the precision requirement of the loop control system.
As shown in fig. 4, the schematic diagram of the working timing sequence of the loop control system using the 3-bit counter module 104 is shown by a Ctrl curve, an OSC curve, a forward/backward bit curve, a D0 curve, a D1 curve, and a D2 curve of fig. 4, when the counter module 104 receives a carry control signal Ctrl, the digital logic signal output by the counter module advances by one bit each time when a pulse signal is input, and when the counter module 104 receives a backward bit control signal Ctrl, the digital logic signal output by the counter module moves backward by one bit each time when a pulse signal is input. As can be seen from the COMP curve, the analog potential COMP signal fluctuates in a step shape along with the change of the counting mode of the counter module 104, and the number of bits of the digital logic signal output by the counter module 104 is increased, so that the change curve of the analog potential COMP signal is a smooth curve, thereby obtaining an effect similar to the charging and discharging of an external capacitor.
The above description is only for the sake of understanding of the three-bit counter module 104, and in practical situations, many options and optimization designs are possible. Information such as the frequency of the oscillator module 103 can be changed according to system requirements, more or less pulses can be generated in the same time, and the voltage value of the COMP signal can be increased or decreased more rapidly or slowly; the carry or back control signal is not limited to high and low levels, and can be set in various combinations.
As described above, the present invention provides a loop control system of an integrated capacitor, in which a loop control module, a capacitor control module, an oscillator module, a counter module and a digital-to-analog conversion module are configured, the counter module is configured to start counting after receiving a pulse signal of the oscillator module, and determine whether to increase or decrease the count according to a carry or a back control signal, and finally output a digital logic signal with a plurality of bits to the digital-to-analog conversion module, and increase the number of bits of the digital logic signal output by the counter module to improve the precision of digital-to-analog conversion, so that a COMP signal can approach an analog potential, thereby realizing output, adjustment, reception feedback, and continuous adjustment of a signal of the loop control system, and finally enabling the loop control system to achieve a stable effect. The invention can integrate the traditional external capacitor into the chip, and save the external capacitor on the premise of only increasing a small amount of chip area, so that the overall cost of the circuit system is greatly reduced.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A capacitive integrated loop control system, the loop control system comprising: the circuit comprises a loop control module, a capacitance control module, an oscillator module, a counter module and a digital-to-analog conversion module;
the loop control module is used for outputting a first control signal to the capacitance control module by detecting the COMP signal state;
the capacitance control module is used for receiving the first control signal and sending a second control signal to the oscillator module to control the working state of the oscillator module, and the capacitance control module also outputs a carry or retreat control signal to the counter module;
the oscillator module is used for generating a pulse signal to the counter module according to the second control signal;
the counter module is used for starting counting according to the pulse signal, entering a carry counting mode or a back-off counting mode according to the carry or back-off control signal and finally outputting a plurality of bits of digital logic signals to the digital-to-analog conversion module;
the digital-to-analog conversion module is used for decoding the received digital logic signals of a plurality of bits to generate a COMP signal, and the COMP signal is returned to the loop control module.
2. The loop control system of integrated capacitance of claim 1, wherein: and the digit of the digital logic signal is configured according to the system precision and the system speed.
3. The loop control system of integrated capacitance of claim 1, wherein: the controlling the carry counting mode or the back-off counting mode according to the carry or back-off control signal further comprises: after receiving the carry control signal, the counter module enters a carry counting mode, and the digital logic signal advances by one bit every time a pulse signal is input; and the counter module enters a back-off counting mode after receiving the back-off control signal, and the digital logic signal backs off by one bit every time a pulse signal is input.
4. The loop control system of integrated capacitance of claim 1, wherein: the digital logic signal output by the counter module is 3-16 bits.
5. The loop control system of integrated capacitance of claim 4, wherein: the digital logic signal output by the counter module is 3 bits, and after the counter module receives the pulse signal each time when receiving the carry control signal, the counter module outputs the digital logic signal which is sequentially increased from the lowest bit 000 or any intermediate state according to the sequence of 000, 001, 010, 011, 100, 101, 110 and 111; after the counter module receives the pulse signal every time when receiving the backspace control signal, the counter module outputs digital logic signals which are sequentially decreased from the highest bit 111 or any intermediate state according to the sequence of 111, 110, 101, 100, 011, 010, 001 and 000.
6. The loop control system of integrated capacitance of claim 1, wherein: and after the loop control module controls the carry or retreat control signal to be turned over and receives the pulse signal again, the counter module is switched to an opposite counting mode from the current counting mode.
7. The loop control system of integrated capacitance of claim 1, wherein: the precision of the digital-to-analog conversion module is related to the digit of the digital logic signal output by the counter module, and the precision of the digital-to-analog conversion module is improved so that the COMP signal is equal to or tends to be equal to the analog potential.
8. The loop control system of integrated capacitance of claim 1, wherein: the COMP signal output by the digital-to-analog conversion module is in stepped fluctuation along with the change of the counting mode of the counter module, and the digit of the digital logic signal output by the counter module is increased so that the change curve of the COMP signal is in a smooth curve.
9. The loop control system of integrated capacitance of claim 1, wherein: the loop control module, the capacitance control module, the oscillator module, the counter module and the digital-to-analog conversion module are all integrated in the same chip.
10. The loop control system of integrated capacitance of claim 1, wherein: the controlling the operating state of the oscillator module includes: controlling a frequency, a duty cycle, or/and an on-time parameter of the oscillator module.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110340345.1A CN115149956A (en) | 2021-03-30 | 2021-03-30 | Loop control system of integrated capacitor |
| PCT/CN2021/138246 WO2022206029A1 (en) | 2021-03-30 | 2021-12-15 | Loop control system for integrated capacitor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110340345.1A CN115149956A (en) | 2021-03-30 | 2021-03-30 | Loop control system of integrated capacitor |
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| CN115149956A true CN115149956A (en) | 2022-10-04 |
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| US6064947A (en) * | 1997-08-27 | 2000-05-16 | Texas Instruments Incorporated | Time base generator internal voltage-controlled oscillator calibration system and method |
| CN107426881B (en) * | 2017-09-07 | 2023-09-22 | 上海晶丰明源半导体股份有限公司 | Integrator, LED current ripple cancellation circuit and method |
| WO2020047776A1 (en) * | 2018-09-05 | 2020-03-12 | 上海晶丰明源半导体股份有限公司 | Low pass filter, switch control circuit, driving system, chip and method |
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