CN115149911B - Ultra-wideband front-end chip, control method and design method - Google Patents
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Abstract
The invention discloses an ultra-wideband front-end chip, a control method and a design method, wherein the ultra-wideband front-end chip comprises a reconfigurable power amplifier, a reconfigurable matching circuit and a low-noise amplifier; the reconfigurable power amplifier can be configured to be in an amplifier mode or a switch mode; the reconfigurable matching circuit is used for realizing input matching of the low-noise amplifier, output matching of the reconfigurable power amplifier and switching of a receiving/transmitting mode; the invention designs the power amplifier, the low noise amplifier and the switch in a coordinated way, and has the characteristics of large bandwidth, high linearity, good noise performance and small occupied area.
Description
Technical Field
The invention relates to the technical field of radio frequency integrated circuits, in particular to an ultra-wideband front-end chip, a control method and a design method.
Background
The front-end chip is an important component in a communication system and consists of three parts, namely a signal transmitting circuit, a signal receiving link and a receiving/transmitting switching circuit. Among them, a front-end chip composed of a power amplifier, a low noise amplifier and a single-pole double-throw switch is the most important module.
In a traditional front-end chip, the output end of a power amplifier, the input end of a low-noise amplifier and three ports of a single-pole double-throw switch are all matched to 50 omega, and then cascade connection is carried out. The design method needs more matching circuits, occupies larger area, has larger matching loss, not only deteriorates the noise performance of the low-noise amplifier, but also reduces the output power and the efficiency of the power amplifier. In addition, the switching tube may also reduce the linearity of the power amplifier. In broadband designs, performance degradation is more pronounced due to bandwidth tradeoffs with other performance.
With the advancement of mobile communication, fifth generation mobile communication (5G) is one of the focuses of global scientific and technological competition. The main 5G millimeter wave communication frequency bands are distributed in the frequency bands of 24.25-29.5GHz and 37-43.5GHz, and the total bandwidth is 11.75GHz. The 5G millimeter wave communication system puts higher requirements on the working frequency band and bandwidth of the front-end chip and the transceiver. The ultra-wideband front-end chip and the transceiver which can cover the global main 5G communication frequency band can support the global main frequency band 5G millimeter wave system, and the commercial prospect is wide.
Therefore, the ultra-wideband front-end chip with small matching loss and high linearity has high engineering application value.
Disclosure of Invention
In order to overcome the above disadvantages and shortcomings of the prior art, the present invention provides an ultra-wideband front-end chip, a control method and a design method. The invention is not only suitable for the common millimeter wave communication system, but also suitable for other communication frequency bands such as microwave and the like, and is also suitable for narrow-band design.
The purpose of the invention is realized by the following technical scheme:
an ultra-wideband front-end chip comprises a reconfigurable power amplifier, a reconfigurable matching circuit and a low-noise amplifier:
the reconfigurable matching circuit is characterized in that a first end of the reconfigurable matching circuit is an input/output end of an ultra-wideband front-end chip, a second end of the reconfigurable matching circuit is connected with the reconfigurable power amplifier, and a third end of the reconfigurable matching circuit is connected with the low-noise amplifier and used for realizing input matching of the low-noise amplifier, output matching of the reconfigurable power amplifier and switching of a receiving and transmitting mode;
the configuration modes of the reconfigurable power amplifier comprise an amplifier mode and a switch mode;
when the configuration mode of the reconfigurable power amplifier is set to be an amplifier mode, the reconfigurable matching circuit is switched to a transmitting mode, and the reconfigurable power amplifier amplifies an input signal at the input end of the reconfigurable matching circuit to obtain a first radio-frequency signal;
performing broadband impedance matching and power matching on the first radio-frequency signal through a reconfigurable matching circuit in a transmitting mode to obtain a second radio-frequency signal, and outputting the second radio-frequency signal from an input/output end of the ultra-wideband front-end chip;
when the configuration mode of the reconfigurable power amplifier is set to be a switch mode, the reconfigurable matching circuit is switched to a receiving mode;
an input signal of an input/output end of the ultra-wideband front-end chip is subjected to wideband impedance matching and noise matching through a reconfigurable matching circuit in a receiving mode to obtain a third radio frequency signal; the low-noise amplifier amplifies the third radio frequency signal to obtain a fourth radio frequency signal, and the fourth radio frequency signal is output from the output end of the low-noise amplifier.
Further, the reconfigurable power amplifier comprises a pair of common-source transistors, a pair of common-gate transistors, a bias circuit and a power supply switching circuit, wherein the common-source transistors comprise a first transistor and a second transistor, and the common-gate transistors comprise a third transistor and a fourth transistor;
the drain electrode of the first transistor is connected with the source electrode of the third transistor, and the source electrode of the first transistor is grounded;
the drain electrode of the second transistor is connected with the source electrode of a fourth transistor, and the source electrode of the second transistor is grounded;
and the drain electrode of the third transistor and the drain electrode of the fourth transistor are output ends of the reconfigurable power amplifier.
Further, the reconfigurable power amplifier further comprises a first capacitor and a second capacitor, wherein a first end of the first capacitor is connected with a drain electrode of the first transistor, and a second end of the first capacitor is connected with a grid electrode of the second transistor; and the first end of the second capacitor is connected with the drain electrode of the second transistor, and the second end of the second capacitor is connected with the grid electrode of the first transistor.
Further, the bias circuit comprises a first resistor, a second resistor, a first bias voltage and a second bias voltage; a first end of the first resistor is connected with a first bias voltage, and a second end of the first resistor is connected with a grid electrode of the first transistor; a first end of the second resistor is connected with a first bias voltage, and a second end of the second resistor is connected with a grid electrode of the second transistor; the second bias voltage is connected to the gates of the third transistor and the fourth transistor, respectively.
Further, the power switching circuit includes a fifth transistor and a sixth transistor, a source of the fifth transistor is connected to the power supply, a drain of the fifth transistor is connected to a drain of the sixth transistor, a gate of the fifth transistor is connected to a gate of the sixth transistor and is connected to the first control voltage, and a source of the sixth transistor is grounded.
Further, the reconfigurable power amplifier further comprises a driving stage amplifier, and the output end of the driving stage amplifier is connected with the grid electrode of the first transistor and the grid electrode of the second transistor.
Further, the reconfigurable matching circuit comprises a first inductor, a second inductor, a third inductor, a fourth inductor, a fifth inductor, a sixth inductor, a seventh transistor, an eighth transistor, a third capacitor, a fourth capacitor, a third resistor and a fourth resistor; the first inductor is connected with the output end of the reconfigurable power amplifier, and a tap of the first inductor is connected with the power supply switching circuit;
the first end of the second inductor is connected with the second end of the fourth inductor and the drain electrode of the seventh transistor respectively; the second end of the second inductor is respectively connected with the second end of the third inductor, the first end of the third capacitor and the first end of the fourth capacitor; the second end of the third capacitor is an input/output port of the ultra-wideband front-end chip; a second end of the fourth capacitor is grounded;
the first end of the third inductor is connected with the first end of the fifth inductor, the first end of the sixth inductor and the drain electrode of the eighth transistor respectively; the second end of the sixth inductor is connected with the input end of the low noise amplifier, and the first end of the fourth inductor is respectively connected with the second end of the fifth inductor and a third bias voltage, wherein the third bias voltage is the bias voltage of the input stage of the low noise amplifier;
the source electrode of the seventh transistor is grounded, the grid electrode of the seventh transistor is connected with the first end of a third resistor, and the second end of the third resistor is connected with a second control voltage;
the source of the eighth transistor is grounded, the gate of the eighth transistor is connected to the first end of the fourth resistor, and the second end of the fourth resistor is connected to a third control voltage.
Further, the first inductor, the second inductor and the third inductor are coupled in pairs; and the fourth inductor, the fifth inductor and the sixth inductor are coupled in pairs.
A control method of an ultra-wideband front-end chip comprises the following steps:
turning off the low noise amplifier, setting the first control voltage and the third bias voltage to be low level, and setting the second control voltage and the third control voltage to be high level; at this time, the fifth transistor, the seventh transistor and the eighth transistor are turned on, the sixth transistor is turned off, the reconfigurable power amplifier is configured in an amplifier mode, the reconfigurable matching circuit is switched to a transmission mode, and the front-end chip works in the transmission mode;
the reconfigurable power amplifier amplifies an input signal thereof to obtain a first radio frequency signal; and the reconfigurable matching circuit is used for performing broadband impedance matching and power matching on the first radio frequency signal to obtain a second radio frequency signal and outputting the second radio frequency signal from the input/output end of the ultra-wideband front-end chip.
Turning on a low noise amplifier, setting a first control voltage, a first bias voltage and a second bias voltage to a high level, and setting a second control voltage and a third control voltage to a low level; at the moment, the fifth transistor, the seventh transistor and the eighth transistor are turned off, the sixth transistor is turned on, the reconfigurable power amplifier is configured to be in a switch mode, the reconfigurable matching circuit is switched to be in a receiving mode, and the front-end chip works in the receiving mode;
an input signal of an input/output end of the ultra-wideband front-end chip is subjected to wideband impedance matching and noise matching through a reconfigurable matching circuit in a receiving mode to obtain a third radio frequency signal; and amplifying the third radio frequency signal through the low-noise amplifier to obtain a fourth radio frequency signal, and outputting the fourth radio frequency signal from the output end of the low-noise amplifier.
A collaborative design method comprises the following steps:
the first step is as follows: setting the first control voltage and the third bias voltage to a low level, and setting the second control voltage and the third control voltage to a high level; at this time, the fifth transistor, the seventh transistor and the eighth transistor are turned on, the sixth transistor is turned off, the low noise amplifier is turned off, and the front-end chip works in an emission mode; the seventh transistor and the eighth transistor are grounded in a conducting mode, so that the influence of the input impedance of the low-noise amplifier on the output impedance matching of the reconfigurable power amplifier is reduced; calculating initial values of a first inductor, a second inductor, a third capacitor and a fourth capacitor according to the output impedance of the reconfigurable power amplifier, and realizing output matching of the reconfigurable amplifier;
the second step: setting a first control voltage, a first bias voltage and a second bias voltage to a high level, and setting a second control voltage and a third control voltage to a low level; at the moment, the fifth transistor, the seventh transistor and the eighth transistor are closed, the sixth transistor is conducted, the reconfigurable power amplifier is configured to be in a switch mode, and the front-end chip works in a receiving mode; the reconfigurable power amplifier and the power supply switching circuit in the switch mode short circuit the first inductor to the ground, so that the influence of the output impedance of the reconfigurable power amplifier on the input impedance matching of the low-noise amplifier is reduced; calculating initial values of a fourth inductor, a fifth inductor, a sixth inductor, a seventh transistor turn-off capacitor and an eighth transistor turn-off capacitor according to the input impedance of the low noise amplifier and the initial values of the first inductor, the second inductor, the third capacitor and the fourth capacitor obtained in the first step, and realizing input matching of the low noise amplifier;
the third step: on the premise of meeting the noise coefficient index, each component is optimized, and the ultra-wideband front-end chip is realized.
Compared with the prior art, the invention has the following advantages and beneficial effects:
1. according to the ultra-wideband front-end chip provided by the invention, the reconfigurable matching circuit adopts an inductive coupling mode to complete output matching of the reconfigurable power amplifier and input matching of the low-noise amplifier, so that a wider working bandwidth is realized.
2. According to the ultra-wideband front-end chip provided by the invention, the reconfigurable power amplifier can be configured to be in an amplifier mode or a switch mode, a switch tube of a transmitting channel is cancelled, and the linearity of the transmitting channel of the front-end chip is effectively improved.
3. The ultra-wideband front-end chip provided by the invention realizes the function of a single-pole double-throw switch by using the reconfigurable matching circuit and the reconfigurable power amplifier, the low-noise amplifier and the switch are cooperatively designed, so that the use of the matching circuit is reduced, the loss of the matching circuit is reduced, the better noise performance and higher output power and efficiency are realized, and the occupied area of the front-end chip is reduced.
Drawings
Fig. 1 is a block diagram of an ultra-wideband front-end chip according to embodiment 1 of the present invention.
Fig. 2 is a schematic circuit structure diagram of an ultra-wideband front-end chip in embodiment 1 of the present invention.
Fig. 3 is a diagram of an experimental result of a variation of gain, return loss and noise coefficient with frequency of the ultra-wideband front-end chip in the receiving mode according to embodiment 1 of the present invention.
Fig. 4 is a graph of an experimental result of the change of the gain and the return loss with the frequency of the ultra-wideband front-end chip in the transmission mode according to embodiment 1 of the present invention.
Fig. 5 is a graph of an experimental result of the variation of the saturated output power (Psat) and the output 1dB compression point (OP 1 dB) with frequency of the ultra-wideband terminal chip in the transmission mode according to embodiment 1 of the present invention.
Detailed Description
The present invention will be described in further detail with reference to examples, but the embodiments of the present invention are not limited thereto.
Examples
As shown in fig. 1, the present embodiment provides an ultra-wideband front-end chip, which may be applied in a transceiver, and mainly includes a reconfigurable power amplifier 101, a reconfigurable matching circuit 102, and a low noise amplifier 103.
The first end of the reconfigurable matching circuit 102 is an input/output end of an ultra-wideband front-end chip, the second end is connected with the reconfigurable power amplifier 101, and the third end is connected with the low-noise amplifier 103;
in the embodiment, the reconfigurable matching circuit is used for realizing input matching of the low-noise amplifier, output matching of the reconfigurable power amplifier and switching of a receiving and transmitting mode;
in this embodiment, the reconfigurable power amplifier may be configured in an amplifier mode or a switch mode.
As shown in fig. 2, in the schematic circuit structure of the ultra-wideband front-end chip of this embodiment, a port 1 is an input/output port of the ultra-wideband front-end chip, a port 2 is an input port for transmitting a signal, i.e., a reconfigurable power amplifier, and a port 3 is an output port for receiving a signal, i.e., a low-noise amplifier output.
In this embodiment, the reconfigurable power amplifier includes a pair of common-source transistors, a pair of common-gate transistors, a bias circuit, a power switching circuit, and a driver stage amplifier circuit.
The method specifically comprises the following steps: the common-source-connected transistor includes a first transistor M1 and a second transistor M2, and the common-gate-connected transistor includes a third transistor M3 and a fourth transistor M4. The connection mode is as follows: the drain electrode of the first transistor M1 is connected with the source electrode of the third transistor M3, and the source electrode of the first transistor M1 is grounded; the drain electrode of the second transistor M2 is connected with the source electrode of the fourth transistor M4, and the source electrode of the second transistor M2 is grounded; the drains of the third transistor M3 and the fourth transistor M4 are output terminals of the reconfigurable power amplifier, and the output terminal of the driver stage amplifier is connected to the gates of the first transistor M1 and the second transistor M2.
In this embodiment, in order to stabilize the reconfigurable power amplifier and improve the gain, the reconfigurable power amplifier further includes a first capacitor C1 and a second capacitor C2; a first end of the first capacitor C1 is connected to the drain of the first transistor M1, and a second end is connected to the gate of the second transistor M2; a first end of the second capacitor C2 is connected to the drain of the second transistor M2, and a second end is connected to the gate of the first transistor M1.
In this embodiment, the bias circuit includes a first resistor R1, a second resistor R2, a first bias voltage VB1, and a second bias voltage VB2; a first end of the first resistor R1 is connected to the first bias voltage VB1, and a second end of the first resistor R1 is connected to the gate of the first transistor M1; a first end of the second resistor R2 is connected to the first bias voltage VB1, and a second end of the second resistor R2 is connected to the gate of the second transistor M2; the second bias voltage VB2 is connected to the gate of the third transistor M3 and the gate of the fourth transistor M4.
In this embodiment, the power switching circuit includes a fifth transistor M5 and a sixth transistor M6; the source of the fifth transistor M5 is connected to the power supply VDD1, the drain of the fifth transistor M5 is connected to the drain of the sixth transistor M6, the gate of the fifth transistor M5 is connected to the gate of the sixth transistor M6 and to the first control voltage VC1, and the source of the sixth transistor M6 is grounded.
When the reconfigurable power amplifier is in an amplifier mode, the common-source-connected transistor and the common-gate-connected transistor jointly realize a signal amplification function with higher gain; in a switching mode, the common-source transistor and the common-gate transistor are short-circuited to the ground, the influence of the output impedance of the reconfigurable power amplifier on a broadband low-noise input impedance matching circuit of the low-noise amplifier is reduced, and the isolation of the ultra-wideband front-end chip can be improved.
In this embodiment, the reconfigurable matching circuit includes a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, a fifth inductor L5, a sixth inductor L6, a seventh transistor M7, an eighth transistor M8, a third capacitor C3, a fourth capacitor C4, a third resistor R3, and a fourth resistor R4.
The concrete connection is as follows: the first inductor L1 is connected to the output end of the reconfigurable power amplifier, and a center tap of the first inductor L1 is connected to a drain of the fifth transistor M5 of the power supply switching circuit.
A first end of the second inductor L2 is connected to a second end of the fourth inductor L4 and a drain of the seventh transistor M7; the second end of the second inductor L2 is connected to the second end of the third inductor L3, the first end of the third capacitor C3, and the first end of the fourth capacitor C4; the second end of the third capacitor C3 is an input/output port of the ultra-wideband front-end chip; the second end of the fourth capacitor C4 is grounded; a first end of the third inductor L3 is connected to a first end of the fifth inductor L5, a first end of the sixth inductor L6, and a drain of the eighth transistor M8, and a first end of the fourth inductor L4 is connected to a second end of the fifth inductor L5 and to a third bias voltage VB3, where the third bias voltage VB3 is a bias voltage of the input stage of the low noise amplifier; a second end of the sixth inductor L6 is connected to the input end of the low noise amplifier, a source of the seventh transistor M7 is grounded, a gate of the seventh transistor M7 is connected to a first end of the third resistor R3, and a second end of the third resistor R3 is connected to the second control voltage VC 2;
the source of the eighth transistor M8 is grounded, the gate of the eighth transistor M8 is connected to the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is connected to the third control voltage VC 3.
Further, in order to improve the output impedance matching bandwidth of the reconfigurable power amplifier and reduce loss, the first inductor, the second inductor and the third inductor are coupled in pairs, and the fourth inductor, the fifth inductor and the sixth inductor are coupled in pairs.
The method for controlling the ultra-wideband front-end chip in the embodiment specifically comprises the following steps:
turning off the low noise amplifier, setting the first control voltage VC1 and the third bias voltage VB3 to be at a low level, and setting the second control voltage VC2 and the third control voltage VC3 to be at a high level; at this time, the fifth transistor, the seventh transistor and the eighth transistor are turned on, the sixth transistor is turned off, the reconfigurable power amplifier is configured to be in an amplifier mode, the reconfigurable matching circuit is switched to be in a transmitting mode, and the front-end chip works in the transmitting mode;
the reconfigurable power amplifier amplifies an input signal of the reconfigurable power amplifier to obtain a first radio frequency signal; and the reconfigurable matching circuit is used for performing broadband impedance matching and power matching on the first radio frequency signal to obtain a second radio frequency signal and outputting the second radio frequency signal from the input/output end of the ultra-wideband front-end chip.
Turning on a low noise amplifier, setting a first control voltage VC1, a first bias voltage VB1 and a second bias voltage VB2 to a high level, and setting a second control voltage VC2 and a third control voltage VC3 to a low level; at the moment, the fifth transistor, the seventh transistor and the eighth transistor are closed, the sixth transistor is conducted, the reconfigurable power amplifier is configured to be in a switch mode, the reconfigurable matching circuit is switched to be in a receiving mode, and the front-end chip works in the receiving mode; an input signal of an input/output end of the ultra-wideband front-end chip is subjected to wideband impedance matching and noise matching through a reconfigurable matching circuit in a receiving mode to obtain a third radio frequency signal; and amplifying the third radio frequency signal through the low noise amplifier to obtain a fourth radio frequency signal, and outputting the fourth radio frequency signal from the output end of the low noise amplifier.
The cooperative design method of the ultra-wideband front-end chip comprises the following steps:
a first step of setting the first control voltage VC1 and the third bias voltage VB3 to a low level, and setting the second control voltage VC2 and the third control voltage VC3 to a high level; at this time, the fifth transistor M5, the seventh transistor M7 and the eighth transistor M8 are turned on, the sixth transistor M6 is turned off, the low noise amplifier is turned off, and the front-end chip operates in the emission mode; the seventh transistor M7 and the eighth transistor M8 are grounded in a conducting mode, so that the influence of the input impedance of the low-noise amplifier on the output impedance matching of the reconfigurable power amplifier is reduced; calculating initial values of a first inductor L1, a second inductor L2, a third inductor L3, a third capacitor C3 and a fourth capacitor C4 according to the output impedance of the power amplifier, and realizing output matching of the reconfigurable amplifier;
a second step of setting the first control voltage VC1, the first bias voltage VB1, and the second bias voltage VB2 to a high level, and setting the second control voltage VC2 and the third control voltage VC3 to a low level; at this time, the fifth transistor M5, the seventh transistor M7 and the eighth transistor M8 are turned off, the sixth transistor M6 is turned on, the reconfigurable power amplifier is configured in a switch mode, and the front-end chip works in a receiving mode; the reconfigurable power amplifier and the power supply switching circuit in the switch mode short circuit the first inductor L1 to the ground, so that the influence of the output impedance of the reconfigurable power amplifier on the input impedance matching of the low-noise amplifier is reduced; calculating initial values of a fourth inductor L4, a fifth inductor L5, a sixth inductor L6, a seventh transistor M7 closing capacitor and an eighth transistor M8 closing capacitor according to the input impedance of the low-noise amplifier and the initial values of the first inductor L1, the second inductor L2, the third inductor L3, the third capacitor C3 and the fourth capacitor C4 obtained in the first step, and realizing input matching of the low-noise amplifier;
and thirdly, optimizing the values of the first inductor L1, the second inductor L2, the third inductor L3, the fourth inductor L4, the fifth inductor L5, the sixth inductor L6, the third capacitor C3 and the fourth capacitor C4 and the sizes of the seventh transistor M7 and the eighth transistor M8 on the basis of the initial values obtained by the calculation in the first step and the second step by compromising the performance of the low-noise amplifier and the reconfigurable power amplifier, and realizing the collaborative design of the power amplifier, the low-noise amplifier and the switch in the ultra-wideband front-end chip.
Specifically, the important index of the low noise amplifier is a noise coefficient, and the index of the reconfigurable power amplifier is output power and efficiency. The compromise performance is the compromise of the noise coefficient, the output power and the efficiency, namely, on the premise of meeting the noise coefficient index, components are optimized, the loss is reduced, and the output power and the efficiency are improved.
The ultra-wideband front-end chip can achieve a larger bandwidth, a smaller matching loss and a higher linearity, and reference may be made to fig. 3, fig. 4 and fig. 5 in particular.
As shown in fig. 3, it is a graph of experimental results of the variation of gain, return loss and noise coefficient with frequency of the ultra-wideband front-end chip in the receiving mode according to the present embodiment; it can be seen that the Noise Figure (NF) is 4-5dB over the frequency range of 22-44 GHz; the small signal gain (S31) is 21.25dB, and the gain flatness is +/-1.25 dB; meanwhile, the return loss (S11) of the input/output port of the front-end chip is more than 10dB, and the return loss (S33) of the output end of the low-noise amplifier is more than 4.3dB.
As shown in fig. 4, it is an experimental result diagram of the variation of the gain and the return loss of the ultra-wideband front-end chip of this embodiment with the frequency in the transmission mode; it can be seen that in the frequency range of 22-44GHz, the small signal gain (S21) is 22.6dB, and the gain flatness is +/-0.6 dB; at the same time, the return loss (S22) at the input of the power amplifier is greater than 7.7dB.
Fig. 5 is a graph showing the experimental results of the variation of the saturated output power (Psat) and the output 1dB compression point (OP 1 dB) of the ultra-wideband end chip of this embodiment with the frequency in the transmission mode; it can be seen that the saturated output power is 17.0-18.9dBm and the output 1dB compression point is 15.0-17.8dBm in the frequency range of 22-44 GHz.
In summary, the ultra-wideband front-end chip of the present invention includes a reconfigurable power amplifier, a reconfigurable matching circuit and a low noise amplifier; the reconfigurable power amplifier, the reconfigurable matching circuit and the low noise amplifier are connected in sequence; the reconfigurable power amplifier can be configured to be in an amplifier mode or a switch mode; the reconfigurable matching circuit is used for realizing input matching of the low-noise amplifier, output matching of the reconfigurable power amplifier and switching of a receiving and transmitting mode. The invention designs the power amplifier, the low-noise amplifier and the switch in a coordinated way, reduces the use of a matching circuit and has the characteristics of large bandwidth, high linearity, good noise performance and small occupied area.
The above embodiments are preferred embodiments of the present invention, but the present invention is not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents thereof, and all such changes, modifications, substitutions, combinations, and simplifications are intended to be included in the scope of the present invention.
Claims (10)
1. An ultra-wideband front-end chip is characterized by comprising a reconfigurable power amplifier, a reconfigurable matching circuit and a low-noise amplifier:
the reconfigurable matching circuit comprises a reconfigurable power amplifier, a reconfigurable matching circuit, a low-noise amplifier, a reconfigurable power amplifier and a reconfigurable receiving-transmitting mode, wherein the reconfigurable matching circuit comprises a first end, a second end and a third end, wherein the first end of the reconfigurable matching circuit is an input/output end of the ultra-wideband front-end chip, the second end of the reconfigurable matching circuit is connected with the reconfigurable power amplifier, and the third end of the reconfigurable matching circuit is connected with the low-noise amplifier and is used for realizing input matching of the low-noise amplifier, output matching of the reconfigurable power amplifier and switching of the receiving-transmitting mode;
the configuration modes of the reconfigurable power amplifier comprise an amplifier mode and a switch mode;
when the configuration mode of the reconfigurable power amplifier is set to be an amplifier mode, the reconfigurable matching circuit is switched to be a transmitting mode, and the reconfigurable power amplifier amplifies an input signal at the input end of the reconfigurable matching circuit to obtain a first radio-frequency signal;
performing broadband impedance matching and power matching on the first radio-frequency signal through a reconfigurable matching circuit in a transmitting mode to obtain a second radio-frequency signal, and outputting the second radio-frequency signal from an input/output end of the ultra-wideband front-end chip;
when the configuration mode of the reconfigurable power amplifier is set to be a switch mode, the reconfigurable matching circuit is switched to a receiving mode;
an input signal of an input/output end of the ultra-wideband front-end chip is subjected to wideband impedance matching and noise matching through a reconfigurable matching circuit in a receiving mode to obtain a third radio frequency signal; the low-noise amplifier amplifies the third radio frequency signal to obtain a fourth radio frequency signal, and the fourth radio frequency signal is output from the output end of the low-noise amplifier.
2. The ultra-wideband front-end chip of claim 1, wherein the reconfigurable power amplifier comprises a pair of cascode transistors comprising a first transistor and a second transistor, a pair of common-gate transistors comprising a third transistor and a fourth transistor, a bias circuit, and a power switching circuit;
the drain electrode of the first transistor is connected with the source electrode of the third transistor, and the source electrode of the first transistor is grounded;
the drain electrode of the second transistor is connected with the source electrode of a fourth transistor, and the source electrode of the second transistor is grounded;
and the drain electrode of the third transistor and the drain electrode of the fourth transistor are output ends of the reconfigurable power amplifier.
3. The ultra-wideband front-end chip of claim 2, wherein the reconfigurable power amplifier further comprises a first capacitor and a second capacitor, a first end of the first capacitor is connected to the drain of the first transistor, and a second end of the first capacitor is connected to the gate of the second transistor; and the first end of the second capacitor is connected with the drain electrode of the second transistor, and the second end of the second capacitor is connected with the grid electrode of the first transistor.
4. The ultra-wideband front-end chip of claim 2, wherein the bias circuit comprises a first resistor, a second resistor, a first bias voltage, and a second bias voltage; a first end of the first resistor is connected with a first bias voltage, and a second end of the first resistor is connected with a grid electrode of the first transistor; a first end of the second resistor is connected with a first bias voltage, and a second end of the second resistor is connected with a grid electrode of the second transistor; the second bias voltage is connected to the gates of the third and fourth transistors, respectively.
5. The ultra-wideband front-end chip of claim 2, wherein the power switching circuit comprises a fifth transistor and a sixth transistor, wherein a source of the fifth transistor is connected to the power supply, a drain of the fifth transistor is connected to a drain of the sixth transistor, a gate of the fifth transistor is connected to a gate of the sixth transistor and to the first control voltage, and a source of the sixth transistor is connected to ground.
6. The ultra-wideband front-end chip of claim 4, wherein the reconfigurable power amplifier further comprises a driver stage amplifier, an output of the driver stage amplifier being connected to a gate of the first transistor and a gate of the second transistor.
7. The ultra-wideband front-end chip of any of claims 1 to 6, wherein the reconfigurable matching circuit comprises a first inductor, a second inductor, a third inductor, a fourth inductor, a fifth inductor, a sixth inductor, a seventh transistor, an eighth transistor, a third capacitor, a fourth capacitor, a third resistor, and a fourth resistor; the first inductor is connected with the output end of the reconfigurable power amplifier, and a tap of the first inductor is connected with the power supply switching circuit;
the first end of the second inductor is connected with the second end of the fourth inductor and the drain electrode of the seventh transistor respectively; the second end of the second inductor is respectively connected with the second end of the third inductor, the first end of the third capacitor and the first end of the fourth capacitor; the second end of the third capacitor is an input/output port of the ultra-wideband front-end chip; a second end of the fourth capacitor is grounded;
the first end of the third inductor is connected with the first end of the fifth inductor, the first end of the sixth inductor and the drain electrode of the eighth transistor respectively; the second end of the sixth inductor is connected with the input end of the low noise amplifier, and the first end of the fourth inductor is respectively connected with the second end of the fifth inductor and a third bias voltage, wherein the third bias voltage is the bias voltage of the input stage of the low noise amplifier;
the source electrode of the seventh transistor is grounded, the grid electrode of the seventh transistor is connected with the first end of a third resistor, and the second end of the third resistor is connected with a second control voltage;
the source of the eighth transistor is grounded, the gate of the eighth transistor is connected to the first end of the fourth resistor, and the second end of the fourth resistor is connected to a third control voltage.
8. The ultra-wideband front-end chip of claim 7, wherein there is coupling between the first inductor, the second inductor, and the third inductor; and the fourth inductor, the fifth inductor and the sixth inductor are coupled in pairs.
9. A control method based on the ultra-wideband front-end chip of any one of claims 1 to 8, comprising:
turning off the low noise amplifier, setting the first control voltage and the third bias voltage to be low level, and setting the second control voltage and the third control voltage to be high level; at the moment, the fifth transistor, the seventh transistor and the eighth transistor are switched on, the sixth transistor is switched off, the reconfigurable power amplifier is configured to be in an amplifier mode, the reconfigurable matching circuit is switched to be in a transmitting mode, and the front-end chip works in the transmitting mode;
the reconfigurable power amplifier amplifies an input signal thereof to obtain a first radio frequency signal; the reconfigurable matching circuit is used for carrying out broadband impedance matching and power matching on the first radio frequency signal to obtain a second radio frequency signal, and outputting the second radio frequency signal from the input/output end of the ultra-wideband front-end chip;
starting a low noise amplifier, setting a first control voltage, a first bias voltage and a second bias voltage as high levels, and setting a second control voltage and a third control voltage as low levels; at the moment, the fifth transistor, the seventh transistor and the eighth transistor are closed, the sixth transistor is turned on, the reconfigurable power amplifier is configured to be in a switch mode, the reconfigurable matching circuit is switched to be in a receiving mode, and the front-end chip works in the receiving mode;
an input signal of an input/output end of the ultra-wideband front-end chip is subjected to wideband impedance matching and noise matching through a reconfigurable matching circuit in a receiving mode to obtain a third radio frequency signal; and amplifying the third radio frequency signal through the low noise amplifier to obtain a fourth radio frequency signal, and outputting the fourth radio frequency signal from the output end of the low noise amplifier.
10. A co-design method implemented on the basis of the ultra-wideband front-end chip of any one of claims 1 to 8, comprising the steps of:
the first step is as follows: setting the first control voltage and the third bias voltage to a low level, and setting the second control voltage and the third control voltage to a high level; at the moment, the fifth transistor, the seventh transistor and the eighth transistor are switched on, the sixth transistor is switched off, the low-noise amplifier is switched off, and the front-end chip works in an emission mode; calculating initial values of a first inductor, a second inductor, a third capacitor and a fourth capacitor according to the output impedance of the reconfigurable power amplifier, and realizing output matching of the reconfigurable amplifier;
the second step is that: the first control voltage, the first bias voltage and the second bias voltage are set to a high level, and the second control voltage and the third control voltage are set to a low level; at the moment, the fifth transistor, the seventh transistor and the eighth transistor are closed, the sixth transistor is conducted, the reconfigurable power amplifier is configured to be in a switch mode, and the front-end chip works in a receiving mode; calculating initial values of a fourth inductor, a fifth inductor, a sixth inductor, a seventh transistor turn-off capacitor and an eighth transistor turn-off capacitor according to the input impedance of the low noise amplifier and the initial values of the first inductor, the second inductor, the third capacitor and the fourth capacitor obtained in the first step, and realizing input matching of the low noise amplifier;
the third step: on the premise of meeting the noise coefficient index, each component is optimized, and the ultra-wideband front-end chip is realized.
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| US20200106394A1 (en) * | 2018-09-28 | 2020-04-02 | Qualcomm Incorporated | Reconfigurable broadband and noise cancellation low noise amplifier (lna) with intra-carrier aggregation (ca) capability |
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