CN115148697A - Semiconductor package structure and manufacturing method thereof - Google Patents

Semiconductor package structure and manufacturing method thereof Download PDF

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Publication number
CN115148697A
CN115148697A CN202210229757.2A CN202210229757A CN115148697A CN 115148697 A CN115148697 A CN 115148697A CN 202210229757 A CN202210229757 A CN 202210229757A CN 115148697 A CN115148697 A CN 115148697A
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metal plating
carrier
packaging
semiconductor chip
semiconductor
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许飞
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Joulwatt Technology Co Ltd
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Joulwatt Technology Co Ltd
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Priority to CN202210229757.2A priority Critical patent/CN115148697A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
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    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering

Abstract

The invention discloses a semiconductor packaging structure and a manufacturing method thereof, wherein the packaging structure comprises: a semiconductor chip, a first surface of the semiconductor chip having at least one pad; at least one conductive post formed on at least one pad respectively; the packaging carrier is electrically connected with the semiconductor chip through at least one conductive column and the solder layer positioned at the top of each conductive column; the plastic packaging body is used for packaging the semiconductor chip, the at least one conductive column and the packaging carrier, wherein at least one metal plating point is selectively arranged on the surface of the packaging carrier facing the semiconductor chip; when the semiconductor chip is electrically connected with the packaging carrier, at least one conductive column is correspondingly connected with at least one metal plating point one by one through the solder layer positioned at the top of each conductive column. The invention can control the tin thinning phenomenon caused by the diffusion of the soldering flux when the chip is subjected to FC mounting and the problem of the interconnection of adjacent conductive columns of the chip, and is beneficial to improving the performance and the service life of the packaging structure.

Description

Semiconductor packaging structure and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging structure and a manufacturing method thereof.
Background
Semiconductor packages (or devices) are becoming smaller and more concentrated over time and are being manufactured in a wide variety of shapes. Semiconductor packages are typically classified into a WB (Wire Bonding) type or an FC (Flip Chip) Bonding type according to a connection method. Wire-bond type packages employ conductive bonding wires to effect bonding of the electrodes of a semiconductor chip (referred to herein simply as a chip) to a package frame, while flip-chip type packages employ conductive bumps disposed on electrode pads of the semiconductor chip to effect bonding of the chip circuitry to the package frame.
The flip chip bonding type package structure has a shorter electrical connection path and a higher density of interconnection requirements than the wire bonding type package structure, thereby providing excellent thermal and electrical characteristics and a smaller package structure size. A leadless package structure such as an LGA (Land Grid Array) package has no solder balls at the bottom and is reflowed by a solder paste applied to pads on a PCB (Printed Circuit Board) to complete the connection. The connection mode greatly shortens the interconnection distance and effectively improves the electrical performance of the semiconductor package.
At present, the FC process is used for power chips due to the requirements of large current and high heat dissipation, and in the substrate structure of the bare Cu + OSP (Organic solder resist, also called copper-protecting agent) adopted by the power chips, the surface of the copper layer is usually roughened by an acid etching roughening process to increase the bonding force between the copper layer and the green oil and between the substrate and the molding compound during subsequent molding, but the copper pillar has severe tin-climbing in the actual production process, which affects the electrical property and the service life. For example, when the subsequent FC chip mounting operation is performed, flux (Flux) on the surface of the copper pillar tin cap may cause excessive diffusion of Flux due to capillary action, and when reflow soldering is performed, the Flux diffuses outward, which causes:
1) After the chip is mounted, tin below the copper column is too thin, so that welding cracks are easily caused during application, and the electrical property of a device is failed.
2) The tin is diffused too much, so that two adjacent copper columns of the chip are electrically interconnected, and the electrical failure of the device is caused.
Therefore, there is a need to provide an improved technical solution to overcome the above technical problems in the prior art.
Disclosure of Invention
In order to solve the technical problems, the invention provides a semiconductor packaging structure and a manufacturing method thereof, which can control the tin thinning phenomenon caused by the diffusion of soldering flux when a chip is subjected to FC (chip on chip) mounting and the interconnection problem of adjacent conductive columns of the chip, and are beneficial to improving the performance and prolonging the service life of the packaging structure.
According to a first aspect of the present disclosure, there is provided a semiconductor package structure comprising: a semiconductor chip having at least one pad on a first surface thereof;
the at least one conductive column is respectively formed on the at least one bonding pad, and a solder layer is arranged at the top of each conductive column in the at least one conductive column;
the packaging carrier is electrically connected with the semiconductor chip through the at least one conductive column and the solder layer positioned at the top of each conductive column;
a plastic package body for packaging the semiconductor chip, the at least one conductive pillar and the package carrier,
the surface of the packaging carrier facing the semiconductor chip is selectively provided with at least one metal plating point, and when the semiconductor chip is electrically connected with the packaging carrier, the at least one conductive column is correspondingly connected with the at least one metal plating point one by one through the solder layer positioned at the top of each conductive column.
Optionally, a roughness of a surface of the at least one metal plating point is less than a roughness of a surface of the package carrier.
Optionally, the at least one metal plating point is configured to be formed on the package carrier by means of electroless plating.
Optionally, when the at least one conductive pillar is correspondingly connected with the at least one metal plating point, each metal plating point of the at least one metal plating point is located directly below the corresponding conductive pillar.
Optionally, the package carrier includes a copper layer and a substrate, and the at least one metal plating point is configured to be formed on the surface of the copper layer by electroless plating.
Optionally, the surface of the copper layer has a microstructure formed after roughening treatment.
Optionally, the material forming each of the at least one metal plating point includes at least one of copper, silver, nickel, palladium, and gold.
Optionally, a cross-sectional dimension of each of the at least one metal plating point is greater than a cross-sectional dimension of the corresponding conductive pillar.
Optionally, any two metal plating points of the at least one metal plating point are spaced apart from each other by a predetermined distance.
Optionally, the package carrier comprises any one of a lead frame and a package substrate.
According to a second aspect of the present disclosure, there is provided a method of manufacturing a semiconductor package structure, including: providing a packaging carrier;
selectively arranging at least one metal plating point on the upper surface of the packaging carrier;
placing a semiconductor chip on the upper surface of the packaging carrier, and connecting at least one conductive column on the conductor chip with the at least one metal plating point in a one-to-one correspondence manner so as to realize the electrical connection between the semiconductor chip and the packaging carrier;
and packaging the packaging carrier and the semiconductor chip to form a packaging structure.
Optionally, a roughness of a surface of the at least one metal plating dot is less than a roughness of a surface of the package carrier.
Optionally, the selectively disposing at least one metal plating point on the upper surface of the package carrier includes:
forming at least one metal plating point corresponding to the at least one conductive post on the surface of the copper layer in the package carrier by adopting an electroless plating mode,
wherein, when each metal plating point is formed, the method comprises the following steps: and forming a silver layer on the upper surface of the packaging carrier in a chemical plating mode or sequentially forming a nickel layer, a palladium layer and a gold layer.
Optionally, the manufacturing method further comprises: and roughening the surface of the copper layer in the packaging carrier.
The beneficial effects of the invention at least comprise:
according to the embodiment of the invention, the at least one metal plating point is selectively arranged on the packaging carrier, so that when the semiconductor chip is in flip connection with the semiconductor chip, the at least one conductive column on the semiconductor chip can be only in corresponding connection with the at least one metal plating point, and the surface roughness of the metal plating point is smaller than that of the packaging carrier, so that the problems of thin soldering tin between the conductive column and the packaging carrier and interconnection of adjacent conductive columns caused by excessive diffusion of soldering flux during FC chip mounting of the semiconductor chip can be controlled, and the performance and the service life of a semiconductor packaging structure (also called as a semiconductor device or a device) can be improved.
In a further preferred embodiment, the surface of the copper layer in the package carrier is roughened, so that the bonding force between the copper layer and green oil and between the package carrier and a plastic package material during subsequent molding (compression molding) is ensured, and the risk of device failure caused by delamination is reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
Fig. 1 is a schematic structural diagram of a semiconductor package structure according to an embodiment of the present invention;
fig. 2 is a flow chart illustrating a method for manufacturing a semiconductor package structure according to an embodiment of the present invention.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
As shown in fig. 1, the semiconductor package structure disclosed in the present invention includes: a semiconductor chip 1, a first surface of the semiconductor chip 1 having at least one pad 7; at least one conductive column 2 respectively formed on at least one bonding pad 7, and a solder layer 4 is arranged on the top of each conductive column 2; a package carrier 6, wherein the package carrier 6 (for example, any one of a lead frame and a package substrate) is used for carrying the semiconductor chip 1 and is electrically connected with the semiconductor chip 1 through at least one conductive pillar 2 and a solder layer 4 on top of each conductive pillar 2; the plastic package body 3 is formed by solidifying a plastic package material in a molten state and is used for packaging the semiconductor chip 1, the at least one conductive column 2 and the packaging carrier 6.
In the present invention, the semiconductor chip (chip for short) 1 is a general name, and the internal structure of the semiconductor chip 1 is not illustrated in the drawings for simplifying the drawings and highlighting the invention point, but the internal structure of the semiconductor chip 1 can be understood according to the prior art. For example, a semiconductor device, a rewiring layer, and the like are formed in the semiconductor chip 1, and the semiconductor device and the at least one pad 7 may be located on the same side surface of the chip 1 or may be located on different side surfaces of the chip 1. When the semiconductor device and the at least one pad 7 are located on different side surfaces of the chip 1, the at least one pad 7 may be electrically connected to the semiconductor device using a through-chip via. In this embodiment, the semiconductor device and the at least one bonding pad 7 are located on the first surface of the chip 1, and the semiconductor device is electrically connected to the at least one bonding pad 7, and the at least one bonding pad 7 is used to electrically connect the circuit structure in the chip with the corresponding pin on the package carrier 6 and the external circuit.
In the present embodiment, the surface of the semiconductor chip 1 facing the package carrier 6 may be defined as a first surface thereof.
At least one conductive pillar 2 may be formed on at least one pad 7 by, for example, an electroplating method, and the at least one conductive pillar 2 corresponds to the at least one pad 7 one by one, that is, a corresponding conductive pillar 2 is formed on each pad 7 of the at least one pad 7. The material of at least one pad 7 is aluminum, copper, gold, silver or the like. At least one conductive post 2 comprises a conductive material such as a metal. In some embodiments, at least one conductive pillar 2 comprises Cu. In other embodiments, the conductive post 2 comprises, for example, a copper alloy; a combination of Cu, ni, and solder; a combination of Cu and solder; and/or combinations thereof. In a cross-sectional view, the conductive post 2 may have a cylindrical shape, a tapered shape, a stepped shape, a plug shape, an "I" letter shape, or a "T" letter shape. Alternatively, the conductive pillars 2 may also contain other conductive materials and/or metals and the conductive pillars 2 may have other shapes.
Alternatively, the solder layer 4 on top of each conductive post 2 may be a tin layer or a tailored metal layer. Further, in the embodiment of the present invention, a layer of flux may be disposed on the surface of the solder layer 4, and then reflow soldering may be performed, so that the semiconductor chip 1 and the package carrier 6 are firmly bonded together. It can be understood that the main function of the flux is to remove the oxide on the surface of the solder or the welded parent metal, so that the metal can reach the necessary cleanness, and the surface of the solder is oxidized again when the solder is placed for welding, so that the surface tension of the solder is reduced, and the welding performance is improved. Wherein, the scaling powder can volatilize after the welding is accomplished.
Further, the package structure in the embodiment of the present invention further includes an insulating layer (not shown) formed on the first surface of the chip 1, and the insulating layer may be formed by depositing an oxide material, such as silicon oxide, on the first surface of the semiconductor chip 1. In a possible embodiment of the invention, at least one pad 7 is also provided on the first surface of chip 1, which at least one pad 7 is directly connected to the semiconductor device in chip 1 and is exposed through an opening etched in the insulating layer. In another possible embodiment of the present invention, at least one pad 7 is disposed on a surface of the insulating layer away from the chip 1, that is, the insulating layer is formed between the semiconductor chip 1 and the at least one pad 7, and the at least one pad 7 is connected to the semiconductor device in the chip 1 through at least one via hole on the insulating layer. Optionally, the insulating layer is a stacked structure of one or more layers of a silicon oxide layer, a silicon nitride layer, a polyimide resin layer, and a benzoxazine resin layer, and is used for protecting the chip 1.
Further, the package structure in the embodiment of the present invention further includes a plating seed layer (not shown) formed on the surface of the at least one pad 7. Preferably, an Under Bump Metallurgy (UBM) is formed on the surface of at least one pad 7 away from the chip 1 to serve as a plating seed layer in this embodiment.
In this embodiment, the at least one pad 7 and the under bump metallurgy (not shown) on the surface of the at least one pad 7 constitute a metal interconnection layer, and the at least one conductive pillar 2 is subsequently formed on the under bump metallurgy layer. The under bump metallurgy is a metallization transition layer between the chip pad 7 and the conductive pillar 2, and mainly functions as an adhesion and diffusion barrier.
Further, the flip chip package structure in the embodiment of the invention further includes a passivation layer (not shown) formed on a surface of the insulating layer away from the semiconductor chip 1, and a portion of each pad 7 may be covered by the passivation layer, so that an exposed area of each pad 7 is reduced, and a size of the conductive pillar 2 formed subsequently is reduced, which facilitates formation of a high-density package structure.
At least one metal plating point 5 is selectively disposed on the surface of the package carrier 6 facing the semiconductor chip 1, for example, by chemical plating, so that when the semiconductor chip 1 is electrically connected to the package carrier 6, at least one conductive pillar 2 on the semiconductor chip 1 is connected to the at least one metal plating point 5 in a one-to-one correspondence manner through the solder layer 4 on the top of each conductive pillar 2.
Specifically, the package carrier 6 includes a substrate 63, and a copper layer 61 and a green oil 62 disposed on an upper surface of the substrate 63. The surface of the copper layer 61 has a microstructure formed after roughening treatment, which can increase the bonding force between the copper layer 61 and the green oil 62, and the bonding force between the package carrier 6 and the molding compound in subsequent packaging.
In the present embodiment, the at least one metal plating point 5 is specifically configured to be selectively disposed on the upper surface of the copper layer 61 by means of electroless plating. The surface of at least one metal plating point 5 is not roughened, so that the roughness of the surface of at least one metal plating point 5 is less than that of the surface of the copper layer 61, that is, less than that of the surface of the package carrier 6, so that when the semiconductor chip 1 is subjected to FC chip mounting, the diffusion degree of the soldering flux on the metal plating point 5 is lower than that of the soldering flux on the package carrier 6, and the wettability between the soldering flux and the metal plating point 5 is relatively poor, thereby well preventing the problems of thin soldering tin between the conductive posts 2 and the package carrier 6 and interconnection of adjacent conductive posts caused by excessive diffusion of the soldering flux, and being beneficial to improving the performance and the service life of the semiconductor package structure.
Alternatively, the copper layer 61 on the package carrier 6 may be connected to the lower surface of the package carrier 6 through respective conductive pillars or conductive vias, and form corresponding outer leads on the lower surface of the package carrier 6. And the outer leads may be formed into different forms according to different package structures, such as BGA (Ball Grid Array) packages, LGA packages, QFN (Quad Flat No-lead package) packages, and so on. And further, the outer pins may be formed with metal balls or square metal blocks.
In the present embodiment, the surface of the package carrier 6 facing the semiconductor chip 1 may be defined as its upper surface, and the surface of the copper layer 61 facing the semiconductor chip 1 may be defined as its upper surface.
In this embodiment, the selective arrangement of the at least one metal plating dot 5 on the package carrier 6 means that the metal plating dot 5 is only arranged on the package carrier 6 at a position corresponding to the connection with the at least one conductive pillar 2, and the metal plating dot 5 is not arranged at other positions on the package carrier 6, so that not only is the surface of the package carrier 6 ensured to have enough roughness to ensure the bonding force between the copper layer and the green oil and between the package carrier 6 and the molding compound 3 during subsequent molding, and the risk of device failure caused by delamination reduced, but also the problems of thinner solder between the conductive pillars 2 and the package carrier 6 and interconnection of adjacent conductive pillars 2 caused by excessive diffusion of the flux on the surface of the package carrier 6 can be prevented. Wherein, when the at least one conductive pillar 2 is correspondingly connected to the at least one metal plating point 5, each metal plating point of the at least one metal plating point 5 is located below the corresponding conductive pillar 2, and in a further preferred embodiment, each metal plating point of the at least one metal plating point 5 can be further configured to be located directly below the corresponding conductive pillar 2.
Furthermore, the invention also forms OSP on the upper surface of the packaging carrier 6, which is simply to chemically grow an organic coating on the clean bare copper surface, wherein the organic coating has the functions of oxidation resistance, thermal shock resistance and moisture resistance, and is used for protecting the surface of the copper layer 61 from being oxidized or vulcanized in the normal environment. However, at subsequent high soldering temperatures, the protective film must be easily and quickly removed by the flux, so that the exposed clean copper surface immediately bonds with the molten solder in a very short time to form a strong solder joint.
It should be noted that in the embodiment disclosed in fig. 1, only the multi-layer metal plating structure of the nickel layer 53 plus the palladium layer 52 plus the gold layer 51 is shown, but it is understood that in other embodiments of the present invention, each metal plating point of the at least one metal plating point 5 may also be provided as a multi-layer structure of a nickel layer plus a gold layer, or a single-layer structure including at least one of silver, copper and gold, or a single-layer or multi-layer structure formed by other single-metal materials or alloy materials capable of forming solder joints with tin, which is not limited by the present invention.
Further, in order to ensure reliable connection between the solder layer 4 and the metal plating points, in the embodiment of the present invention, the cross-sectional dimension of each metal plating point in the at least one metal plating point 5 is also set to be larger than the cross-sectional dimension of the corresponding conductive pillar 2. Meanwhile, any two metal plating points of the at least one metal plating point 5 on the package carrier 6 are formed to be spaced from each other by a predetermined distance, so as to avoid interconnection of the at least one conductive pillar 2 when solder overflows the metal plating points.
Further, the invention also discloses a manufacturing method of the semiconductor packaging structure, and the manufacturing method can be used for forming the semiconductor packaging structure shown in the figure 1. As shown in fig. 2, the manufacturing method includes performing the steps of:
in step S1, a package carrier is provided.
In this embodiment, the package carrier at least includes a substrate 63, and a copper layer 61 and a green oil 62 disposed on an upper surface of the substrate 63. Optionally, the package carrier further comprises an OSP film chemically grown on the surface of the copper layer 61.
Further, the manufacturing method further includes roughening the surface of the copper layer 6 to increase the bonding force between the copper layer 61 and the green oil 62, and the subsequent encapsulation is the bonding force between the encapsulation carrier 6 and the molding compound.
In step S2, at least one metal plating point is selectively disposed on the upper surface of the package carrier.
In this embodiment, step S2 further includes: and forming at least one metal plating point corresponding to the at least one conductive column on the surface of the copper layer in the packaging carrier by adopting an electroless plating mode. Further, the roughness of the surface of the at least one metal plating point is less than the roughness of the surface of the package carrier.
Illustratively, the forming of each metal plating point includes: at least one of silver, copper and gold or other single metal materials or alloy materials capable of forming welding spots with tin are adopted to carry out chemical plating on the upper surface of the packaging carrier to form a single-layer metal plating spot structure, or a chemical plating mode is adopted to sequentially form a multi-layer metal plating spot structure of a nickel layer, a palladium layer and a gold layer. As long as the formed metal plating point structure can form a solder joint with tin, and the surface roughness is less than the surface roughness of the packaging carrier.
In step S3, the semiconductor chip is placed on the upper surface of the package carrier, and the at least one conductive pillar on the conductor chip is connected to the at least one metal plating point in a one-to-one correspondence manner, so as to electrically connect the semiconductor chip and the package carrier.
In this embodiment, the semiconductor chip is disposed on the upper surface of the package carrier in an FC flip-chip manner, and when the semiconductor chip is disposed on the upper surface of the package carrier, the at least one conductive pillar on the first surface of the semiconductor chip can be located right above the at least one metal plating point on the package carrier, and at this time, the at least one conductive pillar and the at least one metal plating point can be bonded together in a one-to-one and firm manner by reflow soldering, so that the semiconductor chip and the package carrier are electrically connected.
In step S4, the package carrier and the semiconductor chip are packaged to form a package structure.
In this embodiment, the semiconductor chip on the package carrier may be packaged by the plastic package mold. And optionally, a material having an insulating property and a strong bonding force, such as epoxy resin, may be used in the packaging process.
In summary, the embodiment of the invention selectively sets at least one metal plating point on the package carrier, so that when the semiconductor chip is in flip-chip connection with the semiconductor chip, at least one conductive pillar on the semiconductor chip can be only in corresponding connection with the at least one metal plating point, and because the surface roughness of the metal plating point is smaller than that of the package carrier, the problems of thinner solder between the conductive pillar and the package carrier and interconnection of adjacent conductive pillars caused by excessive diffusion of the soldering flux when the semiconductor chip is in FC die bonding can be controlled, which is beneficial to improving the performance and service life of the semiconductor package structure (also referred to as a semiconductor device or a device).
In a further preferred embodiment, the surface of the copper layer in the packaging carrier is roughened, so that the bonding force between the copper layer and green oil and the bonding force between the packaging carrier and a plastic package material during subsequent molding are ensured, and the risk of device failure caused by delamination is reduced.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.

Claims (14)

1. A semiconductor package structure, comprising:
a semiconductor chip having at least one pad on a first surface thereof;
the at least one conductive column is respectively formed on the at least one bonding pad, and a solder layer is arranged at the top of each conductive column in the at least one conductive column;
the packaging carrier is electrically connected with the semiconductor chip through the at least one conductive column and the solder layer positioned at the top of each conductive column;
a plastic package body for packaging the semiconductor chip, the at least one conductive pillar and the package carrier,
the surface of the packaging carrier facing the semiconductor chip is selectively provided with at least one metal plating point, and when the semiconductor chip is electrically connected with the packaging carrier, the at least one conductive column is correspondingly connected with the at least one metal plating point one by one through the solder layer positioned at the top of each conductive column.
2. The semiconductor package structure of claim 1, wherein a roughness of a surface of the at least one metal plating point is less than a roughness of a surface of the package carrier.
3. The semiconductor package structure of claim 1, wherein the at least one metal plating is configured to be formed on the package carrier by electroless plating.
4. The semiconductor package structure of claim 1, wherein when the at least one conductive pillar is in corresponding connection with the at least one metal plating point, each of the at least one metal plating point is located directly below the corresponding conductive pillar.
5. The semiconductor package structure of claim 3, wherein the package carrier comprises a copper layer and a base, and the at least one metal plating point is configured to be formed on the surface of the copper layer by electroless plating.
6. The semiconductor package structure of claim 5, wherein the surface of the copper layer has a microstructure formed thereon by roughening treatment.
7. The semiconductor package structure of claim 1, wherein a material forming each of the at least one metal plating comprises at least one of copper, silver, nickel, palladium, and gold.
8. The semiconductor package structure of claim 1, wherein a cross-sectional dimension of each of the at least one metal plating is greater than a cross-sectional dimension of the corresponding conductive pillar.
9. The semiconductor package structure of claim 8, wherein any two metal plating points of the at least one metal plating point are spaced apart from each other by a predetermined distance.
10. The semiconductor package structure of claim 1, wherein the package carrier comprises any one of a leadframe and a package substrate.
11. A method for manufacturing a semiconductor packaging structure comprises the following steps:
providing a packaging carrier;
selectively arranging at least one metal plating point on the upper surface of the packaging carrier;
placing a semiconductor chip on the upper surface of the packaging carrier, and connecting at least one conductive column on the conductor chip with the at least one metal plating point in a one-to-one correspondence manner so as to realize the electrical connection between the semiconductor chip and the packaging carrier;
and packaging the packaging carrier and the semiconductor chip to form a packaging structure.
12. The manufacturing method according to claim 11, wherein a roughness of a surface of the at least one metal plating point is smaller than a roughness of a surface of the package carrier.
13. The method of manufacturing of claim 11, wherein selectively disposing at least one metal plating on the top surface of the package carrier comprises:
forming at least one metal plating point corresponding to the at least one conductive post on the surface of the copper layer in the package carrier by adopting an electroless plating mode,
wherein, when each metal plating point is formed, the method comprises the following steps: and forming a silver layer on the upper surface of the packaging carrier in a chemical plating mode or sequentially forming a nickel layer, a palladium layer and a gold layer.
14. The manufacturing method according to claim 13, wherein the manufacturing method further comprises: and roughening the surface of the copper layer in the packaging carrier.
CN202210229757.2A 2022-03-10 2022-03-10 Semiconductor package structure and manufacturing method thereof Pending CN115148697A (en)

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Application Number Priority Date Filing Date Title
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