CN115118294B - Digital isolator based on self-adaptive frequency control - Google Patents
Digital isolator based on self-adaptive frequency control Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
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- H03M1/822—Digital/analogue converters with intermediate conversion to time interval using pulse width modulation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04B14/00—Transmission systems not characterised by the medium used for transmission
- H04B14/02—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
- H04B14/026—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation using pulse time characteristics modulation, e.g. width, position, interval
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
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Abstract
The present disclosure provides a digital isolator based on adaptive frequency control, comprising: the device comprises a transmitting end circuit, an isolating gate and a receiving end circuit. The transmitting end circuit is used for generating corresponding pulse modulation signals with different frequencies according to different pulse widths of the input digital pulse signals; the isolation gate is used as an isolation medium and connected between the transmitting end circuit and the receiving end circuit and transmits pulse modulation signals; the receiving end circuit is used for demodulating and recovering the pulse modulation signal. The transmitting-end circuit includes: an oscillator, an adaptive frequency controller. The oscillator is used for converting an input digital pulse signal into an oscillation output signal; and the self-adaptive frequency controller is used for receiving the digital pulse signals for sampling detection, outputting control signals to the oscillator according to different pulse widths of the digital pulse signals and controlling the oscillation frequency of the oscillator in real time, so that the frequency of the oscillation output signals is controlled and the energy consumption of the oscillator is reduced.
Description
Technical Field
The present disclosure relates to the field of electronics and integrated circuit technology, and in particular, to a digital isolator based on adaptive frequency control.
Background
With the advance of new energy industry, communication industry and industry age 4.0, the system requires that the digital isolator can provide a certain degree of electrical isolation by utilizing the miniature isolation grating and has the capability of processing higher-speed data with lower power consumption, so that the digital isolator is driven to develop towards a high-speed and low-power consumption direction, and the performance is improved at the same time, which is a main challenge faced by the digital isolator chip.
In order to realize the transmission of digital signals across the isolation gate, the digital signals need to be modulated and demodulated, and common modulation and demodulation architectures mainly include a set/reset method, a pulse edge method and an On-off Keying (OOK) method. The set/reset method requires two independent signal modulation paths, which means that the circuit area and power consumption of the transmitting end are doubled. The pulse edge method is to modulate the rising edge and the falling edge of the transmitted digital signal to obtain an edge modulation signal, wherein the pulse edge method is more common in two modes of pulse counting and pulse polarity, the rising edge and the falling edge are distinguished by different pulse numbers, a transmitting end and a receiving end are required to be provided with a plurality of analog and digital circuit modules such as a counter, a zero crossing detection circuit and the like, and the complexity and the power consumption of the system are increased; the latter uses positive and negative pulses to represent rising and falling edges respectively, and requires that the receiving end must have a pulse polarity discriminating circuit, which requires a certain complexity and power consumption, and the positive and negative pulses are easily disturbed by the environment.
The OOK-based digital isolator is a scheme with lower circuit complexity in three modes, only an input digital signal is used for modulating a high-frequency oscillating signal, envelope information of the high-frequency oscillating signal is digital signal information, only envelope detection is needed at a receiving end, and power consumption and circuit area are relatively small. However, in order to be able to transmit digital signals at a high rate, the OOK method requires the use of an oscillator at the transmitting end, which operates in a high frequency state, typically at an oscillation frequency up to GHz, where there is a large power loss of the oscillator. When transmitting low-rate input digital signals, the fixed high-frequency oscillation causes unnecessary power waste at the transmitting end for modulating the low-rate digital signals. Thus, it is a challenge to obtain low power consumption and high rate data transmission in OOK architecture with low circuit complexity and high signal reliability.
Disclosure of Invention
From the above, the digital isolator adopting the OOK architecture in the prior art can reduce the error rate, and in order to achieve both high data rate and low data rate, the oscillator is required to output a fixed high-frequency oscillation signal, which causes unnecessary power consumption at low rate; the transmitting end of the digital isolator of the existing architecture is not controlled when the input digital signal is low, the oscillator still oscillates at high frequency, and additional power consumption exists. Based on the above problems, the present disclosure provides a digital isolator based on adaptive frequency control to alleviate the above technical problems in the prior art.
Technical scheme (one)
The present disclosure provides a digital isolator based on adaptive frequency control, comprising: transmitting end circuit, barrier gate, and receiving end circuit, wherein: the transmitting end circuit is used for generating corresponding pulse modulation signals with different frequencies according to the difference of pulse widths of the input digital pulse signals; the isolation grid is connected between the transmitting end circuit and the receiving end circuit as an isolation medium and used for transmitting the pulse modulation signal; and the receiving end circuit is used for demodulating and recovering the pulse modulation signal.
According to an embodiment of the present disclosure, the transmitting-side circuit includes: an oscillator, an adaptive frequency controller. The oscillator is used for converting an input digital pulse signal into an oscillation output signal; and the self-adaptive frequency controller is used for receiving the digital pulse signals for sampling detection, outputting control signals to the oscillator according to different pulse widths of the digital pulse signals, and controlling the oscillation frequency of the oscillator in real time so as to control the frequency of an oscillation output signal.
According to the embodiment of the disclosure, when the adaptive frequency controller detects that the digital pulse signal is at a high level, the oscillation frequency of the oscillator is gradually reduced by the control signal, so that the energy consumption of the oscillator is reduced.
According to an embodiment of the present disclosure, the adaptive frequency controller includes: time-voltage converter, voltage-current converter. The time-voltage converter is used for converting an input digital pulse signal into a voltage signal; a voltage-to-current converter coupled to the time-to-voltage converter for receiving and converting the voltage signal to a current signal; the self-adaptive frequency controller obtains a real-time control signal according to the change of the voltage signal and the current signal and outputs the control signal to the oscillator.
According to the embodiment of the disclosure, the voltage signal gradually decreases along with the increase of the pulse width of the input digital pulse signal, and then the current value of the current signal gradually decreases, so that the control signal controls the oscillator to correspondingly gradually decrease the oscillation frequency.
According to an embodiment of the disclosure, the transmitting-side circuit further includes an oscillator control switch, and when the digital pulse signal is at a low level, the oscillator control switch is turned off, and the oscillator stops working.
According to an embodiment of the disclosure, the control signal is a voltage signal or a current signal.
According to an embodiment of the disclosure, the oscillating output signal is a differential signal or a single-ended signal.
According to an embodiment of the present disclosure, the oscillator is a pseudo-differential ring oscillator.
According to an embodiment of the disclosure, the time-voltage converter includes an error amplifier, a PMOS pull-up tube, and a load capacitor; the time-voltage converter inputs a digital pulse signal and a reference voltage and outputs a voltage signal; the voltage-current converter comprises two parallel common source amplifiers with source negative feedback and corresponding current mirrors; the digital pulse signal is connected to the negative end of the error amplifier, the reference voltage is connected to the positive end of the error amplifier, the output of the error amplifier is connected with the load capacitor and the drain electrode of the PMOS pull-up tube, and the negative end of the error amplifier is also connected with the grid electrode of the PMOS pull-up tube; when the voltage value of the digital pulse signal is a high level larger than the reference voltage, the PMOS pull-up tube is cut off, and the voltage value of the voltage signal is slowly reduced; when the voltage value of the digital pulse signal is at a low level smaller than the reference voltage, the PMOS pull-up tube is opened, and the voltage value of the voltage signal is pulled up to the power supply voltage, so that the frequency of the oscillator is always reduced from the highest frequency in the adjusting process.
(II) advantageous effects
As can be seen from the above technical solutions, the digital isolator based on adaptive frequency control of the present disclosure has at least one or a part of the following advantages:
(1) While maintaining the high data rate transmission capability, properly reducing the frequency of the oscillator when the pulse width of the input signal becomes large, and reducing unnecessary power consumption of a transmitting end;
(2) When the input signal is in a low level, the oscillator is turned off in time, so that the power consumption of the oscillator at the moment is canceled, and the total system loss of the transmitting end is further reduced;
(3) The performance of the digital isolator under the OOK modem architecture is improved.
Drawings
Fig. 1 is a block diagram of a prior art pulse counting based digital isolator system.
Fig. 2 is a block diagram of a prior art digital isolator system based on the pulse polarity method.
Fig. 3 is a block diagram of a prior art OOK-based digital isolator system.
Fig. 4 is a schematic diagram of a digital isolator composition based on adaptive frequency control in an embodiment of the present disclosure.
Fig. 5 is a schematic diagram of an adaptive frequency controller according to an embodiment of the present disclosure. ;
fig. 6 is a schematic diagram of waveforms of different signals in a transmitting-side circuit according to an embodiment of the disclosure.
Fig. 7 is a schematic diagram of a time-voltage and voltage-current module circuit according to an embodiment of the present disclosure.
Fig. 8 is a circuit schematic of a current-limited pseudo-differential ring oscillator according to an embodiment of the present disclosure.
[ In the drawings, the main reference numerals of the embodiments of the present disclosure ]
100-Transmitting end circuit;
101-an adaptive frequency controller;
1011-time-voltage converter;
1012-a voltage-to-current converter;
102-an oscillator;
103-a driver;
104-controlling a switch;
200-isolating grids;
300-receiver circuit.
Detailed Description
Aiming at the power consumption problem of the digital isolator of an OOK modulation and demodulation architecture, the frequency of the oscillator is adaptively adjusted by detecting the pulse width of an input digital signal, so that the oscillator works in a high-frequency state at a high speed, works in a low-frequency state at a low speed, and reduces the power consumption of the isolator at the low speed under the condition of supporting the highest data rate; the on and off operation of the oscillator is realized by the input digital signal, so that the oscillator is completely turned off when the input digital signal is at a low level, and the power consumption of the oscillator at the moment is eliminated. Thereby realizing reduction of power consumption of the transmitting-side oscillator while securing the capability of high data rate transmission.
The prior art digital isolator shown in fig. 1 mainly comprises two chips, namely a transmitting end chip and a receiving end chip, and signals are transmitted between the transmitting end chip and the receiving end chip through an isolating grid. The transmitting end modulates the input digital signal to a high frequency band, which is beneficial to reducing the area of the isolation grating, and the receiving end adopts a demodulation mode matched with the transmitting end. The scheme uses an edge detection circuit to modulate the rising edge of an input signal into two continuous high frequency pulses (SET_HI) with a pulse width of 1ns, modulates the falling edge of the input signal into one high frequency pulse (SET_LO) with a pulse width of 1ns, and uses a transformer as an isolation gate for communication. When no input edge signal is in 1 mu s (always high or always low), a1 mu s monostable trigger edge pulse generating circuit is utilized to realize a refreshing mechanism so as to ensure the correctness of the direct current potential, and a receiving end uses the Watchdog to judge whether the output is in a safe fault state or not. The receiving end uses a non-retriggerable monostable edge trigger to generate the detection signal. When two pulses are detected, the OUTPUT (OUTPUT) is pulled high; when a pulse is detected, the output is pulled low. The implementation method of the mode is complex, more digital modules are needed for control, misjudgment is easy to be caused during signal transmission and judgment, and the maximum data rate which can be transmitted is limited by the edge pulse. If more pulses are used, more power consumption is required, for example 7 pulses are used to represent rising edges and 5 pulses are used to represent falling edges, which helps to improve demodulation accuracy, but more complex circuitry and higher power consumption are also required.
The prior art digital isolator based on the pulse polarity method as shown in fig. 2, which detects the rising edge and the falling edge of the input signal and generates a corresponding single pulse signal to control the current limited inverter and the push-pull stage circuit connected to the transformer, respectively. When a rising edge is detected, a positive current pulse signal is correspondingly generated on the transformer, and when a rising edge is detected, a negative current pulse signal is correspondingly generated on the transformer. The two obtained positive and negative pulses are subjected to certain filtering at the receiving end and then are divided into two independent signals for processing, and the original signals are recovered by using an amplifier and a hysteresis comparator. This approach is prone to decoding errors at the receiving end due to the presence of negative pulses and requires more power consumption for the high frequency drive signal of the transformer at high rates.
In the prior art OOK-based digital isolator system shown in fig. 3, when an input digital signal is at a high level, a high-frequency carrier is transmitted to a back end, when the input digital signal is at a low level, a low level is output, and at a transmitting end, a logical and gate and a spread spectrum oscillator are used to implement a signal multiplication operation, and an envelope of a synthesized output signal is a high-frequency modulation signal. The modulating signal is converted into a differential signal by using an inverter and a driver, and is transmitted to a receiving end through an isolation gate. The receiving end amplifies and envelope detects the attenuated signal to recover the original signal. Compared with the former two modes, the OOK scheme has simple circuit implementation mode and relatively high demodulation accuracy of the receiving end. However, this scheme has a problem in that in order to satisfy high data rate transmission, the oscillator operates in a fixed high frequency state, and power consumption is large; the oscillator operating state is unchanged when at low data rate transmission, however, a high frequency oscillator output is not required at low data rates, thus causing unnecessary power consumption. In addition, when the input signal is at a low level, the oscillator is still in a high frequency oscillation state, and the transmitting terminal output is at a low level, and the power consumption of the oscillator is wasted.
In summary, from the circuit design perspective, improving the data rate of the digital isolator and reducing the power consumption can greatly improve the performance of the digital isolator and expand the application field of the digital isolator, and a great contradiction exists between improving the data rate and reducing the power consumption, so that the disclosure provides a better digital isolator to optimize the two performances.
For the purposes of promoting an understanding of the principles and advantages of the disclosure, reference will now be made to the embodiments illustrated in the drawings and specific language will be used to describe the same.
In an embodiment of the present disclosure, there is provided a digital isolator based on adaptive frequency control, as shown in fig. 4, including: a transmitting-side circuit 100, an isolation gate 200, and a receiving-side circuit 300;
wherein: the transmitting end circuit 100 is configured to generate corresponding pulse modulation signals with different frequencies according to the difference of pulse widths of the input digital pulse signal V IN;
an isolation gate 200 as an isolation medium connected between the transmitting-side circuit and the receiving-side circuit 300 and transmitting the pulse modulation signal;
The receiving-end circuit 300 is configured to demodulate and recover the pulse modulated signal.
According to the present disclosure, the transmitting-side circuit 100 includes:
An oscillator 102 for converting an input digital pulse signal V IN into an oscillation output signal; and
The adaptive frequency controller 101 receives the digital pulse signal for sampling detection, and outputs a control signal to the oscillator according to the different pulse widths of the digital pulse signal V IN, and controls the oscillation frequency of the oscillator in real time, thereby controlling the frequency of the oscillation output signal.
The composition and function of each circuit will be described in detail below with reference to fig. 4 to 6:
The transmitting-end circuit 100 needs to modulate the input low-frequency digital pulse signal V IN to a high-frequency pulse modulation signal, so that the high-frequency pulse modulation signal is conveniently transmitted through the isolation gate, and the modulated high-frequency pulse modulation signal is amplified by the driver 103 and then is input into the isolation gate 200 as V TX. The driver 103 is used for amplifying the oscillation signal to drive the isolation gate to the receiving end.
The transmitting end circuit comprises a self-adaptive frequency controller 101 and an oscillator 102, and is used for respectively realizing sampling and detecting a pulse input signal V IN, outputting a control signal 1 to the oscillator according to different pulse widths of the digital pulse signal V IN, and controlling the oscillation frequency f osc of the oscillator in real time so as to control the frequency of an oscillation output signal. The above is the main component of the adaptive frequency control (Adaptive Frequency Control, AFC) solution of the present disclosure. The input signal V IN is also used to control the switch 104 of the oscillator, the switch closes the oscillator to oscillate the modulation signal, the switch opens the oscillator to close, and the transmitting end output signal V TX is at a fixed dc level. The control signal 1 may be a voltage signal or a current signal. The output signal V TX of the transmitting-end circuit 100 may be a differential signal or a single-ended signal. The isolation gate 200 is an isolation medium between the transmitting end and the receiving end, and may be a transformer or a capacitor, and may be a differential structure or a single-ended structure. The receiving-end circuit 300 is configured to demodulate a signal output from the transmitting end, amplify and demodulate a signal V RX attenuated after the signal is input through the isolation gate, and finally recover V OUT. And the oscillator is used for controlling the oscillation frequency of the oscillator in real time, so as to control the frequency of the oscillation output signal. The oscillator may be a pseudo-differential ring oscillator.
According to the embodiment of the disclosure, the adaptive frequency controller 101 gradually decreases the oscillation frequency of the oscillator by the control signal when detecting that the digital pulse signal is at a high level, thereby reducing the power consumption of the oscillator.
According to an embodiment of the present disclosure, the adaptive frequency controller 101 includes:
A time-voltage converter 1011 for converting the input digital pulse signal V IN into a voltage signal; and
A voltage-to-current converter 1012 coupled to the time-to-voltage converter 1011 for receiving and converting the voltage signal into a current signal;
The adaptive frequency controller 101 obtains a real-time control signal according to the changes of the voltage signal and the current signal and outputs the control signal to the oscillator.
The transmitting end circuit also comprises an oscillator control switch, and when the digital pulse signal is in a low level, the oscillator control switch is disconnected, and the oscillator stops working at the moment.
As shown in fig. 5, the time-to-voltage converter 1011 inputs the pulse input signal V IN and outputs the voltage signal V C,VC as the input of the voltage-to-current converter 1012, and the voltage-to-current converter 1012 circuit can generate the current signal I C which changes simultaneously according to the change V C. According to the variation of the voltage VC and the current IC, the oscillator 102 is injected, generating a correspondingly varying oscillation frequency f osc.
According to the embodiment of the disclosure, the voltage signal gradually decreases with the increase of the pulse width of the input digital pulse signal V IN, and then the current value of the current signal gradually decreases, so that the control signal controls the corresponding gradual decrease of the oscillation frequency of the oscillator. Referring to fig. 6, V IN is a pulse input signal of the system, V C is an output of the time-to-voltage converter 1011 and an input voltage signal of the voltage-to-current converter 1012, and V P、VN is a differential output signal of the pseudo-differential oscillator. As can be seen from fig. 6, V C will vary with the pulse width of the input V IN, and when the pulse width is long, V C will slowly drop to a lower voltage value, and the frequency of the time domain waveform of V P、VN will slowly decrease, so as to gradually reduce the power consumption of the oscillator. When V IN is low (e.g., 0), V P、VN outputs VDD and 0, respectively, without oscillating signal, the oscillator is turned off at this time, and the static power consumption is almost 0.
In the embodiment of the disclosure, as shown in fig. 4 to 8, the time-voltage converter is composed of an Error Amplifier (EA), a PMOS pull-up tube M P1 and a load capacitor C L, the input signal is a digital pulse signal V IN and a reference voltage V REF, the output voltage signal is V C, wherein the digital pulse signal is connected to the negative terminal of the Error amplifier, the reference voltage is connected to the positive terminal of the Error amplifier, the output of the Error amplifier and the load capacitor, The drain electrode of the PMOS pull-up tube M P1 is connected, and the negative end of the error amplifier is also connected with the grid electrode of the PMOS pull-up tube M P1; when the voltage value of the digital pulse signal is a high level larger than the reference voltage, the PMOS pull-up tube is cut off, and the voltage value of the voltage signal is slowly reduced; when the voltage value of the digital pulse signal is low (for example, 0 level) which is smaller than the reference voltage, the PMOS pull-up tube is opened, the voltage value of the voltage signal is pulled up to the power supply voltage VDD1, which is equivalent to a reset operation, so that when the next V IN high level moment comes, V C is reduced from VDD1, and the frequency of the oscillator is always reduced from the highest frequency in the adjusting process. In the disclosed embodiment, as shown in connection with fig. 4 to 7, the voltage-to-current converter is composed of two parallel common-source amplifiers with source negative feedback and their corresponding current mirrors. The input NMOS tube M N1, the load resistor R N, the input PMOS tube M P2 and the load resistor R P respectively form a common source transconductance amplifier taking NMOS as input and a common source transconductance amplifier taking PMOS as input, and the conversion from the input voltage V C to the output currents I D1 and I D2 is realized respectively. This complementary architecture ensures that both V C ripple in the 0 to VDD range produces I D1 and I D2, thus having I P1-4 and I N1-4 currents, which helps to increase the frequency tuning range of the ring oscillator. Taking a common source transconductance amplifier with M N1 as an input tube as an example, the total transconductance of the circuit is
GN1＝gN1/(1+RNgN1) (1)
Wherein g N1 is the transconductance of M N1, and R N is the negative feedback resistance of the source of the circuit M N1. When R NgN1 > 1 is satisfied, G N1＝1/RN, which illustrates that a linear variation relationship between the input voltage and the output current is satisfied, helps to increase the frequency tuning range. The same applies to the design requirement of the common source amplifier taking M P2 as the input tube. The 10 current mirror branches copy and add the currents generated by the common source transconductance amplifier. Wherein, M P3 and M P4-8 complete the copy of current I D1, the drain electrode of M P3 is connected with the grid electrodes of M P3 and M P4, the grid electrodes of M P5-8 are connected together and connected with the grid electrode and the drain electrode of M P3, and the source electrodes of M P3-8 are connected together and connected with VDD 1. M N2, M N3-6 and M P5-8 complete the copying of the current of M P4, the gates of M N3-6 are connected together and connected with the gate and drain of M N2, and the sources of M N2-6 are connected together and connected with GND 1. M N7 and M N8-12 complete the copy of current I D2, the drain electrode of M N7 is connected with the gates of M N7 and M N8, the gates of M N9-12 are connected together and connected with the gate and drain electrode of M N7, the source electrode of M N7-12 is connected together and connected with GND1, M P9 and M P10-13 complete the copy of current M N8, the gates of M P10-13 are connected together and connected with the gate and drain electrode of M P9, the sources of M P9-13 are all connected together and to VDD 1. In order to realize the addition of the total currents of the two parallel common-source transconductance amplifiers, the drains of M P5-８ and M P10-13 are respectively connected, the drains of M N3-6 and M N9-12 are respectively connected, wherein the drains of M P5 and M P10 are connected, the drains of M P6 and M P11 are connected, the drains of M P7 and M P12 are connected, the drains of M P8 and M P13 are connected, and the total PMOS currents are respectively I P1、IP2、IP3、IP4. Wherein the drains of M N3 and M N9 are connected, the drains of M N4 and M N10 are connected, the drains of M N5 and M N11 are connected, the drains of M N6 and M N12 are connected, and the total NMOS current is I N1、IN2、IN3、IN4 respectively. I P1＝IP2＝IP3＝IP4＝IN1＝IN2＝IN3＝IN4 is satisfied during design. In order to meet the design requirement that I P1-4 and I N1-4 are reduced when V C is reduced, the equivalent transconductance of the G N1 and G P2 common-source transconductance amplifier needs to be reasonably designed to meet G N1＜GP2 during design.
It should be noted that in the specific embodiments shown in fig. 4 to 7, only one preferred implementation manner of the adaptive frequency controller 101 and the control signal 1 outputted by the adaptive frequency controller 101 may be implemented in other manners, for example, the adaptive frequency controller 101 includes only a time-voltage converter, outputs a voltage signal as a control signal, or the adaptive frequency controller 101 includes only a voltage-current converter, outputs a current signal as a control signal; or by other means: the present disclosure is not limited thereto.
In the disclosed embodiment, as shown in fig. 8, currents I P1-2、IN1-2 and I P3-4、IN3-4 from the time-to-current converter are respectively injected into the single-stage differential delay unit of the oscillator, the negative output terminal of the first-stage delay unit is connected to one side of the transmission gate T1, the other side of T1 is connected to the negative input terminal of the second-stage delay unit and the drain of the NMOS pull-down tube M N13, the source of M N13 is connected to GND1, and the negative output terminal of the second-stage delay unit and the positive input terminal of the first-stage delay unit are connected to the input of the driving buffer BUF 1. The output positive end of the first-stage delay unit is connected with one side of a transmission gate T2, the other side of the T2 is connected with the input positive end of the second-stage delay unit and the drain electrode of a PMOS pull-up tube M P14, the source electrode of M P14 is connected with VDD1, and the output positive end of the second-stage delay unit is connected with the input negative end of the first-stage delay unit and the input of a driving buffer BUF 2. V O1 and V O2 are output modulated voltage signals of BUF1 and BUF2, respectively.
There is a reverse relationship between the V SWN and V IN signals and a co-directional relationship between the V SW and V IN signals, which together control the connection or disconnection of the oscillator loop. When the input V IN is high, V SWN is low, V SW is high, T1 and T2 are both opened, M N13 and M P14 are both closed, an oscillator loop is formed, the oscillation function is maintained, an oscillation signal with frequency changing along with the pulse width change of the input V IN is generated according to the self-adaptive frequency control scheme, and the total power loss of the oscillator is reduced. When input V IN is low, V SWN is high, V SW is low, T1 and T2 are both turned off, the oscillator loop is turned off, the oscillation function is cancelled, M N13 and M P14 are both turned on, and V P/VO1 and V N/VO2 are pulled to low and high levels, respectively, thereby determining the potential output from the transmitting terminal at the moment of oscillation turn-off. By automatically controlling the oscillator switch according to the potential of the input signal V IN, the oscillator is guaranteed to be turned off when V IN is at a low potential, and unnecessary power waste of the oscillator at the moment is eliminated.
Thus, embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It should be noted that, in the drawings or the text of the specification, implementations not shown or described are all forms known to those of ordinary skill in the art, and not described in detail. Furthermore, the above definitions of the elements and methods are not limited to the specific structures, shapes or modes mentioned in the embodiments, and may be simply modified or replaced by those of ordinary skill in the art.
From the above description, it should be apparent to those skilled in the art that the present disclosure is based on an adaptive frequency controlled digital isolator.
In summary, the present disclosure provides a digital isolator based on adaptive frequency control, which automatically adjusts the total current injected into an oscillator by detecting whether an input random digital pulse signal is high level and the duration of the high level, so that the total current reduces the frequency of the oscillator under wide pulse width, and turns off the oscillator when low level is input, so that the power consumption of a transmitting end is controlled while maintaining high data rate, thereby being beneficial to reducing the power consumption of the total system.
It should also be noted that the foregoing describes various embodiments of the present disclosure. These examples are provided to illustrate the technical content of the present disclosure, and are not intended to limit the scope of the claims of the present disclosure. A feature of one embodiment may be applied to other embodiments by suitable modifications, substitutions, combinations, and separations.
It should be noted that in this document, having "an" element is not limited to having a single element, but may have one or more elements unless specifically indicated.
In addition, unless specifically stated otherwise, herein, "first," "second," etc. are used for distinguishing between multiple elements having the same name and not for indicating a level, a hierarchy, an order of execution, or a sequence of processing. A "first" element may occur together with a "second" element in the same component, or may occur in different components. The presence of an element with a larger ordinal number does not necessarily indicate the presence of another element with a smaller ordinal number.
In this context, the so-called feature A "or" (or) or "and/or" (and/or) feature B, unless specifically indicated, refers to the presence of B alone, or both A and B; the feature A "and" (and) or "AND" (and) or "and" (and) feature B, means that the nail and the B coexist; the terms "comprising," "including," "having," "containing," and "containing" are intended to be inclusive and not limited to.
Further, in this document, terms such as "upper," "lower," "left," "right," "front," "back," or "between" are used merely to describe relative positions between elements and are expressly intended to encompass situations of translation, rotation, or mirroring. In addition, in this document, unless specifically indicated otherwise, "an element is on another element" or similar recitation does not necessarily mean that the element contacts the other element.
Furthermore, unless specifically described or steps must occur in sequence, the order of the above steps is not limited to the list above and may be changed or rearranged according to the desired design. In addition, the above embodiments may be mixed with each other or other embodiments based on design and reliability, i.e. the technical features of the different embodiments may be freely combined to form more embodiments.
While the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be understood that the foregoing embodiments are merely illustrative of the invention and are not intended to limit the invention, and that any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the present disclosure are intended to be included within the scope of the present disclosure.
Claims (8)
1. A digital isolator based on adaptive frequency control, comprising: transmitting end circuit, barrier gate, and receiving end circuit, wherein:
The transmitting end circuit is used for generating corresponding pulse modulation signals with different frequencies according to the difference of pulse widths of the input digital pulse signals;
The isolation grid is connected between the transmitting end circuit and the receiving end circuit as an isolation medium and used for transmitting the pulse modulation signal;
The receiving end circuit is used for demodulating and recovering the pulse modulation signal;
the transmitting-end circuit includes:
an oscillator for converting an input digital pulse signal into an oscillation output signal; and
The self-adaptive frequency controller is used for receiving the digital pulse signals for sampling detection, outputting control signals to the oscillator according to different pulse widths of the digital pulse signals, and controlling the oscillation frequency of the oscillator in real time so as to control the frequency of an oscillation output signal;
The self-adaptive frequency controller gradually reduces the oscillation frequency of the oscillator through a control signal when detecting that the digital pulse signal is at a high level, so that the energy consumption of the oscillator is reduced.
2. The adaptive frequency control-based digital isolator of claim 1, the adaptive frequency controller comprising:
a time-voltage converter for converting an input digital pulse signal into a voltage signal; and
A voltage-to-current converter coupled to the time-to-voltage converter for receiving and converting the voltage signal to a current signal;
the self-adaptive frequency controller obtains a real-time control signal according to the change of the voltage signal and the current signal and outputs the control signal to the oscillator.
3. The adaptive frequency control-based digital isolator according to claim 2, wherein the voltage signal gradually decreases in voltage value with an increase in pulse width of the input digital pulse signal, and further gradually decreases in current value of the current signal, such that the control signal controls the oscillator to correspondingly gradually decrease the oscillation frequency.
4. The adaptive frequency control-based digital isolator according to claim 1, wherein the transmitting-side circuit further comprises an oscillator control switch, the oscillator control switch being turned off when the digital pulse signal is at a low level, and the oscillator being stopped.
5. The adaptive frequency control-based digital isolator according to claim 1, the control signal being a voltage signal or a current signal.
6. The adaptive frequency control-based digital isolator according to claim 1, the oscillating output signal being a differential signal or a single-ended signal.
7. The adaptive frequency control-based digital isolator according to claim 1, the oscillator being a pseudo-differential ring oscillator.
8. The adaptive frequency control-based digital isolator as claimed in claim 2,
The time-voltage converter comprises an error amplifier, a PMOS pull-up tube and a load capacitor; the time-voltage converter inputs a digital pulse signal and a reference voltage and outputs a voltage signal;
The voltage-current converter comprises two parallel common source amplifiers with source negative feedback and corresponding current mirrors;
The digital pulse signal is connected to the negative end of the error amplifier, the reference voltage is connected to the positive end of the error amplifier, the output of the error amplifier is connected with the load capacitor and the drain electrode of the PMOS pull-up tube, and the negative end of the error amplifier is also connected with the grid electrode of the PMOS pull-up tube; when the voltage value of the digital pulse signal is a high level larger than the reference voltage, the PMOS pull-up tube is cut off, and the voltage value of the voltage signal is slowly reduced; when the voltage value of the digital pulse signal is at a low level smaller than the reference voltage, the PMOS pull-up tube is opened, and the voltage value of the voltage signal is pulled up to the power supply voltage, so that the frequency of the oscillator is always reduced from the highest frequency in the adjusting process.
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| CN100433528C (en) * | 2004-11-17 | 2008-11-12 | 硕颉科技股份有限公司 | Frequency adjusting convertor circuit with variable pulse width and its controlling method |
| JP4960807B2 (en) * | 2007-08-28 | 2012-06-27 | セイコーインスツル株式会社 | Variable frequency oscillation circuit |
| CN102723887A (en) * | 2011-03-31 | 2012-10-10 | 陈长兴 | Synchronous rectification power supply device with pulse width modulation |
| US8780590B2 (en) * | 2012-05-03 | 2014-07-15 | Hong Kong Applied Science & Technology Research Institute Company, Ltd. | Output current estimation for an isolated flyback converter with variable switching frequency control and duty cycle adjustment for both PWM and PFM modes |
| US9293997B2 (en) * | 2013-03-14 | 2016-03-22 | Analog Devices Global | Isolated error amplifier for isolated power supplies |
| TWI498870B (en) * | 2013-09-23 | 2015-09-01 | Raydium Semiconductor Corp | Panel driving circuit and ring oscillator clock automatic synchronization method thereof |
| CN107919866B (en) * | 2016-10-08 | 2021-08-03 | 北京中科格励微科技有限公司 | Digital signal isolator |
| KR102370285B1 (en) * | 2017-08-11 | 2022-03-07 | 삼성전자주식회사 | Receiver and receiving method based on pulse |
| CN110943713A (en) * | 2019-12-18 | 2020-03-31 | 西安航天民芯科技有限公司 | Pulse width frequency adjustable CMOS ring oscillator |
| CN112039517B (en) * | 2020-09-04 | 2024-03-22 | 上海川土微电子有限公司 | Ultra-low power consumption capacitive digital isolator circuit based on Pulse-Coding |
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