CN115117060A - Embedded word line structure and manufacturing method thereof - Google Patents

Embedded word line structure and manufacturing method thereof Download PDF

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Publication number
CN115117060A
CN115117060A CN202110285290.9A CN202110285290A CN115117060A CN 115117060 A CN115117060 A CN 115117060A CN 202110285290 A CN202110285290 A CN 202110285290A CN 115117060 A CN115117060 A CN 115117060A
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China
Prior art keywords
layer
word line
barrier layer
forming
barrier
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Pending
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CN202110285290.9A
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Chinese (zh)
Inventor
林昶鸿
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Winbond Electronics Corp
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Winbond Electronics Corp
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Priority to CN202110285290.9A priority Critical patent/CN115117060A/en
Publication of CN115117060A publication Critical patent/CN115117060A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate

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Abstract

The invention provides an embedded word line structure and a manufacturing method thereof. The embedded word line structure includes a first isolation structure, an embedded word line, a first barrier layer, a second barrier layer, a channel layer, and a second isolation structure. The first isolation structure is disposed in a substrate and has a trench. The embedded word line is disposed on a bottom surface of the trench. The first barrier layer is disposed between the embedded word line and the sidewall and the bottom surface of the trench. The second barrier layer covers a top surface of the buried word line and includes a main portion and an extension portion, wherein the main portion is located on the buried word line, and the extension portion extends upward from a periphery of the main portion. The channel layer is disposed on the first barrier layer and the second barrier layer. The second isolation structure is arranged on the channel layer.

Description

Embedded word line structure and manufacturing method thereof
Technical Field
The present invention relates to semiconductor structures and methods for fabricating the same, and more particularly, to a buried word line structure and a method for fabricating the same.
Background
In order to increase the integration of the DRAM to accelerate the operation speed of the device and meet the demand of the consumer for miniaturized electronic devices, a buried word line DRAM (buried word line DRAM) has been developed in recent years to meet the demand.
Generally, the buried word lines may be disposed in the isolation structures. However, when the distance between the embedded word line and the capacitor disposed on the substrate is too close, electrons stored in the capacitor are easily attracted by the electric field generated by the embedded word line, resulting in generation of leakage current.
Disclosure of Invention
The present invention is directed to an embedded word line structure, wherein an embedded word line is provided with a channel layer, and the channel layer is connected to a barrier layer disposed around the embedded word line.
The invention is directed to a method for fabricating a buried word line structure, which is used to fabricate the buried word line structure.
According to an embodiment of the present invention, the buried word line structure includes a first isolation structure, a buried word line, a first barrier layer, a second barrier layer, a channel layer, and a second isolation structure. The first isolation structure is disposed in a substrate and has a trench. The embedded word line is disposed on a bottom surface of the trench. The first barrier layer is disposed between the embedded word line and the sidewall and the bottom surface of the trench. The second barrier layer covers a top surface of the buried word line and includes a main portion and an extension portion, wherein the main portion is located on the buried word line, and the extension portion extends upward from a periphery of the main portion. The channel layer is disposed on the first barrier layer and the second barrier layer. The second isolation structure is arranged on the channel layer.
According to an embodiment of the present invention, a method for fabricating a buried word line structure includes the following steps. First, a first isolation structure is formed in a substrate. Then, a trench is formed in the first isolation structure. Then, a first barrier layer is formed on the lower sidewall and the bottom surface of the trench. Then, forming a buried word line on the first barrier layer. Then, a second barrier layer is formed on the top surface of the embedded word line, wherein the second barrier layer includes a main portion and an extension portion, the main portion is located on the embedded word line, and the extension portion extends upward from the periphery of the main portion. Then, a channel layer is formed on the first barrier layer and the second barrier layer. And forming a second isolation structure on the channel layer.
In view of the above, in the embedded word line structure of the present invention, the barrier layer having the extension portion is formed on the embedded word line, and the channel layer is formed on the barrier layer having the extension portion and extends downward beside the extension portion to be connected to another barrier layer formed around the embedded word line. Therefore, when the assembly is operated, the electric field near the corner region of the embedded word line can be effectively reduced, so as to avoid the generation of leakage current caused by the attraction of electrons stored in the capacitor by the electric field generated by the embedded word line.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1A to fig. 1G are schematic cross-sectional views illustrating a manufacturing process of a buried word line structure according to an embodiment of the invention.
Detailed Description
Fig. 1A to fig. 1G are schematic cross-sectional views illustrating a manufacturing process of a buried word line structure according to an embodiment of the invention.
Referring to fig. 1A, a substrate 100 is provided. The substrate 100 may be a semiconductor substrate, and in the present embodiment, the substrate 100 is, for example, a silicon substrate. Next, a first isolation structure 102 is formed in the substrate 100. The first isolation structure 102 is, for example, a Shallow Trench Isolation (STI) structure. In the present embodiment, the material of the first isolation structure 102 is, for example, silicon nitride, but the invention is not limited thereto. In other embodiments, the material of the first isolation structure 102 may also be silicon oxide. Thereafter, a trench 104 is formed in the first isolation structure 102. The trench 104 is used to define a region of a subsequently formed buried word line.
Referring to fig. 1B, after forming the trench 104, an insulating layer 106 may be formed on the sidewalls and bottom of the trench 104. The insulating layer 106 is used to reduce interference between a plurality of subsequently formed buried word lines. In the embodiment, the insulating layer 106 is, for example, an In Situ Steam Generation (ISSG) oxide layer, but the invention is not limited thereto. Next, a barrier material layer 108 is formed on the insulating layer 106 and the surface of the substrate 100. In the embodiment, the barrier material layer 108 is, for example, a titanium nitride layer, but the invention is not limited thereto. Then, a word line material layer 110 is formed on the substrate 100 to fill the trench 104. In the embodiment, the word line material layer 110 is, for example, a tungsten layer, but the invention is not limited thereto.
Referring to fig. 1C, an etch-back process is performed to remove a portion of the barrier material layer 108 and a portion of the word line material layer 110 to form a buried word line 112 and a first barrier layer 114 between the buried word line 112 and the sidewalls and bottom of the trench 104. In detail, in the present embodiment, during the etch-back process, the barrier material layer 108 and the word line material layer 110 on the surface of the substrate 100 and on the sidewalls at the upper portion of the trench 104 are removed. Next, a dielectric layer 116 is formed on the surface of the substrate 100, on the sidewalls of the trench 104, on the embedded word lines 112, and on the first barrier layer 114. The dielectric layer 116 and the first isolation structure 102 need to have an etching selectivity. In the present embodiment, since the material of the first isolation structure 102 is, for example, silicon nitride, the material of the dielectric layer 116 is, for example, silicon oxide. In other embodiments, when the material of the first isolation structure 102 is silicon oxide, the material of the dielectric layer 116 is silicon nitride. In addition, in order to avoid the contact between the subsequently formed channel layer and the buried word line 112, the thickness of the dielectric layer 116 must not exceed the thickness of the first barrier layer 114, which will be described in detail later.
Referring to fig. 1D, an etch-back process is performed to remove a portion of the dielectric layer 116 to form a dielectric structure 118. In detail, in the present embodiment, during the etch-back process, the dielectric layer 116 on the surface of the substrate 100, on the sidewalls at the upper portion of the trench 104, and on the buried word line 112 is removed to expose the top surface of the buried word line 112, and the dielectric layer 116 on the sidewalls at the lower portion of the trench 104 is remained. The remaining dielectric layer 116 forms a dielectric structure 118 on the first barrier layer 114. Since the thickness of the dielectric layer 116 does not exceed the thickness of the first barrier layer 114, the dielectric structure 118 is formed only on the first barrier layer 114 without contacting the buried word line 112. Furthermore, due to the etch selectivity between the dielectric layer 116 and the first isolation structure 102, the first isolation structure 102 is not damaged during the above etch back process.
Referring to fig. 1E, a barrier material layer 120 is formed on the surface of the substrate 100, on the sidewalls of the trench 104, on the top surface of the embedded word line 112, and on the dielectric structure 118. In the embodiment, the barrier material layer 120 is, for example, a titanium nitride layer, but the invention is not limited thereto. Then, a protective material layer 122 is formed on the substrate 100 to fill the trench 104. In the embodiment, the protection material layer 122 is, for example, a spin-on coating (SOC) layer, but the invention is not limited thereto.
Referring to fig. 1F, an etch-back process is performed on the protection material layer 122 to remove a portion of the protection material layer 122, so as to form a protection layer 124 on the barrier material layer 120. The passivation layer 124 exposes the barrier material layer 120 at the upper portion of the trench 104. In other words, the passivation layer 124 covers the barrier material layer 120 on the top surface of the buried word line 112 and on the sidewalls and a portion of the top surface of the dielectric structure 118. Then, an anisotropic etching process is performed to remove the barrier material layer 120 not covered by the protection layer 124 by using the protection layer 124 as an etching mask. As a result, the second barrier layer 126 is formed on the top surface of the buried word line 112. In the present embodiment, the second barrier layer 126 includes a main portion 126a, an extension portion 126b and a horizontal portion 126 c. The main portion 126a is located on the top surface of the buried word line 112, the extension portion 126b extends upward from the periphery of the main portion 126a, and the horizontal portion 126c is connected to the top of the extension portion 126b to form the second barrier layer 126 having a "U" shaped cross section.
The cross-sectional shape of the second barrier layer 126 can be varied by controlling the thickness of the formed barrier material layer 120. For example, in the present embodiment, the thickness of the barrier material layer 120 is smaller than the width of the dielectric structure 118, so the second barrier layer 126 can be formed to have a horizontal portion 126 c. In another embodiment, when the thickness of the barrier material layer 120 is equal to the width of the dielectric structure 118, the second barrier layer 126 is formed without the horizontal portion 126 c. In addition, the thickness of the barrier material layer 120 may not be larger than the width of the dielectric structure 118, otherwise the second barrier layer with the extension portion cannot be formed.
Referring to fig. 1G, an etching process is performed to remove the dielectric structure 108 and the protection layer 124. Next, a channel layer 128 is formed on the first barrier layer 114 and the second barrier layer 126. The channel layer 128 is formed, for example, by forming a channel material layer on the substrate 100 to fill the trench 104, and then performing an etch-back process to remove the channel material layer on the surface of the substrate 100 and at the upper portion of the trench 104. In particular, the electric field generated by the channel layer 128 must be lower than the electric field generated by the embedded word line 112 when the device is operated, as will be further described below. Therefore, in the embodiment, when the buried word line 112 is a tungsten layer, the channel layer 128 is a polysilicon layer, for example, but the invention is not limited thereto. In the present embodiment, after the above-mentioned etch back process, the second barrier layer 126 is not exposed, i.e. the channel layer 128 completely covers the second barrier layer 126 and contacts the first barrier layer 114 around the second barrier layer 126, but the invention is not limited thereto. In other embodiments, after the etch back process, the channel layer 128 may expose a portion of the second barrier layer 126, and the channel layer 128 may still be in contact with the first barrier 114 around the second barrier layer 126. For example, the horizontal portion 126c and a portion of the extension portion 126b of the second barrier layer 126 may be exposed. Thereafter, a second isolation structure 130 is formed on the channel layer 128 to complete the embedded word line structure 10 of the present embodiment. In the present embodiment, the material of the second isolation structure 130 is, for example, silicon nitride, so as to avoid damage when an oxide layer on the substrate 100 is processed in a subsequent process.
The embedded word line structure of the present invention will be described with reference to fig. 1G.
Referring to fig. 1G, in the buried word line structure 10, the second barrier layer 126 having the extension portion 126b is disposed on the buried word line 112, and the channel layer 128 is disposed on the second barrier layer 126 and extends downward beside the extension portion 126b to connect with the first barrier layer 114. As a result, when the device is operated, the electric field near the corner regions of the embedded word lines 112 can be effectively reduced, so that electrons stored in the capacitors formed subsequently on the substrate 100 are not easily attracted by the electric field generated by the embedded word lines 112, and thus the generation of leakage current can be reduced or even avoided.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and these modifications or substitutions do not depart from the spirit of the corresponding technical solutions of the embodiments of the present invention.

Claims (10)

1. A buried word line structure, comprising:
the first isolation structure is arranged in the substrate and is provided with a groove;
the embedded word line is arranged on the bottom surface of the groove;
a first barrier layer disposed between the embedded word line and the sidewall and the bottom surface of the trench;
a second barrier layer covering a top surface of the buried word line and including a main portion and an extension portion, wherein the main portion is located at the buried word line and the extension portion extends upward from a periphery of the main portion;
a channel layer disposed on the first barrier layer and the second barrier layer; and
a second isolation structure disposed on the channel layer.
2. The embedded word line structure of claim 1, wherein the channel layer wraps the second barrier layer and contacts the first barrier layer.
3. The embedded word line structure of claim 1, wherein the second barrier layer further includes a horizontal portion connected to a top of the extension portion.
4. The embedded word line structure of claim 1, further comprising an insulating layer disposed on and in contact with sidewalls and a bottom surface of the trench.
5. The buried word line structure of claim 1, wherein the buried word line includes a tungsten layer.
6. The buried word line structure of claim 1, wherein the channel layer comprises a polysilicon layer.
7. A method for fabricating a buried word line structure, comprising:
forming a first isolation structure in a substrate;
forming a trench in the first isolation structure;
forming a first barrier layer on the lower sidewall and the bottom surface of the trench;
forming a buried word line on the first barrier layer;
forming a second barrier layer on a top surface of the buried word line, wherein the second barrier layer includes a main portion and an extension portion, the main portion is located on the buried word line, and the extension portion extends upward from a periphery of the main portion;
forming a channel layer on the first barrier layer and the second barrier layer; and
and forming a second isolation structure on the channel layer.
8. The method of claim 7, wherein the step of forming the second barrier layer comprises:
forming a dielectric layer on the surface of the substrate, on the sidewalls of the trench, on the first barrier layer, and on the buried word lines after forming the buried word lines, wherein the thickness of the dielectric layer does not exceed the thickness of the first barrier layer;
removing a portion of the dielectric layer to form a dielectric structure on the first barrier layer and expose the top surface of the embedded word line;
forming a layer of barrier material on the surface of the substrate, on the sidewalls of the trench, on the dielectric structure, and on the top surface of the buried word line;
forming a protective layer over the barrier material layer, wherein the protective layer exposes the barrier material layer at an upper portion of the trench;
using the protection layer as a mask, performing an anisotropic etching process to remove a portion of the barrier material layer; and
and removing the protective layer and the dielectric structure.
9. The method as claimed in claim 7, wherein the channel layer covers the second barrier layer and contacts the first barrier layer.
10. The method as claimed in claim 7, further comprising forming an insulating layer on sidewalls and a bottom surface of the trench before forming the first barrier layer.
CN202110285290.9A 2021-03-17 2021-03-17 Embedded word line structure and manufacturing method thereof Pending CN115117060A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110285290.9A CN115117060A (en) 2021-03-17 2021-03-17 Embedded word line structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110285290.9A CN115117060A (en) 2021-03-17 2021-03-17 Embedded word line structure and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN115117060A true CN115117060A (en) 2022-09-27

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110285290.9A Pending CN115117060A (en) 2021-03-17 2021-03-17 Embedded word line structure and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN115117060A (en)

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