CN115116863A - Chip heat dissipation structure and preparation method thereof - Google Patents
Chip heat dissipation structure and preparation method thereof Download PDFInfo
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- CN115116863A CN115116863A CN202210827825.5A CN202210827825A CN115116863A CN 115116863 A CN115116863 A CN 115116863A CN 202210827825 A CN202210827825 A CN 202210827825A CN 115116863 A CN115116863 A CN 115116863A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4878—Mechanical treatment, e.g. deforming
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4882—Assembly of heatsink parts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/38—Cooling arrangements using the Peltier effect
Abstract
The invention relates to a chip heat radiation structure and a preparation method thereof, wherein the preparation method of the chip heat radiation structure comprises the following steps: thinning the refrigeration piece to enable the cold surface of the refrigeration piece to be attached to the chip; the base plate is provided with an installation groove in a penetrating way; wherein, the substrate is arranged on the heat dissipation member; installing the refrigeration piece in the installation groove to enable the hot surface to be attached to the heat dissipation piece; the surface of the base plate, which is back to the heat dissipation piece, is flush with the cold surface of the refrigeration piece; and packaging the chip and the refrigerating piece. After will refrigerating the piece attenuate for the cold side of refrigeration piece can with the direct laminating contact of chip, improve refrigeration efficiency, also reduced the thickness of refrigeration piece, make the refrigeration piece install in the mounting groove after can with the surperficial parallel and level of base plate, reduced chip heat radiation structure's whole volume, increase the integrated level of chip heat radiation structure and relevant equipment. Meanwhile, the hot surface of the refrigerating sheet is attached to the radiating piece, so that the radiating effect and the radiating efficiency of the chip radiating structure are further improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a chip heat dissipation structure and a preparation method thereof.
Background
The current semiconductor refrigerating sheet has wide application field, can effectively refrigerate and radiate the researched electronic product in aspects of medicine, military, optics, cosmetology and the like, and ensures that the temperature of the product is always in a constant value during operation. The method for using the refrigerating sheet at the present stage mainly comprises the steps of clamping and fixing the refrigerating sheet through screws, adhering resin glue, welding, connecting soft pads or other materials and the like to enable the refrigerating sheet to be tightly attached to a heating element, and tightly attaching the refrigerating sheet to a heating surface of the element through a cold surface of the refrigerating sheet, so that mutual heat conduction is balanced; and meanwhile, a radiator is arranged on the hot surface of the heat pipe to conduct heat to the outside. However, the volumes of the refrigerating sheets used at present are large, the thickness of the device is increased to a certain extent by sticking the refrigerating sheets on the surface of the device, and the cold surface of the refrigerating sheet packaged by ceramics cannot be directly contacted with a hot point of a chip, so that the refrigerating efficiency is reduced.
Disclosure of Invention
In view of the above, it is necessary to provide a chip heat dissipation structure capable of improving the heat dissipation efficiency of a chip and a method for manufacturing the same.
A method of making a chip heat dissipation structure, comprising:
thinning the refrigeration piece to enable the cold surface of the refrigeration piece to be attached to the chip; the two opposite side surfaces of the refrigerating sheet are respectively a cold surface and a hot surface;
the base plate is provided with an installation groove in a penetrating way; wherein the substrate is arranged on the heat sink;
installing the refrigeration sheet in the installation groove to enable the hot surface to be attached to the heat dissipation piece; the cold surface of the refrigeration sheet is flush with the surface of the base plate, which faces away from the heat dissipation member;
and packaging the chip and the refrigeration piece.
In one embodiment, the thinning process of the refrigeration sheet includes:
unsealing the refrigeration sheet, and removing a ceramic layer of the refrigeration sheet; the initial state of refrigeration piece is the encapsulated state, just have the ceramic layer in the refrigeration piece, the ceramic layer sets up on the cold face.
In one embodiment, mounting the refrigeration pill in the mounting groove comprises:
and connecting the electrode lead of the refrigerating sheet and the electrode lead of the chip to the substrate.
In one embodiment, the cooling plate is installed in the installation groove, and the method further comprises the following steps:
the refrigeration piece integrated into one piece in on the base plate, and be located in the mounting groove.
In one embodiment, the step of thinning the refrigeration sheet further comprises:
providing a first substrate and providing a conductive structure on the first substrate;
arranging a semiconductor component on the conductive structure, and etching the conductive structure;
and covering a second substrate on the semiconductor assembly to form the refrigerating sheet.
In one embodiment, disposing a conductive structure on the first substrate, disposing a semiconductor assembly on the conductive structure, etching the conductive structure, covering the semiconductor assembly with a second substrate, and forming the chilling plate includes:
the conductive structure comprises a first conductive layer and a second conductive layer, and the semiconductor assembly comprises an N-type semiconductor and a P-type semiconductor;
providing the first conductive layer on the first substrate;
growing thermoelectric arms on the first conducting layer, and carrying out particle doping to form the N-type semiconductor and the P-type semiconductor;
etching the first conductive layer corresponding to the structures of the N-type semiconductor and the P-type semiconductor;
covering the second conducting layer on the N-type semiconductor and the P-type semiconductor, and etching the second conducting layer corresponding to the structures of the N-type semiconductor and the P-type semiconductor;
and covering the second substrate on the N-type semiconductor and the P-type semiconductor to form the refrigerating sheet.
In one embodiment, the number of the N-type semiconductors and the number of the P-type semiconductors are at least two, two adjacent P-type semiconductors are arranged at intervals, each N-type semiconductor is arranged between two adjacent P-type semiconductors, and an electric signal on one P-type semiconductor sequentially passes through the second conductive layer, the N-type semiconductors and the first conductive layer to reach the other P-type semiconductor.
In one embodiment, the step of thinning the refrigeration sheet further comprises:
arranging a third substrate and forming a p-GaN layer on the third substrate;
etching the p-GaN layer and forming a passivation structure on the p-GaN layer;
and etching the passivation structure, and arranging an electrode structure on the passivation structure to form the main body of the chip.
In one embodiment, forming a passivation structure on the p-GaN layer, etching the passivation structure, and disposing an electrode structure on the passivation structure to form a body of the chip, includes:
the passivation structure comprises a first passivation layer and a second passivation layer; the electrode structure comprises a grid electrode, a drain electrode and a source electrode;
forming the first passivation layer on the p-GaN layer;
etching the first passivation layer, and arranging the drain electrode and the source electrode on the first passivation layer to form ohmic contact and arranging a grid electrode to form a grid metal contact;
forming the second passivation layer on the first passivation layer;
etching the second passivation layer to form the drain, source and gate with metallized interconnects to form the body of the chip.
A chip heat radiation structure comprises a heat radiation piece, a substrate and a refrigeration piece, wherein the substrate is arranged on the heat radiation piece, and a mounting groove is formed in the substrate in a penetrating mode; the both sides face that carries on the back on the refrigeration piece is cold face and hot face respectively, the cold face of refrigeration piece is used for laminating with the chip, the refrigeration piece is installed during in the mounting groove, the hot face of refrigeration piece can with the laminating of radiating piece, just the cold face with the base plate dorsad the surperficial parallel and level of radiating piece.
According to the chip heat radiation structure and the preparation method thereof, after the refrigeration piece is thinned, the cold surface of the refrigeration piece can be directly attached and contacted with the chip, the refrigeration efficiency is improved, the thickness of the refrigeration piece is also reduced, the refrigeration piece can be flush with the surface of the substrate after being installed in the installation groove, the whole volume of the chip heat radiation structure is reduced, and the integration level of the chip heat radiation structure and related equipment is increased. Meanwhile, the hot surface of the refrigerating sheet is attached to the radiating piece, so that the radiating effect and the radiating efficiency of the chip radiating structure are further improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the invention and not to limit the invention.
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a chip heat dissipation structure in an embodiment;
FIG. 2 is a schematic diagram of a package of a chip and a cooling plate in the embodiment of FIG. 1;
fig. 3 is a schematic structural diagram of a refrigeration sheet in the embodiment of fig. 1;
fig. 4 is a schematic structural diagram of a main body of the chip in the embodiment of fig. 1.
The elements in the figure are labeled as follows:
10. a chip heat dissipation structure; 100. a refrigeration plate; 110. a first substrate; 120. a conductive structure; 121. a first conductive layer; 122. a second conductive layer; 130. a semiconductor component; 131. an N-type semiconductor; 132. a P-type semiconductor; 140. a second substrate; 150. an electrode assembly; 151. a negative electrode; 152. a positive electrode; 200. a main body of the chip; 210. a third substrate; 220. a p-GaN layer; 230. a passivation structure; 231. a first passivation layer; 232. a second passivation layer; 240. an electrode structure; 241. a drain electrode; 242. a source electrode; 243. a gate electrode; 300. a substrate; 400. a heat sink.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
Referring to fig. 1 and 2, the chip heat dissipation structure 10 in an embodiment includes a substrate 300, a heat dissipation member 400, and a cooling member. In this embodiment, the cooling member is a cooling plate 100. The substrate 300 is disposed on the heat sink 400, and a mounting groove is formed in the substrate 300 in a penetrating manner; the both sides face that carries on the back on the refrigeration piece 100 is cold face and hot face respectively, the cold face of refrigeration piece 100 is used for laminating with the chip, refrigeration piece 100 is installed during in the mounting groove, the hot face of refrigeration piece 100 can with the laminating of radiating piece 400, just cold face with base plate 300 dorsad the surface parallel and level of radiating piece 400. The chip heat dissipation structure 10 is applied to various fields such as medicine, military, optics, cosmetology and the like, and can effectively refrigerate and dissipate heat of electronic products in related fields.
The method for manufacturing the chip heat dissipation structure 10 in one embodiment includes:
thinning the refrigeration piece 100 to enable the cold surface of the refrigeration piece 100 to be attached to the chip; wherein, the two opposite side surfaces of the refrigeration sheet 100 are respectively a cold surface and a hot surface;
the base plate 300 is provided with a mounting groove in a penetrating manner; wherein the substrate 300 is disposed on the heat sink 400;
installing the refrigeration sheet 100 in the installation groove to attach the hot surface to the heat sink 400; wherein the cold surface of the refrigeration sheet 100 is flush with the surface of the substrate 300 facing away from the heat sink 400;
encapsulating the chip and the refrigeration pill 100.
According to the chip heat dissipation structure 10 and the preparation method thereof, after the refrigeration piece 100 is thinned, the cold surface of the refrigeration piece 100 can be directly attached to and contacted with the chip, the refrigeration efficiency is improved, the thickness of the refrigeration piece 100 is reduced, the refrigeration piece 100 can be flush with the surface of the substrate 300 after being installed in the installation groove, the whole volume of the chip heat dissipation structure 10 is reduced, and the integration level of the chip heat dissipation structure 10 and related equipment is increased. Meanwhile, the hot surface of the refrigeration sheet 100 is attached to the heat dissipation member 400, so that the heat dissipation effect and the heat dissipation efficiency of the chip heat dissipation structure 10 are further improved.
In one embodiment, the thinning process of the refrigeration sheet 100 includes:
unsealing the refrigeration sheet 100, and removing a ceramic layer of the refrigeration sheet 100; the initial state of the refrigeration piece 100 is a packaging state, and the refrigeration piece 100 is provided with a ceramic layer which is arranged on the cold surface.
The cooling plate 100 is generally combined with the chip in a packaged state. The thickness of the cooling plate 100 in the packaged state is large, and after the chips are combined, the overall structure is large, which is not convenient for miniaturization of electronic products. After the refrigerating sheet 100 is unsealed, the ceramic layer in the refrigerating sheet 100 is removed, the thickness of the refrigerating sheet 100 is reduced, and the thickness of the whole structure is effectively reduced. Thereby making the chip directly contact with the cold surface of the refrigeration plate 100 and ensuring the heat dissipation efficiency of the chip heat dissipation structure 10.
In one embodiment, mounting the refrigeration pill 100 in the mounting slot includes:
and connecting the electrode leads of the refrigeration plate 100 and the electrode leads of the chip to the substrate 300.
At present, the refrigeration piece needs to be additionally provided with a power supply wiring design during operation, so that the circuit structure of an electronic product is complicated. After the refrigeration piece 100 is directly contacted with the chip, the electrode lead on the refrigeration piece 100 and the electrode lead on the chip can be connected to the same substrate 300, the circuit structure complexity of an electronic product is reduced, the reliability of the chip heat dissipation structure 10 is ensured, and the refrigeration efficiency is improved.
In one embodiment, the installing the refrigeration sheet 100 in the installation groove further comprises:
the refrigeration sheet 100 is integrally formed on the base plate 300 and is located in the mounting groove.
The method for using the refrigerating sheet at the present stage mainly comprises the steps of clamping and fixing the refrigerating sheet through screws, adhering resin glue, welding, connecting soft pads or other materials and the like to enable the refrigerating sheet to be tightly attached to a heating element, and tightly attaching the refrigerating sheet to a heating surface of the element through a cold surface of the refrigerating sheet, so that mutual heat conduction is balanced; while mounting the heat sink 400 on its hot side to conduct heat to the outside. However, the thickness of the heat dissipation structure of the chip is large due to the connection method, so that the size of the related components is large, and the miniaturization of the instrument structure is not convenient to realize. In the embodiment, the refrigeration sheet 100 is integrally formed on the substrate 300, so that the hot surface of the refrigeration sheet 100 can be in direct contact with the heat sink 400, the heat of the refrigeration sheet 100 is rapidly led out, and the refrigeration efficiency of the refrigeration sheet 100 is improved. And the chip can direct contact refrigerate the cold side of piece 100, further improves the refrigeration efficiency of piece 100 to the chip that refrigerates, guarantees chip heat radiation structure 10's practicality and reliability, improves the holistic integrated level of structure.
Referring to fig. 2 and 3, in one embodiment, thinning the refrigeration sheet 100 further includes:
providing a first substrate 110, and providing a conductive structure 120 on the first substrate 110;
disposing a semiconductor element 130 on the conductive structure 120, and etching the conductive structure 120;
a second substrate 140 is covered on the semiconductor assembly 130 to form the refrigeration plate 100.
In one embodiment, disposing a conductive structure 120 on the first substrate 110, disposing a semiconductor component 130 on the conductive structure 120, etching the conductive structure 120, and covering the semiconductor component 130 with a second substrate 140 to form the refrigeration plate 100 includes:
the conductive structure 120 includes a first conductive layer 121 and a second conductive layer 122, and the semiconductor component 130 includes an N-type semiconductor 131 and a P-type semiconductor 132;
providing the first conductive layer 121 on the first substrate 110;
growing thermoelectric legs on the first conductive layer 121 and performing particle doping to form the N-type semiconductor 131 and the P-type semiconductor 132;
etching the first conductive layer 121 corresponding to the structures of the N-type semiconductor 131 and the P-type semiconductor 132;
covering the second conductive layer 122 on the N-type semiconductor 131 and the P-type semiconductor 132, and etching the second conductive layer 122 corresponding to the structures of the N-type semiconductor 131 and the P-type semiconductor 132;
the second substrate 140 is covered on the N-type semiconductor 131 and the P-type semiconductor 132 to form the refrigeration sheet 100.
In one embodiment, the step of covering the second substrate 140 on the N-type semiconductor 131 and the P-type semiconductor 132 further includes:
disposing the electrode assembly 150 of the refrigeration pill 100 on the first conductive layer 121; wherein the negative electrode 151 of the electrode assembly 150 is connected to the P-type semiconductor 132, and the positive electrode 152 of the electrode assembly 150 is connected to the N-type semiconductor 131. The electrode assembly 150 is used for connecting the base plate 300, and power is supplied to the refrigerating sheet 100 through the base plate 300.
In one embodiment, the second substrate 140 is covered on the N-type semiconductor 131 and the P-type semiconductor 132, and then the method further includes:
the first substrate 110 and the second substrate 140 are thinned.
In one embodiment, the number of the N-type semiconductors 131 and the P-type semiconductors 132 is at least two, two adjacent P-type semiconductors 132 are arranged at intervals, each N-type semiconductor 131 is arranged between two adjacent P-type semiconductors 132, and an electrical signal on one P-type semiconductor 132 sequentially passes through the second conductive layer 122, the N-type semiconductor 131 and the first conductive layer 121 to reach the other P-type semiconductor 132.
Referring to fig. 2 and 4, in one embodiment, thinning the refrigeration sheet 100 further includes:
providing a third substrate 210 and forming a p-GaN layer 220 on the third substrate 210;
etching the p-GaN layer 220 and forming a passivation structure 230 on the p-GaN layer 220;
the passivation structure 230 is etched and an electrode structure 240 is disposed on the passivation structure 230 to form the body 200 of the chip.
In one embodiment, forming a passivation structure 230 on the p-GaN layer 220, etching the passivation structure 230, and disposing an electrode structure 240 on the passivation structure 230 to form the body 200 of the chip includes:
the passivation structure 230 includes a first passivation layer 231 and a second passivation layer 232; the electrode structure 240 includes a gate 243, a drain 241, and a source 242;
forming the first passivation layer 231 on the p-GaN layer 220;
etching the first passivation layer 231, and disposing the drain electrode 241 and the source electrode 242 on the first passivation layer 231 to form an ohmic contact, and disposing a gate electrode 243 to form a gate electrode 243 metal contact;
forming the second passivation layer 232 on the first passivation layer 231;
the second passivation layer 232 is etched to form the drain 241, the source 242 and the gate 243 into metallization interconnects, forming the body 200 of the chip.
Specifically, the main body 200 of the chip is a gallium nitride high electron mobility transistor. Gallium nitride high electron mobility transistors are representative of wide bandgap power semiconductor devices, which have great potential in high frequency power applications. While GaN materials have higher electron mobility, saturated electron velocity, and breakdown electric field than Si and SiC.
When the semiconductor contacts with metal, a barrier layer is formed, but when the doping concentration of the semiconductor is high, electrons can penetrate through the barrier layer by virtue of a tunnel effect, so that ohmic contact with low resistance is formed. Ohmic contact is very important for semiconductor devices, good ohmic contact is formed to facilitate input and output of current, and alloys with different formulations are often selected as ohmic contact materials for different semiconductor materials.
In one embodiment, the drain 241, the source 242, and the gate 243 form a metallization interconnect, which then further includes:
the third substrate 210 is thinned.
In one embodiment, said forming of said refrigeration pill 100 and said forming of said main body 200 of the chip, followed by:
and packaging the refrigeration plate 100 and the main body 200 of the chip.
The stability of connection of the refrigeration piece 100 and the chip is ensured. Meanwhile, when packaging is performed, electrode leads of the chip and the cooling plate 100 are connected to the substrate 300.
In one embodiment, a thermally conductive silicone grease is applied between the hot side of the refrigeration plate 100 and the heat sink 400. Further improving the heat conduction efficiency. Because the refrigeration piece can be in direct contact with the chip, the refrigeration efficiency is improved, and the heat-conducting silicone grease is not required to be coated between the refrigeration piece and the chip.
In one embodiment, the packaging of the refrigeration pill 100 and the body 200 of the chip includes:
removing or thinning the second substrate 140;
bonding the third substrate 210 and the second conductive layer 122;
and (5) completing the packaging.
Since the third substrate 210 of the chip 200 is close to the second conductive layer 122 on the top of the refrigeration chip, the second substrate 140 on the top of the refrigeration chip 100 may be thinned, or the second substrate 140 may be completely removed, and the second conductive layer 122 on the top of the refrigeration chip 100 is directly bonded to the third substrate 210 of the chip, and finally the two parts are packaged.
Along with the continuous improvement of the integration level of electronic components, heat generated during the operation of components can not be discharged to the outside in time, so that the internal temperature of the components is overhigh, and hot spots occur, thereby reducing the working performance of the components and damaging the whole components in serious cases. In response to such problems, thermal management techniques have been proposed and applied in many fields to solve various heat generation problems. At present, a plurality of heat dissipation technologies exist only in the field of chips and packaging, including various heat dissipation schemes such as adding heat sinks, heat pipes, air cooling, water cooling and the like to the outside.
The peltier effect of semiconductors can be utilized as a heat sink for solid state refrigeration. Semiconductor refrigeration, also called thermoelectric refrigeration, is the use of the peltier effect of semiconductor materials. When direct current passes through a couple formed by connecting two different semiconductor (P-type and N-type) materials in series, heat can be absorbed and released at two ends of the couple respectively, and the aim of refrigeration can be fulfilled. The method is a refrigeration technology for generating negative thermal resistance, and is mainly characterized by no moving parts, no noise, small volume, convenient operation and maintenance, compact structure and no need of coolant. The refrigeration efficiency can be adjusted by changing the magnitude and the direction of the current, and the reliability is higher. Wherein, acceptor impurities are doped in the semiconductor to make the hole concentration larger than the electron concentration, thus obtaining the P-type semiconductor. And doping donor impurities into the semiconductor to enable the electron concentration to be larger than the hole concentration, and thus obtaining the N-type semiconductor.
When electrons flow from the low-energy P-type material to the high-energy N-type material, the electrons jump from the low energy level to the high energy level, which shows that the electrons need to absorb heat, so that a cold surface (a cold surface of a refrigerating sheet) is formed at the node; when electrons flow from the high-energy N-type material to the low-energy P-type material, the electrons jump from the high energy level to the low energy level, which shows that the electrons need to release heat, so that a hot surface (a hot surface of the refrigerating sheet) is formed at the node. In fact, most closed loops formed by different metals have this phenomenon; the Peltier effect of the current commercial bismuth telluride-based thermoelectric material is more obvious, namely the electron level jump is higher, and the corresponding refrigeration efficiency is higher.
The thickness of the refrigeration piece 100 is effectively reduced after the ceramic layer on the surface is removed by unsealing the refrigeration piece 100; after the refrigeration piece 100 is attached to the chip, the electrode lead of the refrigeration piece 100 and the electrode lead of the chip are bonded to the same substrate 300, and no extra lead is required to be provided for the refrigeration piece 100 to supply power; meanwhile, the refrigeration plate 100 is integrally integrated on the substrate 300, so that the integration level can be greatly improved.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may directly conflict with the first and second features, or the first and second features may indirectly conflict with each other through intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature "under," "beneath," and "under" a second feature may be directly under or obliquely under the second feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and the like as used herein are for illustrative purposes only and do not denote a unique embodiment.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that various changes and modifications can be made by those skilled in the art without departing from the spirit of the invention, and these changes and modifications are all within the scope of the invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A preparation method of a chip heat dissipation structure is characterized by comprising the following steps:
thinning the refrigeration piece to enable the cold surface of the refrigeration piece to be attached to the chip; the two opposite side surfaces of the refrigerating sheet are respectively a cold surface and a hot surface;
the base plate is provided with an installation groove in a penetrating way; wherein the substrate is arranged on the heat sink;
installing the refrigeration sheet in the installation groove to enable the hot surface to be attached to the heat dissipation piece; the cold surface of the refrigeration sheet is flush with the surface of the base plate, which faces away from the heat dissipation member;
and packaging the chip and the refrigeration piece.
2. The method for preparing the chip heat dissipation structure according to claim 1, wherein the thinning of the refrigeration sheet comprises:
unsealing the refrigeration sheet, and removing a ceramic layer of the refrigeration sheet; the initial state of refrigeration piece is the encapsulated state, just have the ceramic layer in the refrigeration piece, the ceramic layer sets up on the cold face.
3. The method for preparing the chip heat dissipation structure as recited in claim 1, wherein the installing the cooling plate in the installation groove comprises:
and connecting the electrode lead of the refrigerating sheet and the electrode lead of the chip to the substrate.
4. The method for preparing a chip heat dissipation structure according to claim 1, wherein the cooling fins are mounted in the mounting grooves, and further comprising:
the refrigeration piece integrated into one piece in on the base plate, and be located in the mounting groove.
5. The method for preparing the chip heat dissipation structure according to any one of claims 1 to 4, wherein the step of thinning the refrigeration sheet further comprises:
providing a first substrate and providing a conductive structure on the first substrate;
arranging a semiconductor component on the conductive structure, and etching the conductive structure;
and covering a second substrate on the semiconductor assembly to form the refrigerating sheet.
6. The method for preparing the chip heat dissipation structure according to claim 5, wherein the steps of providing a conductive structure on the first substrate, providing a semiconductor assembly on the conductive structure, etching the conductive structure, and covering a second substrate on the semiconductor assembly to form the cooling fin comprise:
the conductive structure comprises a first conductive layer and a second conductive layer, and the semiconductor assembly comprises an N-type semiconductor and a P-type semiconductor;
providing the first conductive layer on the first substrate;
growing thermoelectric arms on the first conducting layer, and carrying out particle doping to form the N-type semiconductor and the P-type semiconductor;
etching the first conductive layer corresponding to the structures of the N-type semiconductor and the P-type semiconductor;
covering the second conducting layer on the N-type semiconductor and the P-type semiconductor, and etching the second conducting layer corresponding to the structures of the N-type semiconductor and the P-type semiconductor;
and covering the second substrate on the N-type semiconductor and the P-type semiconductor to form the refrigerating sheet.
7. The method for manufacturing the chip heat dissipation structure according to claim 6, wherein the number of the N-type semiconductors and the number of the P-type semiconductors are at least two, two adjacent P-type semiconductors are arranged at intervals, each N-type semiconductor is arranged between two adjacent P-type semiconductors, and an electrical signal on one P-type semiconductor sequentially passes through the second conductive layer, the N-type semiconductor and the first conductive layer to reach the other P-type semiconductor.
8. The method for preparing the chip heat dissipation structure according to any one of claims 1 to 4, wherein the step of thinning the refrigeration sheet further comprises:
arranging a third substrate and forming a p-GaN layer on the third substrate;
etching the p-GaN layer and forming a passivation structure on the p-GaN layer;
and etching the passivation structure, and arranging an electrode structure on the passivation structure to form the main body of the chip.
9. The method for manufacturing the chip heat dissipation structure according to claim 8, wherein forming a passivation structure on the p-GaN layer, etching the passivation structure, and disposing an electrode structure on the passivation structure to form a main body of the chip comprises:
the passivation structure comprises a first passivation layer and a second passivation layer; the electrode structure comprises a grid electrode, a drain electrode and a source electrode;
forming the first passivation layer on the p-GaN layer;
etching the first passivation layer, and arranging the drain electrode and the source electrode on the first passivation layer to form an ohmic contact and arranging a grid electrode to form a grid metal contact;
forming the second passivation layer on the first passivation layer;
etching the second passivation layer to form the drain, source and gate with metallized interconnects to form the body of the chip.
10. A chip heat dissipation structure, comprising:
a heat sink;
the base plate is arranged on the heat dissipation piece, and an installation groove is formed in the base plate in a penetrating mode; and
the refrigeration piece, the both sides face that carries on the back on the refrigeration piece is cold face and hot face respectively, the cold face of refrigeration piece is used for laminating with the chip, the refrigeration piece is installed during in the mounting groove, the hot face of refrigeration piece can with the laminating of radiating piece, just the cold face with the base plate dorsad the surperficial parallel and level of radiating piece.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210827825.5A CN115116863A (en) | 2022-07-14 | 2022-07-14 | Chip heat dissipation structure and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210827825.5A CN115116863A (en) | 2022-07-14 | 2022-07-14 | Chip heat dissipation structure and preparation method thereof |
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| CN115116863A true CN115116863A (en) | 2022-09-27 |
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| CN202210827825.5A Pending CN115116863A (en) | 2022-07-14 | 2022-07-14 | Chip heat dissipation structure and preparation method thereof |
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| Country | Link |
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