CN115116838A - Method for improving dielectric layer peeling by wet process - Google Patents
Method for improving dielectric layer peeling by wet process Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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Abstract
The invention provides a method for improving dielectric layer peeling by using a wet process, which comprises the following steps: providing a wafer, wherein a grid dielectric layer is formed on the surface of the wafer, and the grid dielectric layer is provided with a plurality of grooves at intervals; filling metal in the groove, and removing the metal on the surface of the grid dielectric layer by a planarization process to form a metal grid; and performing a wet process to remove the contaminants on the back of the wafer and the metal layer remaining on the edge of the wafer, wherein the wet process comprises the following steps: putting the wafer into a first cleaning solution, and simultaneously immersing the wafer back and the wafer edge by the first cleaning solution until pollutants on the wafer back and a residual metal layer on the wafer edge are removed; and forming an interlayer dielectric layer which covers the gate dielectric layer and the metal gate. The method provided by the invention improves the problem of peeling of the interlayer dielectric layer of the crystal edge and improves the process quality under the condition of not changing the existing process flow.
Description
Technical Field
The invention relates to the field of semiconductor device manufacturing, in particular to a method for improving dielectric layer peeling.
Background
With the development of semiconductor technology, the size of semiconductor devices is continuously reduced, corresponding technology nodes are continuously improved, and the influence of wafer edges (wafer level) on the manufacturing process is larger and larger. After processes such as chemical vapor deposition, physical vapor deposition, grinding process, photolithography process, etching process, etc., recesses may be formed at the edge of the wafer and different thin film layers may be deposited, and the bonding force between the thin film layers of the edge of the wafer may be weak due to the rough surface and uneven thickness of each thin film layer.
Particularly, in the metal gate manufacturing process, after the metal layer is deposited, the metal layer is deposited and embedded in the concave part of the crystal edge, the metal layer positioned on the crystal edge is remained after planarization treatment, and then after the interlayer dielectric layer is formed, the residual metal layer on the crystal edge and the dielectric layer on the crystal edge have a larger stress action, so that the bonding force between the film layers is weaker, the dielectric layer is easy to peel off in the subsequent process, and the quality of the subsequent process is influenced.
Disclosure of Invention
In order to solve the problem of peeling off of the dielectric layer of the crystal edge, the invention provides a method for improving the peeling off of the dielectric layer by using a wet process, which comprises the following steps:
providing a wafer, wherein a grid dielectric layer is formed on the surface of the wafer, and the grid dielectric layer is provided with a plurality of grooves at intervals;
filling metal in the groove, and removing the metal on the surface of the grid dielectric layer by a planarization process to form a metal grid;
and performing a wet process to remove the pollutants on the back of the wafer and the residual metal layer on the edge of the wafer, wherein the wet process comprises the following steps: putting the wafer into first cleaning liquid, so that the wafer back and the wafer edge are immersed by the first cleaning liquid at the same time until pollutants on the wafer back and a residual metal layer on the wafer edge are removed;
and forming an interlayer dielectric layer which covers the grid dielectric layer and the metal grid.
Optionally, the material of the gate dielectric layer and the interlayer dielectric layer comprises SiO 2 。
Optionally, the crystal edge is an annular region on the front surface of the wafer within a predetermined distance from the sidewall of the wafer, and the predetermined distance is 2mm to 3 mm.
Optionally, the material of the metal layer comprises aluminum.
Optionally, the first cleaning solution includes one of an SC1 cleaning solution and an SC2 cleaning solution, and the SC1 cleaning solution is a mixture of ammonia water, hydrogen peroxide and water; the SC2 cleaning solution is a mixture of hydrochloric acid, hydrogen peroxide and water.
Optionally, after the step of removing the contamination on the back of the wafer and the metal layer remaining on the edge of the wafer, the wet process further includes: and putting the wafer into a second cleaning solution, so that the wafer back and the wafer edge are immersed by the second cleaning solution at the same time until the interlayer dielectric layer of the wafer edge is partially removed.
Optionally, the second cleaning solution includes diluted hydrofluoric acid, and the volume percentage concentration of the diluted hydrofluoric acid is 1% to 49%.
Optionally, the diluted hydrofluoric acid has a concentration of 1% by volume.
Optionally, the wet process is performed in a cleaning tank having a shield plate assembly that at least protects the metal gate from being corroded by the cleaning solution.
Optionally, the process of forming the gate dielectric layer, the metal layer and the interlayer dielectric layer includes at least one of an atomic layer deposition process, a chemical vapor deposition process and a physical vapor deposition process.
Compared with the prior art, the method for improving the peeling of the dielectric layer by using the wet process has the following advantages:
the residual metal layer at the crystal edge is removed through the wet process, after the interlayer dielectric layer is formed, the bonding force between the film layers at the crystal edge is improved, the problem of peeling of the interlayer dielectric layer at the crystal edge caused by the residual metal layer in the prior art is solved, and the process quality is improved; meanwhile, the wet process can simultaneously carry out the steps of cleaning the wafer back and removing the residual metal layer on the wafer edge in the existing cleaning machine, and the existing process flow does not need to be increased or changed. Therefore, the wet process improves the problem of interlayer dielectric layer peeling without changing the existing process flow, and effectively improves the process quality.
Drawings
FIG. 1 is a scanning electron microscope image of a stripped dielectric layer;
FIG. 2 is a flow chart of a method for improving dielectric layer exfoliation in an embodiment of the present invention;
FIGS. 3-7 are schematic views of cross-sectional views of a wafer at corresponding steps of a method for improving peeling-off of a dielectric layer according to an embodiment of the invention;
wherein the reference numerals are as follows:
10-a stripped dielectric layer; 20-a wafer; 201-a gate dielectric layer; 202-a trench; 203-shallow trench isolation structures; 204-crystal edge; 205-metal gate; 206-residual metal layer; 207-back of wafer; 208-an interlayer dielectric layer; 31-a cleaning tank; 32-a first cleaning liquid; 33-a fender assembly; 331-annular baffle.
Detailed Description
To make the objects, advantages and features of the present invention more apparent, the method for improving peeling of a dielectric layer by a wet process provided by the present invention is further described in detail with reference to the accompanying drawings.
Referring to fig. 1, fig. 1 is a scanning electron microscope image of a stripped dielectric layer 10 in a conventional metal gate process, wherein the different shapes of the bulk thin films are all stripped from the edge of the wafer.
The reason why the dielectric layer 10 is peeled off is that a metal layer is deposited at the edge recess during the formation of the metal gate. When the metal layer is subjected to chemical mechanical polishing treatment, the metal layer at the depressed crystal edge can not be completely removed, and the residual metal layer has different thickness and a rough surface. When a dielectric layer is deposited later, excessive stress is generated between the residual metal layer with different thickness and rough surface and the dielectric layer deposited on the upper layer, and finally the dielectric layer deposited on the upper layer is peeled off. These stripped dielectric layers 10 can become a source of defects, which can cause damage to subsequent processes, such as blocking the etching holes when wires are introduced, and cause electrical anomalies in the device. In order to effectively prevent the dielectric layer from peeling off, the residual metal layer at the edge of the die needs to be removed.
Moreover, after the metal layer deposition and the chemical mechanical polishing are performed, the back of the wafer is also contaminated by the metal, and the contaminants need to be removed in time, so as to avoid adverse effects on the subsequent processes. In the prior art, a wafer back cleaning process is usually adopted to remove the contaminants on the wafer back.
In view of the above, the present invention provides a method for improving peeling of a dielectric layer by using a wet process, referring to fig. 2, the method comprises the following steps:
step S1: providing a wafer, wherein a grid dielectric layer is formed on the surface of the wafer and is provided with a plurality of spaced grooves;
step S2: filling metal in the groove, and removing the metal on the surface of the grid dielectric layer by a planarization process to form a metal grid;
step S3: and performing a wet process to remove the contaminants on the back of the wafer and the metal layer remaining on the edge of the wafer, wherein the wet process comprises the following steps: putting the wafer into a first cleaning solution, and simultaneously immersing the wafer back and the wafer edge by the first cleaning solution until pollutants on the wafer back and a residual metal layer on the wafer edge are removed;
step S4: forming an interlayer dielectric layer covering the gate dielectric layer and the metal gate.
Referring to fig. 3, step S1 is executed to provide a wafer 20, wherein a gate dielectric layer 201 is formed on a surface of the wafer 20, and the gate dielectric layer has a plurality of spaced trenches 202.
In this embodiment, the material of the gate dielectric layer 201 is preferably SiO 2 (SiO 2 Either undoped or doped) or other suitable materials, such as silicon oxynitride (SiON); the gate dielectric layer 201 is preferably formed by a chemical vapor deposition process, but other suitable processes may be selected. In this embodiment, a shallow trench isolation structure 203 is further formed below the gate dielectric layer 201, and the shallow trench isolation structure 203 may be located at the edge of the wafer 20, or may be located at other positions of the wafer 20, and may be specifically configured according to process requirements. For example, fig. 3 shows a shallow trench isolation structure at the edge. The material of the shallow trench isolation structure 203 is preferably SiO 2 Other suitable materials known in the art, such as silicon oxynitride (SiON), are also possible. The shallow trenchThe trench isolation structure 203 is conventional and will not be described herein.
After the gate dielectric layer 201 is formed, a step-like or ramp-like recess structure is formed on the crystal edge 204 due to the influence of the previous process. In the present embodiment, the edge 204 is defined as an annular region on the front surface of the wafer 20 within a predetermined distance from the sidewall, and the predetermined distance is between 2mm and 3 mm.
Referring to fig. 4, step S2 is performed to fill the trench 202 with metal and perform a planarization process to remove the metal on the surface of the gate dielectric layer 201 to form a metal gate 205.
The planarization process removes at least the metal layer above the plane of the upper opening of the trench 202 and the metal layer above the gate dielectric layer 201, exposes the upper surface of the gate dielectric layer 201, and ensures that the surface of the wafer 20 is smooth. After the planarization process, the metal gate 205 is formed in the trench. In addition, since the edge has a recess, after the metal layer is formed, the metal layer is deposited on the recessed edge, and after the planarization process, the metal layer on the recessed edge is difficult to remove, so that the residual metal layer 206 is formed. These residual metal layers 206 may cause excessive stress between the subsequently deposited inter-layer dielectric layers, which may eventually cause the inter-layer dielectric layers thereon to peel off, and thus need to be removed in a timely manner.
Since aluminum has excellent electrical properties, in this embodiment, the material of the metal layer is preferably metal aluminum, and may also be other suitable metals, such as tungsten; the forming process of the metal layer is preferably an atomic layer deposition process, but is not limited to this, and may also be other suitable processes; the planarization process is preferably a Chemical Mechanical Polishing (CMP) process, but is not limited thereto, and other suitable processes may be employed.
In another embodiment, before the metal layer is formed, a barrier layer and a work function layer are sequentially formed on the trench and the gate dielectric layer, and the barrier layer, the work function layer and the metal layer form a metal gate stack to improve the quality of a finally formed metal gate. Wherein the thickness of the metal layer exceeds 95% of the thickness of the entire metal gate stack. The work function layer can adjust the work function of the metal gate, and the barrier layer separates the gate dielectric layer below the barrier layer from the work function layer above the barrier layer so as to reduce the interaction between the gate dielectric layer and the work function metal layer. The materials and forming processes of the barrier layer and the work function layer can refer to the prior art, and are not described herein in detail.
Referring to fig. 5, in step S3, a wet process is performed to remove the contamination on the wafer back and the metal layer 206 remaining on the wafer edge, the wet process includes: the wafer 20 is placed in a first cleaning solution, so that the wafer back 207 and the wafer edge 204 are simultaneously immersed by the first cleaning solution until the contaminants on the wafer back 207 and the residual metal layer 206 on the wafer edge 204 are removed.
In this embodiment, the contaminants of the wafer back 207 mainly include metals and metal oxides, which are formed in the foregoing step S2, and these contaminants are easily diffused to become defect sources to cause device damage or cause cross contamination, and therefore need to be removed in time. The first cleaning solution is preferably an SC1 cleaning solution, the SC1 cleaning solution is a mixture of ammonia water, hydrogen peroxide and water, the volume ratio of the ammonia water to the hydrogen peroxide to the water is 1:2:50, contaminants of the crystal back 207 and the residual metal layer 206 of the crystal edge 204 can be effectively removed, and other oxide contaminants can be removed at the same time. To ensure the cleaning effect, the parameters of the wet process can be controlled, for example, in this embodiment, the thickness of the residual metal layer 206 of the edge 204 reaches several tens of thickness
To ensure the residual metal layer is completely removed, the etching rate of the SC1 cleaning solution on the residual metal layer 206 is controlled to be
The cleaning time is controlled between 180s and 300 s. The first cleaning liquid is not limited to the SC1 cleaning liquid, and in another embodiment, the first cleaning liquid may be the SC2 cleaning liquid, and the SC2 cleaning liquid is hydrochloric acidThe volume ratio of the first cleaning liquid to the second cleaning liquid is 1:1:50, and the first cleaning liquid can also be other suitable cleaning liquids.
In this embodiment, the wet process may be used to simultaneously perform the operations of cleaning the backside and removing the residual metal layer 206, so as to simplify the process flow. The wet process can be performed in an existing cleaning machine. For example, in the present embodiment, the wet process is performed in a cleaning tank of a single wafer cleaning machine, referring to fig. 6, the wafer 20 is fixed and placed above the cleaning tank 31, the first cleaning solution 32 is introduced into the cleaning tank 31, so that the first cleaning solution 32 immerses the wafer back 207 and the wafer edge 204, and the wafer back 207 and the wafer edge 204 are cleaned for a certain time until the contaminants on the wafer back 207 and the residual metal layer 206 on the wafer edge 204 are removed. In the above operation, in order to ensure that the first cleaning liquid 32 does not corrode the metal gate 205 on the front surface of the wafer 20 when cleaning the back side 207 and the edge 204, and further, in order to ensure that the first cleaning liquid 32 does not corrode other regions of the front surface of the wafer 20 except the edge 204, a guard plate assembly 33 is usually required. The guard plate assembly 33 is a pot structure, an annular baffle 331 on the outer side of the pot is buckled on the front surface of the wafer 20, a desired guard area is formed and the wafer edge 204 is exposed by adjusting the guard radius of the guard plate assembly 33, the guard area at least covers the metal gate 205, and further, the guard area covers other areas of the front surface of the wafer 20 except the wafer edge 204. After the ring-shaped baffle 331 on the outside of the bowl is buckled on the front surface of the wafer 20, nitrogen (N) is continuously blown into the bowl 2 ) So that N is formed in the pot body 2 The protective gas flow, which continuously blows to the periphery of the basin, can prevent the first cleaning liquid 32 at the periphery of the annular baffle 331 from entering the protective area, thereby ensuring that the metal grid 205 on the front surface of the wafer 20 is not corroded by the first cleaning liquid 32.
In this embodiment, after the step of removing the contaminants of the back side 207 and the residual metal layer 206 of the edge 204, the wet process further includes: and cleaning with a second cleaning solution. Referring to fig. 6, the method for cleaning with the second cleaning solution includes: after the first cleaning solution is cleaned, a discharge pipeline of the cleaning tank 31 is opened to discharge the first cleaning solution 32, then the discharge pipeline is closed and the second cleaning solution is introduced, so that the second cleaning solution immerses the wafer back 207 and the wafer edge 204, and the wafer edge 204 is cleaned for a certain time until the gate dielectric layer 201 of the wafer edge 204 is partially removed. The second cleaning solution is also used to protect the metal gate 205 on the front surface of the wafer 20 from being corroded by the second cleaning solution by using the protection plate assembly 33.
The second cleaning solution is preferably diluted hydrofluoric acid (DHF), and a small portion of the gate dielectric layer 201 (not more than the gate dielectric layer) of the edge of the wafer is etched away by using the DHF
) So as to ensure that the residual metal layer 206 on the gate dielectric layer 201 is completely removed, and improve the removal effect of the residual metal layer 206 of the die edge 204; meanwhile, the DHF can also effectively remove some oxide particles, such as silicon oxide particles, on the back surface 207, so as to improve the cleaning effect of the back surface.
When cleaning with DHF, it is necessary to ensure that the gate dielectric layer 201 is only partially removed, i.e., DHF does not damage the structure below the gate dielectric layer 201. To achieve the above purpose, the process parameters are controlled, for example, in this embodiment, the concentration of the DHF is not too high, the volume percentage concentration is preferably 1%, and the etching rate of the DHF on the residual metal layer 206 is controlled to be within the range of
And the etching time does not exceed 60 s.
In other embodiments, after the wet process is completed, the wafer 20 is then subjected to a deionized water rinse to remove the residual rinse solution and other by-products on the surface of the wafer 20. The deionized water cleaning is a frequently used process in the wafer production and processing processes, and is not described herein again.
In step S3, the residual metal layer 206 of the die edge 204 is effectively removed by the wet process, so as to improve the problem of interlayer dielectric layer peeling caused by the residual metal layer 206; meanwhile, the wet process can simultaneously clean the back of the wafer and remove the residual metal layer 206 on the edge of the wafer in the existing cleaning machine, and the existing process flow does not need to be increased or changed. Therefore, the wet process can effectively improve the process quality under the condition of not changing the conventional process flow.
Referring to fig. 7, step S4 is performed to form an interlayer dielectric layer 208, where the interlayer dielectric layer 208 covers the gate dielectric layer 201 and the metal gate 205.
In the present embodiment, the process of forming the interlayer dielectric layer 208 includes a chemical vapor deposition process, but is not limited thereto, and may be other suitable processes. The material of the interlayer dielectric layer 208 comprises SiO 2 But is not limited thereto, and may also be SiON, for example. The interlayer dielectric layer 208 covers the gate dielectric layer 201 and also covers the edge 204, and at the edge 204, the interlayer dielectric layer 208 is directly attached to the gate dielectric layer 201, and has a similar mechanical structure due to the fact that both are insulating dielectric layers, and further, in the present embodiment, both are SiO layers 2 Therefore, the interlayer bonding force between the two is strong and effectively reduces the stress effect between the two, and the strong interlayer bonding force can effectively prevent the interlayer dielectric layer 208 from peeling off.
In summary, the method for improving dielectric layer peeling by using a wet process provided by the invention effectively removes the residual metal layer on the edge of the wafer by using the wet process, and improves the problem of interlayer dielectric layer peeling caused by the residual metal layer; meanwhile, the wet process can simultaneously carry out the steps of cleaning the wafer back and removing the residual metal layer on the wafer edge in the existing cleaning machine, and the existing process flow does not need to be increased or changed. Therefore, the wet process effectively solves the problem of interlayer dielectric layer peeling without changing the existing process flow, and improves the process quality.
Further, it is to be understood that "layer" as referred to herein refers to a thin film layer formed by an existing suitable thin film preparation process. It will also be understood that when a "layer" is referred to as being "on" or "under" another "layer, it can be directly on or under the other" layer "or intervening layers may also be present, unless the context clearly dictates otherwise, between the two layers. It is also to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (10)
1. The method for improving the peeling of the dielectric layer by using the wet process comprises the following steps:
providing a wafer, wherein a grid dielectric layer is formed on the surface of the wafer, and the grid dielectric layer is provided with a plurality of grooves at intervals;
filling metal in the groove, and removing the metal on the surface of the grid dielectric layer by a planarization process to form a metal grid;
and performing a wet process to remove the contaminants on the back of the wafer and the metal layer remaining on the edge of the wafer, wherein the wet process comprises the following steps: putting the wafer into a first cleaning solution, and simultaneously immersing the wafer back and the wafer edge by the first cleaning solution until pollutants on the wafer back and a residual metal layer on the wafer edge are removed;
forming an interlayer dielectric layer covering the gate dielectric layer and the metal gate.
2. The method of claim 1, wherein the material of the gate dielectric layer and the interlayer dielectric layer comprises SiO 2 。
3. The method of claim 1, wherein the edge of the wafer is an annular region on the front surface of the wafer within a predetermined distance from a sidewall of the wafer, and the predetermined distance is 2mm to 3 mm.
4. The method for improving exfoliation of a dielectric layer by a wet process as claimed in claim 1, wherein the material of the metal layer comprises aluminum.
5. The method for improving the peeling of the dielectric layer by using the wet process as claimed in claim 1, wherein the first cleaning solution comprises one of a SC1 cleaning solution and a SC2 cleaning solution, and the SC1 cleaning solution is a mixture of ammonia water, hydrogen peroxide and water; the SC2 cleaning solution is a mixture of hydrochloric acid, hydrogen peroxide and water.
6. The method of improving dielectric layer exfoliation using a wet process as claimed in claim 1, wherein after the step of removing backside contaminants and the edge-to-edge remaining metal layer, the wet process further comprises: and putting the wafer into a second cleaning solution, so that the wafer back and the wafer edge are simultaneously immersed by the second cleaning solution until the gate dielectric layer of the wafer edge is partially removed.
7. The method of claim 6, wherein the second cleaning solution comprises diluted hydrofluoric acid, and the diluted hydrofluoric acid has a concentration of 1-49% by volume.
8. The method of claim 7, wherein said diluted hydrofluoric acid is present in a concentration of 1 vol%.
9. The method for improving peeling of dielectric layer by using wet process as claimed in claim 1 or 6, wherein said wet process is performed in a cleaning tank having a protection plate assembly, said protection plate assembly at least protecting said metal gate from being corroded by cleaning solution.
10. A method for improving dielectric layer exfoliation according to claim 1, wherein the processes for forming the gate dielectric layer, the metal layer, and the interlayer dielectric layer comprise at least one of an atomic layer deposition process, a chemical vapor deposition process, and a physical vapor deposition process.
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