CN115116206B - Load protection alarm circuit of double MOS tube - Google Patents
Load protection alarm circuit of double MOS tube Download PDFInfo
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- CN115116206B CN115116206B CN202210889477.4A CN202210889477A CN115116206B CN 115116206 B CN115116206 B CN 115116206B CN 202210889477 A CN202210889477 A CN 202210889477A CN 115116206 B CN115116206 B CN 115116206B
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- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 8
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 238000001514 detection method Methods 0.000 claims description 27
- 230000009977 dual effect Effects 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 4
- 230000001939 inductive effect Effects 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 claims description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 235000011389 fruit/vegetable juice Nutrition 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
Classifications
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- G—PHYSICS
- G08—SIGNALLING
- G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
- G08B21/00—Alarms responsive to a single specified undesired or abnormal condition and not otherwise provided for
- G08B21/18—Status alarms
- G08B21/185—Electrical failure alarms
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Abstract
The invention provides a load protection alarm circuit with double MOS (metal oxide semiconductor) tubes, which comprises an MCU (micro control unit) singlechip and a load control circuit, wherein the load control circuit comprises a load power supply, a load, an NMOS (N-channel metal oxide semiconductor) tube, a PMOS (P-channel metal oxide semiconductor) tube and a fifth resistor; the load power supply, the load, the NMOS tube, the PMOS tube and the fifth resistor are sequentially connected in series to be grounded, the NMOS tube and the PMOS tube are controlled by different levels of different control ends of the MCU singlechip, and the MCU singlechip also detects the level between the NMOS tube and the PMOS tube and the voltage value of the fifth resistor. The invention can accurately detect the product faults, and prevents the risk and hidden trouble in the aspect of safety to users under the non-working state of the load by triple protection alarm.
Description
Technical Field
The present invention relates to a load protection alarm circuit, and more particularly, to a load protection alarm circuit with dual MOS transistors for home appliances.
Background
At present, household appliances (handheld juice cups, intelligent bowls, electric rice cookers and the like) are provided with a load which is a resistive heating load or an inductive rotating load, and the load is controlled to be turned on or off through a triode or an MOS tube. Under normal conditions, the load of the household appliance products is controlled by only one triode or MOS tube, if the triode or MOS tube is invalid or damaged, the triode or MOS tube is always conducted and is not controlled, and the load always works, so that potential safety hazards and risks can be generated.
Disclosure of Invention
The invention aims to overcome the defects of the prior art in controlling the load of household appliances, and provides a load protection alarm circuit with double MOS (metal oxide semiconductor) tubes.
The invention solves the technical problems through the following technical scheme:
the load protection alarm circuit with the double MOS tubes comprises an MCU (micro control unit) singlechip and a load control circuit, wherein the load control circuit comprises a load power supply, a load, an NMOS (N-channel metal oxide semiconductor) tube, a PMOS (P-channel metal oxide semiconductor) tube and a fifth resistor;
the load power supply, the load, the NMOS tube, the PMOS tube and the fifth resistor are sequentially connected in series to be grounded, the NMOS tube and the PMOS tube are controlled by different levels of different control ends of the MCU singlechip, and the MCU singlechip also detects the level between the NMOS tube and the PMOS tube and the voltage value of the fifth resistor.
Preferably, the NMOS tube is conducted when the first control end of the MCU singlechip is at a high level, the PMOS tube is conducted when the second control end of the MCU singlechip is at a low level, and the load is conducted when the NMOS tube and the PMOS tube are conducted simultaneously.
Preferably, the load control circuit further comprises an NPN triode, a first resistor, a second resistor and a third resistor;
the base electrode of the NPN triode is connected with the first control end through a sixth resistor and is grounded through the first resistor; the emitter of the NPN triode is connected with the grid electrode of the NMOS tube and is grounded through the second resistor; the collector electrode of the NPN triode is connected with VCC;
and the grid electrode of the PMOS tube is connected with the second control end through a seventh resistor and is also connected with VCC through a third resistor.
Preferably, the MCU singlechip also detects whether the NMOS tube fails to be conducted or not and whether the PMOS tube fails to be conducted or not in the non-working state of the load through a level detection end.
Preferably, the source electrode of the NMOS tube is connected with the source electrode of the PMOS tube, and the drain electrode of the PMOS tube is grounded through the fifth resistor;
the source electrode of the NMOS tube is connected with the level detection end through an eighth resistor, and is also connected with the detection control end of the MCU singlechip through a ninth resistor, and the detection control end is set to output high level, output low level or input.
Preferably, the MCU singlechip also detects whether the load is conducted or not through a voltage detection end.
Preferably, the load control circuit further includes a fourth resistor, wherein the non-grounded end of the fifth resistor is connected to the voltage detection end through the fourth resistor, and the voltage detection end is grounded through a capacitor.
Preferably, the third control end of the MCU singlechip is connected with the alarm through a tenth resistor.
Preferably, the third control end controls the alarm to send out an alarm when any one of the following conditions occurs:
under the non-working state of the load, the NMOS tube fails to be conducted;
under the non-working state of the load, the PMOS tube fails to be conducted;
and in the non-working state of the load, the MCU singlechip detects that the voltage of the fifth resistor is not 0.
Preferably, the load is a resistive heating load or an inductive rotating load.
On the basis of conforming to the common knowledge in the field, the above preferred conditions can be arbitrarily combined to obtain the preferred examples of the invention.
The invention has the positive progress effects that: according to the invention, the NMOS tube and the PMOS tube are connected in series, and are controlled by different levels of different control ends; for the NMOS tube and the PMOS tube which are connected in series, judging whether the NMOS tube and the PMOS tube are in failure conduction or not by detecting the level between the NMOS tube and the PMOS tube; and for the load, judging whether the load is conducted or not by detecting the voltage value of the fifth resistor. The invention can accurately detect the product faults, and prevents the risk and hidden trouble in the aspect of safety to users under the non-working state of the load by triple protection alarm.
Drawings
Fig. 1 is a circuit diagram of a load protection alarm circuit of a dual MOS transistor according to embodiment 1 of the present invention.
Detailed Description
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments are shown.
Example 1
Fig. 1 shows a load protection alarm circuit of a dual MOS transistor of this embodiment. The load protection alarm circuit comprises an MCU singlechip U1 and a load control circuit, wherein the load control circuit comprises a load power supply VLOAD, a load L1, a PMOS tube Q1, an NMOS tube Q2 and a fifth resistor R5; the load power supply VLOAD, the load L1, the NMOS tube Q2, the PMOS tube Q1 and the fifth resistor R5 are sequentially connected in series to be grounded, the NMOS tube Q2 and the PMOS tube Q1 are controlled by different levels of different control ends of the MCU singlechip U1, and the MCU singlechip U1 also detects the level between the NMOS tube Q2 and the PMOS tube Q1 and the voltage value of the fifth resistor R5.
The fifth resistor R5 may be a resistor with a high precision and a small resistance value. The control end can be an I/O port of the MCU singlechip U1. The load L1 may be a resistive heating load or an inductive rotating load.
In an optional implementation manner, the NMOS transistor Q2 is turned on when the first control end of the MCU single chip microcomputer U1 is at a high level, the PMOS transistor Q1 is turned on when the second control end of the MCU single chip microcomputer U1 is at a low level, and the load L1 is turned on when the NMOS transistor Q2 and the PMOS transistor Q1 are turned on simultaneously. The first control end and the second control end may be different I/O ports, for example, 3 pins and 4 pins of the MCU single-chip microcomputer U1, respectively.
Further, the load control circuit further comprises an NPN triode Q3, a first resistor R1, a second resistor R2 and a third resistor R3; the base electrode of the NPN triode Q3 is connected with the first control end through a sixth resistor R6 and is grounded through the first resistor R1; the emitter of the NPN triode Q3 is connected with the grid electrode of the NMOS tube Q2 and is grounded through the second resistor R2; the collector electrode of the NPN triode Q3 is connected with VCC; the grid electrode of the PMOS tube Q1 is connected with the second control end through a seventh resistor R7 and is also connected with VCC through a third resistor R3.
In this embodiment, the NMOS transistor Q2 and the PMOS transistor Q1 are connected in series, and the NMOS transistor Q2 and the PMOS transistor Q1 are controlled by different levels of different control ends: the NMOS tube Q2 is connected with the PMOS tube Q1 in series, one MOS tube fails to be conducted, the other MOS tube can control the load L1 to be switched on, the NMOS tube Q2 and the PMOS tube Q1 are respectively controlled by different levels of two different control ends, and if the MCU is dead or out of control (for example, the levels of the two control ends are the same), the load L1 cannot be conducted.
In an optional implementation manner, the MCU single chip microcomputer U1 further detects, through a level detection end, whether the NMOS transistor Q2 fails to be turned on or not and whether the PMOS transistor Q1 fails to be turned on or not in the non-working state of the load L1. The level detection end may be another I/O port, for example, 5 pins of the MCU single chip microcomputer U1.
Further, the source electrode of the NMOS transistor Q2 is connected to the source electrode of the PMOS transistor Q1, and the drain electrode of the PMOS transistor Q1 is grounded through the fifth resistor R5; the source of the NMOS tube Q2 is connected with the level detection end through an eighth resistor R8, and is also connected with the detection control end of the MCU singlechip U1 through a ninth resistor R9, and the detection control end is set to output high level, output low level or input.
The detection control end may be another I/O port, for example, 6 pins of the MCU single chip microcomputer U1.
In this embodiment, if the PMOS transistor Q1 fails to be turned on, the level detection terminal will detect a low level, and if the NMOS transistor Q2 fails to be turned on, the level detection terminal will detect a high level.
In an optional implementation manner, the MCU single chip microcomputer U1 further detects whether the load L1 is turned on or not through a voltage detection end. The voltage detection end can be an A/D port, for example, 7 pins of the MCU singlechip U1.
Further, the load control circuit further includes a fourth resistor R4, the non-grounded end of the fifth resistor R5 is connected to the voltage detection end through the fourth resistor R4, and the voltage detection end is further grounded to GND through a capacitor C5.
In this embodiment, by detecting whether the voltage detection terminal has a voltage, it can be determined whether the load L1 is turned on.
In an optional implementation manner, the third control end of the MCU singlechip U1 is connected with the alarm B1 through a tenth resistor R10. The third control end may be another I/O port, for example, 8 pins of the MCU single chip microcomputer U1.
Further, the third control end controls the alarm to send out an alarm when any one of the following conditions occurs:
in the non-working state of the load L1, the NMOS tube Q2 fails to be conducted;
under the non-working state of the load L1, the PMOS tube Q1 is in failure conduction;
and in the non-working state of the load L1, the MCU singlechip U1 detects that the voltage of the fifth resistor R5 is not 0.
Wherein, the alarm B1 may be an acousto-optic device. One end of the acousto-optic device is connected with VCC, and the other end of the acousto-optic device is connected with the third control end through the tenth resistor.
In this embodiment, the circuit has triple protection alarm, and under the non-operating condition, the load L1 can be more effectively avoided from working out of control, and the risk and hidden danger in the aspect of safety to the user are prevented.
The following describes in detail the principle of a load protection alarm circuit with double MOS transistors according to the present embodiment with reference to fig. 1:
1. when driver_p is at a high level, the NPN triode is conducted, and when the grid electrode of the NMOS tube Q2 is at a high level, the NMOS tube Q2 is conducted; when driver_n is at a low level, the gate of the PMOS transistor Q1 is at a low level, and the PMOS transistor Q1 is turned on, so that the load L1 is turned on. When any one of the PMOS transistor Q1 and the NMOS transistor Q2 fails to be turned on, the other MOS transistor may control the load L1 to be turned on or off. When driver_p is at high level and driver_n is at low level, the load L1 is conducted, and if the MCU singlechip U1 is dead or out of control to enable the levels of two IO ports of the 3-pin and the 4-pin to be the same, the load L1 is not conducted.
2. In the non-working state of the load L1, if the PMOS transistor Q1 fails to be turned on, the 5 pin of the MCU singlechip U1 detects the short_chk level, and at this time, the short_chk port is provided with a pull-up resistor (such as a pull-up resistor connected to the outside of the drawing or a pull-up resistor arranged in a chip pin), that is, in the drawing, the 6 pin of the MCU singlechip U1 outputs a high level, vshort_chk= (r5/(r5+r9))vload, and vshort_chk is a low level because of the resistor R5> > R9. And when the 5 pins of the MCU singlechip U1 do not detect the short_chk level, no pull-up resistor is arranged, namely the 6 pins are used as input.
In the non-working state of the load L1, if the NMOS transistor Q2 fails to be turned on, the 5 pin of the MCU singlechip U1 detects the short_chk level, and at this time, the short_chk port sets a pull-down resistor (such as a pull-down resistor externally connected to a drawing or a pull-down resistor in a chip pin is set), that is, in the drawing, the 6 pin of the MCU singlechip U1 outputs a low level, vshort_chk= (r9/(lr1+r9)) =vload, and vshort_chk is a high level because of the load resistor LR1> > R9. And when the 5 pins of the MCU singlechip U1 do not detect the short_chk level, no pull-down resistor is arranged, namely 6 pins are used as input. At this time, the user is alerted to the product failure by the audible and visual annunciator B1.
3. If the load L1 is on, vsense= (R5/(r5+lr1)) ×vload, so that it can be determined whether the load L1 is on by detecting the voltage value of Vsense. If the voltage is detected at the load L1 in the non-working state, the audible and visual device B1 alarms the user of the product failure.
In the embodiment, the NMOS tube and the PMOS tube are connected in series and controlled by different levels of different control ends; for the NMOS tube and the PMOS tube which are connected in series, judging whether the NMOS tube and the PMOS tube are in failure conduction or not by detecting the level between the NMOS tube and the PMOS tube; and for the load, judging whether the load is conducted or not by detecting the voltage value of the fifth resistor. According to the embodiment, the product faults can be accurately detected, and risks and hidden dangers in safety caused to users under the load non-working state are prevented through triple protection alarms.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the principles and spirit of the invention, but such changes and modifications fall within the scope of the invention.
Claims (8)
1. The load protection alarm circuit with the double MOS tubes is characterized by comprising an MCU (micro control unit) singlechip and a load control circuit, wherein the load control circuit comprises a load power supply, a load, an NMOS (N-channel metal oxide semiconductor) tube, a PMOS (P-channel metal oxide semiconductor) tube and a fifth resistor;
the load power supply, the load, the NMOS tube, the PMOS tube and the fifth resistor are sequentially connected in series to be grounded, the NMOS tube and the PMOS tube are controlled by different levels of different control ends of the MCU singlechip, and the MCU singlechip also detects the level between the NMOS tube and the PMOS tube and the voltage value of the fifth resistor;
the NMOS tube is conducted when the first control end of the MCU singlechip is at a high level, the PMOS tube is conducted when the second control end of the MCU singlechip is at a low level, and the load is conducted when the NMOS tube and the PMOS tube are conducted at the same time;
the load control circuit further comprises an NPN triode, a first resistor, a second resistor and a third resistor;
the base electrode of the NPN triode is connected with the first control end through a sixth resistor and is grounded through the first resistor; the emitter of the NPN triode is connected with the grid electrode of the NMOS tube and is grounded through the second resistor; the collector electrode of the NPN triode is connected with VCC;
and the grid electrode of the PMOS tube is connected with the second control end through a seventh resistor and is also connected with VCC through a third resistor.
2. The load protection alarm circuit of the double-MOS tube according to claim 1, wherein the MCU singlechip also detects whether the NMOS tube fails to be conducted or not and whether the PMOS tube fails to be conducted or not in the non-working state of the load through a level detection end.
3. The load protection alarm circuit of the double-MOS tube as set forth in claim 2, wherein the source electrode of the NMOS tube is connected with the source electrode of the PMOS tube, and the drain electrode of the PMOS tube is grounded through the fifth resistor;
the source electrode of the NMOS tube is connected with the level detection end through an eighth resistor, and is also connected with the detection control end of the MCU singlechip through a ninth resistor, and the detection control end is set to output high level, output low level or input.
4. The load protection alarm circuit of the double-MOS tube according to claim 1, wherein the MCU singlechip also detects whether the load is conducted or not through a voltage detection end.
5. The dual MOS transistor load protection alarm circuit of claim 4 wherein the load control circuit further comprises a fourth resistor, wherein the ungrounded terminal of the fifth resistor is connected to the voltage detection terminal through the fourth resistor, and wherein the voltage detection terminal is further connected to ground through a capacitor.
6. The load protection alarm circuit of the double-MOS tube according to claim 1, wherein the third control end of the MCU singlechip is connected with an alarm through a tenth resistor.
7. The dual MOS transistor load protection alarm circuit of claim 6, wherein the third control terminal controls the alarm to alarm when any one of:
under the non-working state of the load, the NMOS tube fails to be conducted;
under the non-working state of the load, the PMOS tube fails to be conducted;
and in the non-working state of the load, the MCU singlechip detects that the voltage of the fifth resistor is not 0.
8. The dual MOS transistor load protection alarm circuit of claim 1, wherein the load is a resistive heating load or an inductive rotating load.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210889477.4A CN115116206B (en) | 2022-07-27 | 2022-07-27 | Load protection alarm circuit of double MOS tube |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210889477.4A CN115116206B (en) | 2022-07-27 | 2022-07-27 | Load protection alarm circuit of double MOS tube |
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| Publication Number | Publication Date |
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| CN115116206A CN115116206A (en) | 2022-09-27 |
| CN115116206B true CN115116206B (en) | 2024-01-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202210889477.4A Active CN115116206B (en) | 2022-07-27 | 2022-07-27 | Load protection alarm circuit of double MOS tube |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009247072A (en) * | 2008-03-29 | 2009-10-22 | Shindengen Electric Mfg Co Ltd | Abnormality detection protection circuit, method, and program |
| CN211630111U (en) * | 2020-02-24 | 2020-10-02 | 九阳股份有限公司 | Food processing machine with multiple semiconductor switches and motor |
| CN213371541U (en) * | 2020-07-30 | 2021-06-08 | 杭州九阳小家电有限公司 | Safety protection circuit and food preparation machine |
| CN213849978U (en) * | 2020-09-27 | 2021-08-03 | 九阳股份有限公司 | Food processing machine |
| CN214314566U (en) * | 2021-02-04 | 2021-09-28 | 深圳市超力源科技有限公司 | MOS (metal oxide semiconductor) tube protection circuit for load short-circuit detection |
| CN216390833U (en) * | 2021-12-09 | 2022-04-26 | 青岛建邦汽车科技股份有限公司 | Emergency motor drive circuit |
-
2022
- 2022-07-27 CN CN202210889477.4A patent/CN115116206B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009247072A (en) * | 2008-03-29 | 2009-10-22 | Shindengen Electric Mfg Co Ltd | Abnormality detection protection circuit, method, and program |
| CN211630111U (en) * | 2020-02-24 | 2020-10-02 | 九阳股份有限公司 | Food processing machine with multiple semiconductor switches and motor |
| CN213371541U (en) * | 2020-07-30 | 2021-06-08 | 杭州九阳小家电有限公司 | Safety protection circuit and food preparation machine |
| CN213849978U (en) * | 2020-09-27 | 2021-08-03 | 九阳股份有限公司 | Food processing machine |
| CN214314566U (en) * | 2021-02-04 | 2021-09-28 | 深圳市超力源科技有限公司 | MOS (metal oxide semiconductor) tube protection circuit for load short-circuit detection |
| CN216390833U (en) * | 2021-12-09 | 2022-04-26 | 青岛建邦汽车科技股份有限公司 | Emergency motor drive circuit |
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