CN115114877B - Wiring method and system of FPGA chip - Google Patents
Wiring method and system of FPGA chip Download PDFInfo
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- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
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Abstract
The application relates to the field of integrated circuits and discloses a wiring method and a wiring system of an FPGA chip. The method comprises the following steps: initial wiring is carried out on the FPGA chip, and the time sequence allowance of each wire net is calculated; determining that resource conflict exists in the initial wiring result; dividing the areas with resource conflict, calculating the congestion coefficient of each divided area, and adjusting the areas with the congestion coefficient higher than a preset threshold so that the congestion coefficient of each area is lower than the preset threshold; and sequentially rewiring all the removed nets in each adjusted area according to the principle of the net with the minimum priority wiring time sequence allowance, wherein N nets with the maximum time sequence allowance passing through the congestion units in the area are removed before rewiring, and for the nets with resource conflict passing through the congestion units in the area, the net with the minimum time sequence allowance is reserved, and the rest nets are removed. The application not only can accelerate the convergence speed of the wiring process, but also can obtain better wire network time sequence.
Description
Technical Field
The application relates to the field of integrated circuits, in particular to a wiring technology of an FPGA chip.
Background
An FPGA (Field Programmable GATE ARRAY) chip is a programmable integrated circuit. Through the processes of logic synthesis and layout wiring, the circuit design of a user can be realized on the FPGA. Nowadays, FPGA chip scale has reached tens of millions or billions, and thus, the wiring process is challenged by severe congestion and thus prolonged wiring time. The wiring process is to map the net in the circuit design onto the wiring resources of the FPGA chip. In the wiring process, different nets may use the same wiring resource, so that a "conflict" situation occurs. The main process of wiring is to solve all the places where the conflict exists on the premise of meeting the targets such as time sequence, power consumption and the like. However, a new conflict is usually introduced when resolving the "conflict", so that one iteration process is required to resolve all the "conflict" places finally. A flow chart of an existing wiring method is shown in fig. 1, and can be divided into two stages: an initial routing stage and a conflict resolution stage. In the initial wiring stage, generally, on the premise of time sequence priority, an initial wiring result is obtained quickly without or with less consideration of resource competition. Since in most cases, the result of the initial wiring has a problem of resource conflict, the wiring process enters a stage of resolving the conflict, in this stage, it is checked whether there is a resource conflict in the initial wiring result, and if there is a resource conflict, all the involved nets are rerouted, and after the rerouting is completed, it is called as one iteration completion. And after one iteration is completed, the situation of whether the resource conflict exists or not is checked again, and if so, the next iteration process is continued until the wiring is completed when the situation of no resource conflict exists.
Therefore, the existing wiring method mainly relies on blindly trying new paths to solve the 'conflict', and for complex user circuit design, the existing wiring method may introduce a large number of new conflicts while solving the conflicts in the area with serious congestion, so that the wiring time is greatly increased, or the wiring process is difficult to converge, or the timing of the wire network cannot meet the requirement.
Disclosure of Invention
The application aims to provide a wiring method and a wiring system for an FPGA chip, which can not only accelerate the convergence rate of the wiring process, but also obtain better wire network time sequence.
The application discloses a wiring method of an FPGA chip, which comprises the following steps:
a, initial wiring is carried out on an FPGA chip, and the time sequence allowance of each wire net is calculated;
b, determining that resource conflict exists in the initial wiring result;
C, dividing the areas with resource conflict, calculating the congestion coefficient of each divided area, and adjusting the areas with the congestion coefficient higher than a preset threshold so that the congestion coefficient of each area is lower than the preset threshold;
And D, sequentially rewiring all the removed nets in each area according to the principle of the net with the minimum time sequence allowance of the preferential wiring, wherein N nets with the maximum time sequence allowance passing through the congestion units in the area are removed before rewiring, and for the nets with resource conflict passing through the congestion units in the area, reserving the net with the minimum time sequence allowance, removing other rest nets, wherein the congestion units are units with congestion coefficients larger than a preset threshold value, and N is a preset positive integer.
In a preferred embodiment, the method further comprises:
Calculating a congestion coefficient of each unit according to the number of used wiring resources and the total number of wiring resources in the unit;
According to The congestion factor of each area is calculated, wherein N t represents the number of units in the area r (i), and Congo t(c,r) represents the congestion degree of the units (c, r) in the area r (i).
In a preferred embodiment, the re-wiring further includes:
calculating the congestion influence cost of each node in each area according to the congestion coefficient of the unit and the congestion coefficient of the area;
calculating the comprehensive wiring cost of each node in each area according to the calculated congestion influence cost, the time delay influence cost and the historical influence cost;
And calculating the cost of all wiring possible paths of each dismantled wire net of each region according to the comprehensive wiring cost of each node in the region, and respectively selecting the wiring path with the minimum cost to re-wire each dismantled wire net.
In a preferred embodiment, the calculating the comprehensive wiring cost of each node in each area according to the calculated congestion influence cost and the time-delay influence cost and the history influence cost further includes:
According to a formula Cost(n)＝ωbas*Costbas(n)+ωhis*(His_Numu+f*His_Numcond)+ωcur(Numcond+h*C(Congot,Congor,Regin_Size)), the comprehensive wiring Cost of each node is calculated, wherein Cost bas (n) represents the time delay influence Cost of the node n, his_Num u represents the number of times the history of the node n is used, f and h are constants, his_Num cond represents the number of times the history of the node has competition, num cond represents the number of times the node n is currently used, C (Congo t,Congor and Regin _Size) represents the current congestion influence Cost of the node n, congo t represents the congestion coefficient of a unit where the node n is located, congo r represents the congestion coefficient of the area where the node n is located, regin _Size represents values representing the shape and the Size of the area where the node n is located, and omega bas,ωhis,ωcur respectively represents the weight of the corresponding part.
In a preferred embodiment, when the congestion coefficient is higher than the area of the predetermined threshold, the method further includes:
For areas where the congestion factor is above a predetermined threshold, one or more factors of the shape, location, size and number of the area are changed to make the adjustment.
In a preferred embodiment, the method further comprises: if there is a resource conflict in the initial routing result, performing steps C to D in an iterative manner until there is no resource conflict in the re-routing result.
The application also discloses a wiring system of the FPGA chip, which comprises:
The first wiring module is used for initially wiring the FPGA chip;
the calculation module is used for calculating the time sequence allowance of each wire net in the initial wiring result;
The area dividing and adjusting module is used for determining that resource conflict exists in an initial wiring result, dividing the areas with the resource conflict, calculating the congestion coefficient of each divided area, and adjusting the areas with the congestion coefficient higher than a preset threshold so that the congestion coefficient of each area is lower than the preset threshold;
And the second wiring module is used for sequentially rewiring all the removed nets in each area after adjustment according to the principle of the net with the minimum priority wiring time sequence allowance, wherein N nets with the maximum time sequence allowance passing through the congestion units in the area are removed before rewiring, the net with the minimum time sequence allowance is reserved for the net with the resource conflict passing through the congestion units in the area, other rest nets are removed, the congestion units are units with the congestion coefficient larger than a preset threshold value, and N is a preset positive integer.
In a preferred embodiment, the calculation module is further configured to calculate a congestion factor for each of the units based on the number of used wiring resources and the total number of wiring resources in the unit, and based on the number of used wiring resources The congestion factor of each area is calculated, wherein N t represents the number of units in the area r (i), and Congo t(c,r) represents the congestion degree of the units (c, r) in the area r (i).
In a preferred embodiment, the calculation module is further configured to calculate a congestion impact cost of each node in each area according to the congestion coefficient of the located unit and the congestion coefficient of the located area, calculate a comprehensive wiring cost of each node in each area according to the calculated congestion impact cost and the time impact cost, and calculate costs of all possible routes of each removed wire net in each area according to the comprehensive wiring cost of each node in each area; and the second wiring module is also used for respectively selecting the wiring path with the minimum cost to re-route each dismantled wire net.
In a preferred embodiment, the calculation module is further configured to calculate a comprehensive wiring Cost of each node according to a formula Cost(n)＝ωbas*Costbas(n)+ωhis*(His_Numu+f*His_Numcond)+ωcur(Numcond+h*C(Congot,Congor,Regin_Size)), where Cost bas (n) represents a delay impact Cost of the node n, his_num u represents a number of times the history of the node n is used, f, h is a constant, his_num cond represents a number of times the history of the node has a contention, num cond represents a number of times the node n is currently used, C (conno t,Congor, regin _size) represents a current congestion impact Cost of the node n, conno t represents a congestion coefficient of a unit where the node n is located, conno r represents a congestion coefficient of a region where the node n is located, regin _size represents a value representing a shape and a Size of the region where the node n is located, and ω bas,ωhis,ωcur represents weights of the corresponding portions, respectively.
The embodiment of the application at least comprises the following advantages and beneficial technical effects:
The method comprises the steps of dividing and adjusting the area with the resource conflict in the initial wiring result, removing N nets with the largest time sequence allowance passing through the congestion units in the area, reserving the net with the smallest time sequence allowance and removing the forward feedback mechanism of other rest nets for the net with the resource conflict passing through the congestion units in the area, avoiding the problem that a large number of new conflicts are introduced while the conflicts are solved by the existing method, improving the conflict resolution efficiency, improving the convergence speed of the wiring process and obtaining better net time sequence. And during the division and adjustment of the areas, the congestion state is quantized, so that the wiring process can be guided to search for a solution preferentially from the outside of the area with serious congestion, the number of invalid iterations in the area with serious congestion is reduced, and the convergence rate of the conflict is further improved. And the rerouting in all areas can be sequentially carried out by using a multithreading mode, so that the convergence rate of conflict is further improved.
In addition, the congestion state data obtained based on the quantized congestion state provides a new cost calculation model containing the real-time congestion state, and the new cost calculation model is used for guiding the wiring process, so that the conflict convergence speed is further improved, and better wire network time sequence can be obtained.
According to the embodiment of the application, in the wiring process, the division area, the cost model and the like are subjected to multi-angle adjustment according to the quantized congestion state data, so that the conflict resolution efficiency can be greatly improved, the convergence speed of the wiring process is improved, and a better wire network time sequence is obtained.
The numerous technical features described in the description of the present application are distributed among the various technical solutions, which can make the description too lengthy if all possible combinations of technical features of the present application (i.e., technical solutions) are to be listed. In order to avoid this problem, the technical features disclosed in the above summary of the application, the technical features disclosed in the following embodiments and examples, and the technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (these technical solutions are regarded as already described in the present specification) unless such a combination of technical features is technically impossible. For example, in one example, feature a+b+c is disclosed, in another example, feature a+b+d+e is disclosed, and features C and D are equivalent technical means that perform the same function, technically only by alternative use, and may not be adopted simultaneously, feature E may be technically combined with feature C, and then the solution of a+b+c+d should not be considered as already described because of technical impossibility, and the solution of a+b+c+e should be considered as already described.
Drawings
Fig. 1 is a flow chart of a prior art wiring method.
Fig. 2 is a schematic flow chart of a wiring method of an FPGA chip according to a first embodiment of the present application.
Fig. 3 is an example illustration of unit congestion and global congestion area partitioning in accordance with the present application.
Fig. 4 (a) and fig. 4 (b) are schematic diagrams of the area divided according to the present application, including the whole area where congestion is severe and the divided area where congestion is possibly all located.
Fig. 4 (c) and 4 (d) are schematic views of the regions of fig. 4 (a) and 4 (b), respectively, after adjustment according to the present application.
Fig. 5 is a flow chart of a wiring method of an FPGA chip according to an embodiment of the present application.
Fig. 6 is a schematic diagram of a wiring system structure of an FPGA chip according to a second embodiment of the present application.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be understood by those skilled in the art that the claimed application may be practiced without these specific details and with various changes and modifications from the embodiments that follow.
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
The inventors of the present application found that when wiring resources of some areas of the FPGA chip are used in large amounts, a congestion phenomenon occurs, and the higher the resource usage, the more serious the congestion. The serious congestion not only reduces the efficiency of resolving the conflict, increases the wiring time, but also can cause the failure of wiring because the conflict of the resource cannot be completely resolved. And congestion is typically located in the middle region of the chip. Then, if the real-time congestion state can be obtained and the wiring method can be adjusted according to the real-time congestion state feedback in the wiring process, the congestion degree of the subsequent wiring can be reduced, and the convergence speed of the wiring can be increased. Moreover, the reduction of the congestion level is also beneficial to the better timing of the wiring of the critical nets. Therefore, the embodiment of the application calculates the real-time congestion state data and integrates the real-time congestion state data into the wiring process, so that the wiring process is more flexible and more effective.
The first embodiment of the application relates to a wiring method of an FPGA chip, the flow of which is shown in fig. 2, and the method comprises the following steps:
in step 201: and (5) carrying out initial wiring on the FPGA chip and calculating the time sequence allowance of each wire net. For example, but not limited to, the FPGA chip may be initially routed on the premise of time-series priority, and the initial routing result may be obtained quickly without or with less consideration to resource contention.
Thereafter, step 202 is entered: and determining that resource conflict exists in the initial wiring result. In another embodiment, the wiring method further comprises the steps of: and determining that no resource conflict exists in the initial wiring result, and ending the wiring.
Then, step 203 is entered, where the areas where there are resource conflicts are divided into areas, and the congestion coefficient of each divided area is calculated, and the areas where the congestion coefficient is higher than the predetermined threshold are adjusted so that the congestion coefficient of each area is lower than the predetermined threshold.
The manner of initially dividing the area where there is a resource conflict is various. Alternatively, in one embodiment, units (i.e., congestion units) whose congestion coefficients exceed a predetermined threshold are selected, and a region of a certain size is set as a resource conflict region centering on each congestion unit. Optionally, in one embodiment, multiple regions that have partial overlap or adjacent regions may be further combined into one region (e.g., the congestion region division example shown as 302, 303 in fig. 3). Alternatively, in one embodiment, multiple congestion units with a distance less than a predetermined threshold may be directly partitioned into one area.
For a more intuitive understanding of the present embodiment, congestion can be divided into two categories, for example: unit congestion and global congestion. Global congestion data (i.e., areas of resource conflict) may be derived based on the congestion status data (e.g., calculated congestion coefficients) for each element. The congestion status data of the cell is useful for guiding the re-routing process, while the main purpose of global congestion is to confirm from a more macroscopic perspective which area of the chip is heavily congested, so the global congestion status data can provide a more macroscopic perspective to the routing process. In fig. 3, a diagram of unit congestion and global congestion is given, 301 representing unit congestion and 302, 303 representing global congestion. An example of an initial division of cells and regions is shown in fig. 3, where the rectangle shown at 302 is only one form of region division, and a quasi-circular shape such as an ellipse shown at 303 is also a very effective form, which region shape is used in relation to how congestion status data is applied during the routing process. Global congestion status data is more efficient for the wire-line convergence speed of the net across the congested area than the congestion status data of the cells.
The FPGA chip is divided into a plurality of cells in a row and column distribution, and each cell is the smallest unit (usually denoted by Tile) for calculating congestion status data in the present application. Alternatively, the congestion coefficient of each cell may be calculated from the number of wiring resources that have been used within the cell and the total number of wiring resources. In one embodiment, the formula may be based onCalculating the congestion coefficient of each unit, wherein c and r respectively represent the row number and the column number of the chip where the unit is located; nu (c,r) represents the number of resources that have been used within a cell; na (c,r) represents the number of all resources within a cell. In other embodiments, the method of calculating the congestion factor of each unit may be any variation of the above formula.
Alternatively, the congestion coefficient of each divided area may be calculated from the congestion coefficient of each unit. In one embodiment, the formula may be based onThe congestion factor for each region is calculated, where N t represents the number of cells within region r (i) and Congo t(c,r) represents the degree of congestion of cells (c, r) within region r (i). In other embodiments, the method for calculating the congestion coefficient of each area may further include adding a portion describing information such as the size, shape, and distribution of congestion status data of units in the area to the above formula.
The manner of adjustment in step 203 is varied. Alternatively, the adjustment may be, for example, but not limited to, one or more factors that change the shape, location, size, and number of the regions. For example, fig. 4 (a) to 4 (d) list several area division and adjustment results. In the case where congestion state data is not introduced, the entire area where congestion is serious is included in the divided area (fig. 4 (a)) or the divided area may be entirely located in the area where congestion is serious (fig. 4 (b)). The efficiency of the conflict convergence is low in this case of re-routing in this area. In the area division, if the current congestion state data is added, for example, the division result of fig. 4 (a) may be optimized to fig. 4 (c), and for example, the division result of fig. 4 (b) may be optimized to fig. 4 (d). Compared with the division results of fig. 4 (a) and fig. 4 (b), the division results of fig. 4 (c) and fig. 4 (d) can equally divide the influence of congestion, thereby being beneficial to reducing the subsequent congestion degree, improving the conflict convergence efficiency and accelerating the wiring speed. It should be noted that although fig. 4 (a) to 4 (d) show only the adjustment process of changing the position, it is not limited to include the adjustment of the shape, size, and number.
And then, entering a step 204, and sequentially rewiring all the removed nets in each area after adjustment according to the principle of preferentially routing the net with the smallest time sequence allowance, wherein before rewiring, removing N nets with the largest time sequence allowance passing through the congestion units in the area, and for the nets with resource conflict passing through the congestion units in the area, reserving the net with the smallest time sequence allowance, removing other rest nets, wherein the congestion units are units with congestion coefficients larger than a preset threshold value, and N is a preset positive integer. When a resource within a cell is simultaneously used by multiple nets, the multiple nets are referred to as nets that have resource conflicts across the cell.
In one embodiment, for each area after adjustment, the cost of the possible routing paths of each removed wire net of the area is calculated according to the congestion coefficient of each unit and the congestion coefficient of each area, and the routing paths with the minimum cost are selected to re-route each removed wire net.
Each wiring resource is called a node, and is denoted by node (n). In the routing process, which node is preferentially selected is determined by the Cost (Cost) of the node. Factors affecting the cost of the node are very numerous, such as latency information of the node, the current used state of the node, and the historical used state. In the invention, the congestion data of the unit (namely, tile) where the node is located and the regional congestion data where the node is located are also added into the cost calculation model. The "rewiring each area after adjustment" in step 204 is further implemented as: calculating the congestion influence cost of each node in the area according to the congestion coefficient of the unit and the congestion coefficient of the area; calculating the comprehensive wiring cost of each node in each area according to the calculated congestion influence cost, the time delay influence cost and the historical influence cost; and calculating the cost of all wiring possible paths of each dismantled wire net of each area according to the comprehensive wiring cost of each node in each area, and respectively selecting the wiring path with the minimum cost to re-wire each dismantled wire net. For example, the decomposition state of the integrated cost calculation model of the node (n) considering the congestion state data is: cost (n) =cost bas(n)+Costhis(n)+Costcur (n), where Cost bas (n) represents the basic Cost of the node, and is mainly used to reflect the effect of latency; cost his (n) represents the Cost of a node in relation to a historical wiring process, primarily to enable the wiring process to avoid selecting routes that have been tried before; cost cur (n) represents the Cost of the node in relation to the current state and thus the congestion state as part of it. The calculation models of the respective sections are described below. Cost his (n), referred to as the historical impact Cost of the node, can be quantified using the following model: Wherein ω his is generally a constant, or a value that varies with the number of iterations, in order to adjust the specific gravity of the historical information in the composite cost calculation; /(I) The number of times the node was used in a previous iteration; /(I)The number of times the node competes in the previous iteration process; f is a constant, and is generally a value between 0 and 1; it should be noted that, if the historical congestion status data needs to be considered, it may be added as a part to the historical impact cost of the node. Cost cur (n) is called the current congestion shadow Cost of the node, and can be calculated according to the number of times the node is currently used, the local congestion coefficient of the unit where the node is located, the global congestion coefficient of the congestion area where the node is located and the value representing the shape and size of the congestion area. For example, the following model may be used for quantification: cost cur(n)＝ωcur(Numcond+h*C(Congot,Congor, regin _size)), where ω cur is a constant for the purpose of adjusting the specific gravity of the current information in the integrated Cost calculation, h is a constant for adjusting the specific gravity C (conno t,Congor, regin _size) of the congestion Cost term in the current Cost is a Cost corresponding to the current congestion status data, mainly determined with the local congestion value conno t of the unit where the node is located, the global congestion value conno r of the congestion area where the node is located, and Regin _size characterizing the shape and Size of the congestion area.
In one embodiment, the comprehensive wiring Cost of each node may be calculated according to the formula Cost(n)＝ωbas*Costbas(n)+ωhis*(His_Numu+f*His_Numcond)+ωcur(Numcond+h*C(Congot,Congor,Regin_Size)), where Cost bas (n) represents the delay impact Cost of node n, his_num u represents the number of times node n is used, f, h is a constant, f generally takes a value between 0 and 1, his_num cond represents the number of times node history has competition, C (conno t,Congor, regin _size) represents the current congestion impact Cost of node n, num cond represents the number of times node n is currently used, conno t represents the congestion coefficient of the unit where node n is located, conno r represents the congestion coefficient of the area where node n is located, regin _size represents the values representing the shape and Size of the area where node n is located, ω bas,ωhis,ωcur respectively represents the weights of the corresponding parts, and the sizes of the weights may be changed accordingly according to the number of iterations. In other embodiments, the method of calculating the composite routing cost for each node may be any variation on the above formula.
Optionally, the wiring method further includes: the re-wiring in all the partitioned areas is performed by using a multithreading mode, so that the wiring process can be accelerated by using the architecture of a computer multiprocessor, the re-wiring process for processing resource conflict occurs in each partitioned area, and the net with the resource conflict in the area is removed and other wiring paths are tried to be found in the area to finish the wiring. Because if the congestion situation in the area is severe, a large number of new resource conflicts will be brought after the re-routing is completed, even if the number of conflicts will be greater than the number of previous conflicts, the re-routing process is ineffective for conflict convergence, but takes up computer processor time. In zone division, taking into account congestion data, in particular global congestion data, such inefficient rewiring processes can be avoided or reduced.
Optionally, the wiring method further includes: if there is a resource conflict in the initial routing result, performing steps C to D in an iterative manner until there is no resource conflict in the re-routing result. In the beginning stage of each iteration, congestion state data is updated and used for guiding the iteration process. Optionally, N is set differently for each iteration, for example, but not limited to, as the number of iterations increases, N is set to decrease. Optionally, N set for each iteration is the same. As shown in fig. 5, an iterative routing process of an embodiment is different from the routing method shown in fig. 1, and the routing method considering congestion status data needs to calculate current congestion data in case of determining that there is a resource conflict, the congestion data can quantify the current congestion status, update a cost calculation model and perform region division based on the congestion data, and sequentially perform rerouting in all regions by using a multithreading manner, which is called as one iteration completion after all region processing is completed. Then, whether the resource competition still exists is confirmed again, and if yes, the next round of iterative process of rewiring is carried out.
The second embodiment of the present application relates to a wiring system of an FPGA chip, which has a structure as shown in fig. 6, and includes a first wiring module, a calculation module, a region dividing and adjusting module, and a second wiring module.
The first wiring module is used for initially wiring the FPGA chip. For example, but not limited to, the first routing module rapidly obtains the initial routing result on the premise of time sequence priority without or with less consideration of resource competition.
The area division and adjustment module is used for determining that resource conflict exists in an initial wiring result, dividing the areas with the resource conflict, calculating the congestion coefficient of each divided area, and adjusting the areas with the congestion coefficient higher than a preset threshold so that the congestion coefficient of each area is lower than the preset threshold.
The area dividing and adjusting module can be used for carrying out initial division on the areas with resource conflicts in various ways. Alternatively, in one embodiment, units (i.e., congestion units) whose congestion coefficients exceed a predetermined threshold are selected, and a region of a certain size is set as a resource conflict region centering on each congestion unit. Alternatively, in one embodiment, multiple regions that partially overlap or are adjacent may be further combined into one region. Alternatively, in one embodiment, multiple congestion units with a distance less than a predetermined threshold may be directly partitioned into one area.
The area dividing and adjusting module adjusts the area with the congestion coefficient higher than the preset threshold in various ways, for example, by changing one or more factors of the shape, the position, the size and the number of the area.
In other embodiments, the area dividing and adjusting module is configured to determine that the routing is ended when there is no resource conflict in the initial routing result.
The calculation module is used for calculating the time sequence allowance of each wire net in the initial wiring result.
Optionally, the calculation module is further configured to calculate a congestion coefficient of each cell based on the number of used wiring resources and the total number of wiring resources in the cellThe congestion factor for each region is calculated, where N t represents the number of cells within region r (i) and Congo t(c,r) represents the degree of congestion of cells (c, r) within region r (i).
Optionally, the calculation module is further configured to calculate costs of all possible routing paths of each removed net of each area according to the congestion factor of each unit and the congestion factor of each area, and the second routing module is further configured to select a routing path with the smallest cost to re-route each removed net.
Optionally, the calculating module is further configured to calculate a congestion impact cost of each node in each area according to the congestion coefficient of the located unit and the congestion coefficient of the located area, calculate a comprehensive routing cost of each node in each area according to the calculated congestion impact cost and the time impact cost and the history impact cost, and calculate costs of all possible routes of each removed wire net in each area according to the comprehensive routing cost of each node in each area. And in this alternative embodiment, the second routing module is also used to individually select the least costly routing path to reroute each of the removed nets.
In one embodiment, the calculation module may calculate, for example, a comprehensive wiring Cost of each node according to a formula Cost(n)＝ωbas*Costbas(n)+ωhis*(His_Numu+f*His_Numcond)+ωcur(Numcond+h*C(Congot,Congor,Regin_Size)), where Cost bas (n) represents a delay impact Cost of the node n, his_num u represents a number of times the history of the node n is used, his_num cond represents a number of times the history of the node has a contention, num cond represents a number of times the node n is currently used, C (conno t,Congor, regin _size) represents a current congestion impact Cost of the node n, conno t represents a congestion coefficient of a unit where the node n is located, conno r represents a congestion coefficient of a region where the node n is located, regin _size represents a value representing a shape and a Size of the region where the node n is located, ω bas,ωhis,ωcur represents weights of corresponding portions, and f and h are constants, respectively.
And the second wiring module is used for sequentially rewiring all the removed nets in each area after adjustment according to the principle of preferentially wiring the net with the smallest time sequence allowance, wherein N nets with the largest time sequence allowance passing through the congestion units in the area are removed before rewiring, and for the nets with resource conflict passing through the congestion units in the area, the net with the smallest time sequence allowance is reserved, other rest nets are removed, the congestion units are units with congestion coefficients larger than a preset threshold value, and N is a preset positive integer. When a resource within a cell is simultaneously used by multiple nets, the multiple nets are referred to as nets that have resource conflicts across the cell.
Optionally, the second routing module is further configured to perform rerouting in all the partitioned areas respectively using a multithreading manner.
Optionally, the system further includes an iteration module, where the iteration module is configured to call the area dividing and adjusting module, the calculation module, and the second routing module in an iterative manner when there is a resource conflict in the initial routing result, and each iteration round executes the area dividing and adjusting module, the calculation module, and the second routing module, and update congestion status data at a stage of starting each iteration round, so as to guide the current iteration process. Optionally, N is set differently for each iteration, for example, but not limited to, as the number of iterations increases, N is set to decrease. Optionally, N set for each iteration is the same.
It is to be understood that the first embodiment is a method embodiment corresponding to the present embodiment, and the technical details in the first embodiment may be applied to the present embodiment, and the technical details in the present embodiment may also be applied to the first embodiment.
It should be noted that, those skilled in the art should understand that the implementation functions of the modules shown in the embodiments of the wiring system of the FPGA chip described above may be understood with reference to the description related to the wiring method of the FPGA chip described above. The functions of the modules shown in the above-described embodiment of the wiring system of the FPGA chip may be implemented by a program (executable instructions) running on a processor or by a specific logic circuit. The wiring system of the FPGA chip according to the embodiment of the present application may be stored in a computer-readable storage medium if implemented in the form of a software functional module and sold or used as an independent product. Based on such understanding, the technical solutions of the embodiments of the present application may be embodied in essence or a part contributing to the prior art in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read Only Memory (ROM), a magnetic disk, an optical disk, or other various media capable of storing program codes. Thus, embodiments of the application are not limited to any specific combination of hardware and software.
It should be noted that in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, and two cases are included: the act is performed solely on the basis of the element and is performed on the basis of the element and other elements. Multiple, etc. expressions include 2, 2 times, 2, and 2 or more, 2 or more times, 2 or more.
All references mentioned in this disclosure are to be considered as being included in the disclosure of the application in its entirety so that modifications may be made as necessary. Furthermore, it should be understood that the foregoing description is only of the preferred embodiments of the present application and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement, or the like, which is within the spirit and principles of one or more embodiments of the present disclosure, is intended to be included within the scope of one or more embodiments of the present disclosure.
Claims (8)
1. The wiring method of the FPGA chip is characterized by comprising the following steps of:
a, initial wiring is carried out on an FPGA chip, and the time sequence allowance of each wire net is calculated;
b, determining that resource conflict exists in the initial wiring result;
C, dividing the areas with resource conflict, calculating the congestion coefficient of each divided area, and adjusting the areas with the congestion coefficient higher than a preset threshold so that the congestion coefficient of each area is lower than the preset threshold; wherein the congestion coefficient of each unit is calculated according to the number of used wiring resources and the total number of wiring resources in the unit; according to Calculating the congestion coefficient of each area, wherein N t represents the number of units in the area r (i), and Congo t(c,r) represents the congestion degree of the units (c, r) in the area r (i);
And D, sequentially rewiring all the removed nets in each area according to the principle of the net with the minimum time sequence allowance of the preferential wiring, wherein N nets with the maximum time sequence allowance passing through the congestion units in the area are removed before rewiring, and for the nets with resource conflict passing through the congestion units in the area, reserving the net with the minimum time sequence allowance, removing other rest nets, wherein the congestion units are units with congestion coefficients larger than a preset threshold value, and N is a preset positive integer.
2. The wiring method according to claim 1, wherein when the wiring is re-routed, further comprising:
Calculating the congestion influence cost of each node in the area according to the congestion coefficient of the unit and the congestion coefficient of the area;
calculating the comprehensive wiring cost of each node in each area according to the calculated congestion influence cost, the time delay influence cost and the historical influence cost;
And calculating the cost of all wiring possible paths of each dismantled wire net of each region according to the comprehensive wiring cost of each node in each region, and respectively selecting the wiring path with the minimum cost to re-wire each dismantled wire net.
3. The routing method of claim 2, wherein calculating the composite routing cost for each node in each region based on the calculated congestion impact costs and the time-and history impact costs further comprises:
According to a formula Cost(n)＝ωbas*Costbas(n)+ωhis*(His_Numu+f*His_Numcond)+ωcur(Numcond+h*C(Congot,Congor,Regin_Size)), the comprehensive wiring Cost of each node is calculated, wherein Cost bas (n) represents the time delay influence Cost of the node n, his_Num u represents the number of times the history of the node n is used, f and h are constants, his_Num cond represents the number of times the history of the node has competition, num cond represents the number of times the node n is currently used, C (Congo t,Congor and Regin _Size) represents the current congestion influence Cost of the node n, congo t represents the congestion coefficient of a unit where the node n is located, congo r represents the congestion coefficient of the area where the node n is located, regin _Size represents values representing the shape and the Size of the area where the node n is located, and omega bas,ωhis,ωcur respectively represents the weight of the corresponding part.
4. The wiring method according to claim 1, wherein when the area where the congestion factor is higher than the predetermined threshold is adjusted, further comprising: for areas where the congestion factor is above a predetermined threshold, one or more factors of the shape, location, size and number of the area are changed to make the adjustment.
5. The wiring method according to any one of claims 1 to 4, characterized in that the method further comprises: if there is a resource conflict in the initial routing result, performing steps C to D in an iterative manner until there is no resource conflict in the re-routing result.
6. A wiring system for an FPGA chip, comprising:
The first wiring module is used for initially wiring the FPGA chip;
the calculation module is used for calculating the time sequence allowance of each wire net in the initial wiring result;
The area dividing and adjusting module is used for determining that resource conflict exists in an initial wiring result, dividing the areas with the resource conflict, calculating the congestion coefficient of each divided area, and adjusting the areas with the congestion coefficient higher than a preset threshold so that the congestion coefficient of each area is lower than the preset threshold;
The second wiring module is used for sequentially rewiring all the removed nets in each area after adjustment according to the principle of the net with the minimum priority wiring time sequence allowance, wherein N nets with the maximum time sequence allowance passing through the congestion units in the area are removed before rewiring, and for the nets with resource conflict passing through the congestion units in the area, the nets with the minimum time sequence allowance are reserved, other rest nets are removed, the congestion units are units with the congestion coefficient larger than a preset threshold value, and N is a preset positive integer;
the calculation module is also used for calculating the congestion coefficient of each unit according to the number of the used wiring resources and the total number of the wiring resources in the unit, and according to the congestion coefficient And calculating the congestion coefficient of each area, wherein Nt represents the number of units in the area r (i), and Congo t(c,r) represents the congestion degree of the units (c, r) in the area r (i).
7. The wiring system of claim 6, wherein the calculation module is further configured to calculate a congestion impact cost for each node in the each area based on the congestion coefficients of the located units and the congestion coefficients of the located areas, calculate a composite wiring cost for each node in the each area based on the calculated congestion impact cost and the time-dependent impact cost, and calculate costs for all wiring potential paths for each removed net for the each area based on the composite wiring cost for each node in the each area; and the second wiring module is also used for respectively selecting the wiring path with the minimum cost to re-route each dismantled wire net.
8. The cabling system of claim 7, wherein the calculation module is further configured to calculate the comprehensive cabling Cost of each node according to a formula Cost(n)＝ωbas*Costbas(n)+ωhis*(His_Numu+f*His_Numcond)+ωcur(Numcond+h*C(Congot,Congor,Regin_Size)), wherein Cost bas (n) represents a delay impact Cost of the node n, his_num u represents a number of times the history of the node n is used, f, h is a constant, his_num cond represents a number of times the history of the node has a contention, num cond represents a number of times the node n is currently used, C (conno t,Congor, regin _size) represents a current congestion impact Cost of the node n, conno t represents a congestion coefficient of a unit where the node n is located, conno r represents a congestion coefficient of a region where the node n is located, regin _size represents a value representing a shape and a Size of the region where the node n is located, and ω bas,ωhis,ωcur represents weights of the corresponding portions, respectively.
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