CN115102263B - Communication method for battery protection chip in cascade application - Google Patents
Communication method for battery protection chip in cascade application Download PDFInfo
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- CN115102263B CN115102263B CN202211006629.8A CN202211006629A CN115102263B CN 115102263 B CN115102263 B CN 115102263B CN 202211006629 A CN202211006629 A CN 202211006629A CN 115102263 B CN115102263 B CN 115102263B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/18—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for batteries; for accumulators
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Charge And Discharge Circuits For Batteries Or The Like (AREA)
- Protection Of Static Devices (AREA)
Abstract
The invention discloses a communication method of a battery protection chip in cascade application, which relates to the field of battery chips and comprises the following steps: step 1, detecting whether a CO/DO pin output by an MOS driving circuit has output current or not when a chip is in a normal state, and judging that the chip without the output current corresponds to a main chip when the CO/DO pin has no output current when the chip is in the normal state, otherwise, judging that the chip is a secondary chip; step 2, the cascade control unit of the main chip draws current to the CO/DO pin of the secondary chip through the CTLC/CTLD pin; step 3, controlling to close a safety detection circuit of the secondary chip so as to reduce the operation current; the invention has the beneficial effects that: when the battery protection chip is applied in cascade connection, the safety detection circuit of the main chip is reserved under the condition of not influencing the circuit safety detection of the battery, and the safety detection circuit of the circuit where the secondary chip is located is closed, so that the operation current of the circuit is reduced.
Description
Technical Field
The invention relates to the field of battery chips, in particular to a communication method of a battery protection chip in cascade application.
Background
Batteries are one of the core components of new energy, and the safety of the batteries is always concerned. In order to improve the safety of the battery, a battery protection chip is usually provided in the battery application, and the battery protection chip can monitor the charging and discharging states of the battery, and actively shut off the charging and discharging circuit when an abnormal condition is detected to prevent damage to the battery, and simultaneously prevent potential safety hazards such as fire or explosion.
In the prior art, in order to protect a battery, a single or a plurality of protection chips are usually arranged, when a multi-battery module is applied, a plurality of groups of chips are required to be arranged in order to protect the battery, the number of the chips used is large, the types are various, the chips respectively keep working, the protection chips generate large current, in addition, in the normal communication and communication process, the operation current of the chips is overlarge, the service life of the battery is shortened, meanwhile, the current of the battery is accompanied with the generation of heat, the accumulation of the heat causes potential safety hazards, and meanwhile, the service life and the reliability of the battery are reduced.
Disclosure of Invention
The present invention is directed to a communication method for a battery protection chip in cascade application, so as to solve the problems in the background art.
In order to achieve the purpose, the invention provides the following technical scheme:
a communication method of a battery protection chip in cascade application is provided, the battery protection chip comprises a control logic module, a cascade control unit, an MOS drive circuit and a safety detection circuit, the control logic module is respectively connected with the cascade control unit, the MOS drive circuit and a battery signal detection unit through signals, and the communication method is characterized by comprising the following steps:
and 3, controlling to close the safety detection circuit of the secondary chip so as to reduce the operation current.
Further, in step 2: the primary chip draws current from the CO/DO pin of the secondary chip through the CTLC/CTLD pin of the primary chip in a low frequency and low duty cycle current drawing manner.
Further, in step 2: and the control logic module judges the input voltage of the CTLC/CTLD pin input by the main chip through an input voltage judging circuit, and executes the step 3 when the input voltage is matched with the drawn current, otherwise, does not execute the step 3.
Further, the CO/DO pins of the main chip respectively output level driving MOS tubes Q2/Q1, and the MOS tubes Q2/Q1 are connected in series in a loop of the battery.
Further, the method also comprises a step 4, wherein the step 4 comprises the following steps: the control logic module of the main chip carries out safety detection on the battery through the safety detection circuit, and when the safety detection circuit detects that the battery comprises one or more of undervoltage, overvoltage, disconnection and battery nonuniformity, the main chip turns off an MOS (metal oxide semiconductor) tube Q2/Q1 connected in series in the battery pack loop through the CO/DO pin, and turns off the battery loop.
Further, the CTLC/CTLD pin of the secondary chip is floated.
Furthermore, the main chip and the secondary chip both comprise VC (VC) pin groups, the VC pin groups comprise detection pins VC1-VCn, positive and negative ends of a battery are connected between adjacent detection pins, and n is an integer greater than or equal to 2.
Further, an output buffer is arranged between the control logic module and the pin CO/DO, the output buffer comprises an NMOS tube and a PMOS tube, the D pole of the NMOS tube is connected with the D pole of the PMOS tube, the G poles of the NMOS tube and the PMOS tube are connected with the control logic module, the source electrode of the NMOS tube is connected with a power supply end, and the source electrode of the PMOS tube is grounded.
Further, step 3 is executed while the safety detection circuit of the main chip is kept working normally.
Further, the controller also comprises an overcurrent detection and short circuit detection circuit, a load detection and charger detection circuit and a temperature detection circuit which are connected with the control logic module, wherein the output of the overcurrent detection and short circuit detection circuit corresponds to a CS pin, the output of the load detection and charger detection circuit corresponds to a VM pin, the output of the temperature detection circuit corresponds to an RTC pin, when the main chip or the secondary chip detects that signals of the corresponding CS pin and the RTC pin are abnormal, the CO/DO pin output signal of the main chip is used for turning off the MOS tube Q2/Q1, and when the main chip detects that the VM pin is effective and the main chip and the secondary chip are normal, the CO/DO pin output signal of the main chip is used for turning on the MOS tube Q2/Q1.
Compared with the prior art, the invention has the beneficial effects that: the battery protection chip with the specific structure can realize cascade control of the battery module, simultaneously can reserve the safety detection circuit of the main chip under the condition of not influencing the circuit safety detection of the battery, can carry out safety detection on the battery module through the main chip to improve the safety, and simultaneously closes the safety detection circuit of the circuit where the secondary chip is positioned so as to reduce the operation current of the circuit, save electric energy, reduce heat and potential safety hazard, and improve the service life and reliability of the battery.
Drawings
FIG. 1 is a schematic diagram of a communication method of a battery protection chip in a cascade application;
FIG. 2 is a circuit diagram of a MOS transistor driving circuit;
FIG. 3 is a circuit diagram of cascade control and a low frequency and low duty cycle signal diagram;
FIG. 4 is a circuit diagram of a single application master chip;
FIG. 5 is a circuit diagram of a primary chip and a secondary chip for cascade application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments, and all other embodiments obtained by a person of ordinary skill in the art without creative efforts based on the embodiments of the present invention belong to the protection scope of the present invention.
Referring to fig. 1, a communication method of a battery protection chip in a cascade application includes a control logic module, a cascade control unit, an MOS driving circuit, and a safety detection circuit, where the control logic module is respectively in signal connection with the cascade control unit, the MOS driving circuit, and a battery signal detection unit, and includes the following steps:
and 3, controlling to close the safety detection circuit of the secondary chip so as to reduce the operation current.
In a specific embodiment: the left battery detection unit, the equalizing voltage part and the reference voltage in fig. 1 are common battery detection parts, and the invention does not relate to the innovation of the parts.
In this embodiment: alternatively, only one of the chips may be included, where the chip is a master chip that is connected in a similar manner as the master chip in a cascade application, except that the CTLC/CTLD pins are floating.
In this embodiment: referring to fig. 2 and 5, in step 2: the CO/DO pin output level of the master chip drives MOS transistor Q2/Q1. As shown in FIG. 5, MOS transistor Q2/Q1 is connected in series in the battery module loop, more specifically at the negative terminal of the series connection loop.
The CO/DO pin output level of the secondary chip is connected with the CTLC/CTLD pin of the main chip; when the chip is in a normal state (namely, the chip does not have a trigger protection state), detecting whether the CO/DO pin has output current; when no output current is detected, the main chip is judged to be a main chip, otherwise, the main chip is a secondary chip, specifically, as shown in fig. 5, the main chip is connected with an MOS transistor Q2/Q1, and because the current is in a normal state, the MOS transistor Q2/Q1 is in a closed state, and the corresponding CO/DO pin has no current and is the main chip, and in the secondary chip, because a low-frequency and low-duty-cycle pulse current exists between the main chip and the secondary chip, the current exists, so that whether the chip is the main chip or the secondary chip can be judged through whether the CO/DO pin has the output current.
In this embodiment: referring to fig. 3 and 5, in step 3, the CTLC/CTLD pin of the primary chip is connected to the CO/DO pin of the secondary chip, and the CO/DO pin is determined to be at a high level or a low level according to the voltage of the CTLC/CTLD pin.
By sampling at a low frequency and a low ratio, a sampling current I is generated CTL Does not affect the current of the CTLC/CTLD pin, and the modeThe cascade control is performed in such a way that the generated power consumption is extremely low and the operation current of the secondary chip is hardly affected.
In this embodiment: referring to fig. 5, in step 4, when the chip is in a normal state in step 4, the CO/DO pin of the main chip is connected to the MOS transistor Q2/Q1, and the operation is not triggered (the CTLC/CTLD pin draws current with low frequency and low duty ratio to have little influence on the operating current of the sub chip);
the CO/DO pin of the secondary chip detects output current (derived from current drawn by the CTLC/CTLD of the main chip); the "charging overcurrent detection/discharging overcurrent detection/short circuit detection/load detection/charger detection" is turned off to reduce the operation current.
The secondary chip has current flowing through the pins at four positions of CO, DO, CTLC and CTLD, so as to drive the output current of CS and VM to be cut off, and the charging overcurrent detection/discharging overcurrent detection/short circuit detection/load detection/charger detection is turned off, thereby reducing the operation current.
In this embodiment: referring to fig. 4, in a single application, the CO pin of the main chip U1 is connected to the D pole of the PMOS transistor V1 and the D pole of the NMOS transistor W1, the DO pin of the main chip U1 is connected to the D pole of the PMOS transistor V2 and the D pole of the NMOS transistor W2, the S pole of the PMOS transistor V1 and the S pole of the PMOS transistor V2 are connected to the voltage regulator circuit, the S pole of the NMOS transistor W1 and the S pole of the NMOS transistor W2 are connected to the negative electrode of the power supply, the CTLC pin and the CTLD pin of the main chip U1 are connected to the ground, the CO pin of the chip U1 is connected to the G pole of the NMOS transistor Q2, and the DO pin of the main chip U1 is connected to the G pole of the NMOS transistor Q1.
When the single-application chip is used, the CTLC pin and the CTLD pin of the main chip U1 are in floating connection, no current flows through the CO pin and the DO pin, the current flows through the pins at the four positions of the CO, the DO, the CTLC and the CTLD which are not triggered, and the CS pin and the VM pin continue to output current, so that the work of charging overcurrent detection/discharging overcurrent detection/short circuit detection/load detection/charger detection is ensured.
In this embodiment: referring to fig. 5, in the cascade application, the CO pin of the main chip U1 is connected to the G pole of the NMOS transistor Q2, the DO pin of the chip U1 is connected to the G pole of the NMOS transistor Q1, the CTLC pin of the main chip U1 is connected to the CO pin of the sub chip U2, the CTLD pin of the main chip U1 is connected to the DO pin of the sub chip U2, and the CTLC pin and the CTLD pin of the sub chip U2 are idle-connected.
In cascade application, the main chip U1 collects I at low frequency and low occupation ratio through CTLC pin and CTLD pin CTL The signal and the CO pin and the DO pin of the secondary chip U2 confirm the primary chip and the secondary chip, no current flows through the CO pin and the DO pin, current flows through the pins at the positions of CO, DO, CTLC and CTLD which are not triggered, and the CS pin and the VM pin continue to output current, so that the work of charging overcurrent detection/discharging overcurrent detection/short circuit detection/load detection/charger detection is ensured.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (5)
1. A communication method of a battery protection chip in cascade application is provided, the battery protection chip comprises a control logic module, a cascade control unit, an MOS drive circuit and a safety detection circuit, the control logic module is respectively connected with the cascade control unit, the MOS drive circuit and the safety detection circuit by signals, and the communication method is characterized by comprising the following steps:
step 1: detecting whether output current exists at a CO/DO pin output by an MOS driving circuit when the chip is in a normal state, and judging that the chip without the output current corresponds to a main chip when the chip is in the normal state and the CO/DO pin has no output current, otherwise, judging that the chip is a secondary chip;
and 2, step: the cascade control unit of the primary chip draws current for the CO/DO pin of the secondary chip through a CTLC/CTLD pin in a low-frequency and low-duty-cycle current mode; the control logic module judges the input voltage of the CTLC/CTLD pin input by the main chip through an input level judging circuit, a constant current source is connected between the CTLC/CTLD pin and a ground electrode, when the input voltage is matched with the drawing current, the step 3 is executed, otherwise, the step 3 is not executed;
and 3, step 3: the safety detection circuit of the secondary chip is closed to reduce the operation current;
and 4, step 4: the control logic module of the main chip carries out safety detection on the battery through the safety detection circuit, and when the safety detection circuit detects one or more conditions of undervoltage, overvoltage, disconnection and battery unevenness, the main chip switches off the level through the CO/DO pin to drive the MOS tube Q2/Q1 so as to cut off a battery loop;
an output buffer is arranged between the control logic module and the pin CO/DO and comprises an NMOS tube and a PMOS tube, wherein the D pole of the NMOS tube is connected with the D pole of the PMOS tube, the G poles of the NMOS tube and the PMOS tube are connected with the control logic module, the source electrode of the NMOS tube is connected with a power supply end, the source electrode of the PMOS tube is grounded, and the CTLC/CTLD pin of the secondary chip is in floating connection.
2. A communication method for a battery protection chip in cascade connection according to claim 1, wherein the CO/DO pins of the main chip respectively output level driving MOS transistors Q2/Q1, and the MOS transistors Q2/Q1 are connected in series in the loop of the battery.
3. A communication method for battery protection chips in cascade connection according to claim 1, wherein the primary chip and the secondary chip each include a VC pin set, and the VC pin set includes a plurality of detection pins VC1-VCn, and positive and negative ends of a battery are connected between adjacent detection pins, where n is an integer greater than or equal to 2.
4. A communication method for cascade application of battery protection chips as claimed in claim 1, wherein step 3 is executed while maintaining the normal operation of the safety detection circuit of the main chip.
5. The communication method of the battery protection chip in the cascade application according to claim 1, further comprising an over-current detection and short-circuit detection circuit, a load detection and charger detection circuit, and a temperature detection circuit connected to the control logic module, wherein an output of the over-current detection and short-circuit detection circuit corresponds to a CS pin, an output of the load detection and charger detection circuit corresponds to a VM pin, and an output of the temperature detection circuit corresponds to an RTC pin, when the primary chip or the secondary chip detects that signals of the CS pin and the RTC pin are abnormal, the CO/DO pin of the primary chip outputs a signal to turn off the MOS transistor Q2/Q1, and when the primary chip detects that the VM pin is valid and the primary chip and the secondary chip are normal, the CO/DO pin of the primary chip outputs a signal to turn on the MOS transistor Q2/Q1.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211006629.8A CN115102263B (en) | 2022-08-22 | 2022-08-22 | Communication method for battery protection chip in cascade application |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211006629.8A CN115102263B (en) | 2022-08-22 | 2022-08-22 | Communication method for battery protection chip in cascade application |
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| CN115102263A CN115102263A (en) | 2022-09-23 |
| CN115102263B true CN115102263B (en) | 2022-11-29 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003061252A (en) * | 1992-11-24 | 2003-02-28 | Seiko Instruments Inc | Charge/discharge control circuit and rechargeable power supply unit |
| JP2013135479A (en) * | 2011-12-24 | 2013-07-08 | Sanyo Electric Co Ltd | Threshold voltage decision method for detection circuit, overvoltage detection circuit, and battery pack |
| CN104849536A (en) * | 2015-06-11 | 2015-08-19 | 中国人民解放军国防科学技术大学 | Detection circuit for serial lithium battery pack protection chip |
| CN111403832A (en) * | 2020-03-31 | 2020-07-10 | 点晶微(厦门)集成电路有限公司 | Extensible battery protection method |
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2022
- 2022-08-22 CN CN202211006629.8A patent/CN115102263B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003061252A (en) * | 1992-11-24 | 2003-02-28 | Seiko Instruments Inc | Charge/discharge control circuit and rechargeable power supply unit |
| JP2013135479A (en) * | 2011-12-24 | 2013-07-08 | Sanyo Electric Co Ltd | Threshold voltage decision method for detection circuit, overvoltage detection circuit, and battery pack |
| CN104849536A (en) * | 2015-06-11 | 2015-08-19 | 中国人民解放军国防科学技术大学 | Detection circuit for serial lithium battery pack protection chip |
| CN111403832A (en) * | 2020-03-31 | 2020-07-10 | 点晶微(厦门)集成电路有限公司 | Extensible battery protection method |
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| CN115102263A (en) | 2022-09-23 |
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