CN115101527A - Method for manufacturing memory device - Google Patents

Method for manufacturing memory device Download PDF

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Publication number
CN115101527A
CN115101527A CN202210759381.6A CN202210759381A CN115101527A CN 115101527 A CN115101527 A CN 115101527A CN 202210759381 A CN202210759381 A CN 202210759381A CN 115101527 A CN115101527 A CN 115101527A
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Prior art keywords
floating gate
photoresist layer
substrate
patterned photoresist
memory device
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梁肖
贾雪梅
郭楠
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Priority to CN202210759381.6A priority Critical patent/CN115101527A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

The invention provides a manufacturing method of a memory device, which comprises the following steps: providing a substrate, wherein the substrate comprises a storage area and a logic area; forming a first side wall and a first floating gate in the logic area; forming a graphical photoresist layer to cover the storage region; detecting whether the patterned photoresist layer is qualified or not, performing a rework process on the unqualified patterned photoresist layer, and removing the patterned photoresist layer by adopting a first wet process when the rework process is performed, wherein the process temperature of the first wet process is lower than or equal to 150 ℃. In the invention, the unqualified patterned photoresist layer is removed by adopting a first wet process, the process temperature is less than or equal to 150 ℃, and the unqualified photoresist layer is removed at a lower temperature relative to the ashing process so as to reduce the oxidation of the floating gate polysilicon layer of the logic region, thereby indirectly increasing the etching window of the first floating gate of the logic region, facilitating the subsequent etching to remove the first floating gate of the logic region and further solving the floating gate residue problem of the logic region.

Description

Method for manufacturing memory device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a storage device.
Background
At present, a Flash memory (Flash memory), also called Flash memory, has become the mainstream of a non-volatile memory, and a memory cell of the Flash memory is formed by adding a Floating Gate (FG) and a Tunnel Oxide (Tunnel Oxide) on the basis of a conventional MOS transistor structure, and storing charges by using the Floating Gate to realize non-volatility of stored contents. The flash memory is provided with a Shallow Trench Isolation (STI) structure to achieve Isolation between and within the memory region and the logic region, thereby most effectively utilizing the line width of the active region and improving the integration level.
After the polysilicon floating gate is formed in the storage region of the memory device by etching, the polysilicon floating gate in the logic region needs to be removed completely (floating gate suspended beam). However, when the polysilicon floating gate on the sidewall of the shallow trench isolation structure in the logic region is removed, it is difficult to remove the polysilicon floating gate cleanly, which causes the problem of polysilicon floating gate residue, thereby affecting the product yield.
Disclosure of Invention
The invention aims to provide a manufacturing method of a memory device, which aims to solve the floating gate residue problem of a logic area.
In order to solve the above technical problem, the present invention provides a method for manufacturing a memory device, including:
providing a substrate, wherein the substrate comprises a storage region and a logic region, floating gate polycrystalline silicon layers and side wall material layers are arranged on the storage region and the logic region, and the logic region is provided with a shallow trench isolation structure;
forming a first side wall and a first floating gate in the logic area, and forming a second side wall and a second floating gate in the storage area, wherein the first side wall and the first floating gate are positioned on the side wall of the shallow trench isolation structure of the logic area;
forming a graphical photoresist layer to cover the storage region;
detecting whether the patterned photoresist layer is qualified or not, and performing a rework process on the unqualified patterned photoresist layer, wherein the rework process comprises the step of removing the unqualified patterned photoresist layer by adopting a first wet process, and the process temperature of the first wet process is lower than or equal to 150 ℃; and the number of the first and second groups,
and sequentially removing the first floating gate, the first side wall and the patterned photoresist layer.
Optionally, when the second sidewall, the second floating gate, the first sidewall and the first floating gate are formed by etching, a polymer is formed on the surfaces of the substrate, the first sidewall and the second sidewall, and the polymer is removed by a second wet process, where a process temperature of the second wet process is lower than or equal to 150 ℃.
Optionally, the etching solution of the second wet process package includes an SPM solution, and the process temperature of the second wet process is 80-150 ℃.
Optionally, the side wall material layer includes a silicon oxide-silicon nitride-silicon oxide structure.
Optionally, the first wet process includes removing the unqualified patterned photoresist layer by using a photoresist thinner.
Optionally, the step of removing the unqualified patterned photoresist layer by using the photoresist thinner includes: placing the substrate on a vacuum chuck of a spin coating device; spraying the photoresist thinner on the surface of the substrate; stopping spraying the photoresist thinner, and spin-drying the substrate; and taking the substrate out of the spin coating equipment.
Optionally, the time for spraying the photoresist thinner is 60 seconds to 300 seconds.
Optionally, after removing the unqualified patterned photoresist layer, performing a wet cleaning process on the substrate, and reforming the patterned photoresist layer on the substrate.
Optionally, the patterned photoresist layer is used as a mask, and isotropic dry etching is used to remove the first floating gate.
Optionally, the memory device is a split gate flash memory device.
In summary, the first wet process is adopted to remove the unqualified patterned photoresist layer, and the process temperature in time for executing the first wet process is less than or equal to 150 ℃, so that the oxidation of the floating gate polysilicon layer of the logic region is reduced by removing the unqualified photoresist layer at a lower temperature relative to the ashing process, thereby indirectly increasing the etching window of the second floating gate of the logic region, facilitating the subsequent etching to remove the first floating gate of the logic region, and solving the floating gate residue problem of the logic region.
Drawings
It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation to the scope of the invention.
FIGS. 1a to 1c are schematic views illustrating the formation of floating gate polysilicon residue in the logic region;
fig. 2 is a flowchart of a method for manufacturing a memory device according to an embodiment of the present application;
fig. 3a to fig. 3f are schematic structural diagrams corresponding to respective steps of a method for manufacturing a memory device according to an embodiment of the present application.
In fig. 1a to 1 c:
10' -a substrate; 10 a' -storage region; 10 b' -logic region; 21' -shallow trench isolation structures; 31' -a floating gate; 32' -side walls; 33' -polymer residue; 35' -thick oxide layer; 36' -etching the window; 37' -floating gate polysilicon residue.
In fig. 3a to 3 f:
10-a substrate; 10 a-a storage area; 10 b-logical area; 21-shallow trench isolation structures; 22-a storage unit; 23-floating gate polysilicon layer; 24-a side wall material layer;
31-a first floating gate; 32-a first side wall; 33-a polymer; 34-a second floating gate; 35-a second side wall; 36-etching the window; 40-a patterned photoresist layer.
Detailed Description
The inventors experimentally found that, as shown in fig. 1a, the sidewall 32 ' and the floating gate 31 ' located on the sidewall of the shallow trench isolation structure 21 ' are formed in the logic region 10b ' by using dry etching, and at the same time, the polymer 33 ' generated by the dry etching is removed by performing an ashing process, as shown in fig. 1b, wherein the floating gate 31 ' exposed by the dry etching is oxidized more (the thickness of the oxide layer is increased) in the ashing process (e.g., 200-300 ℃), i.e., a thick oxide layer 35 ' (the thickness is about 6 angstroms, for example) is generated in the etching window 36 ' for etching the floating gate 31 ', as shown in fig. 1c, when the floating gate 31 ' is etched and removed by using a patterned photoresist layer as a mask, the etching window 36 ' for the first floating gate 31 ' is reduced due to the thick oxide layer 35 ', which is not beneficial for removing the floating gate 31 ' in the logic region 10b '.
In particular, if the formed patterned photoresist layer is not detected to be acceptable, the rework process will also be performed on the unacceptable patterned photoresist layer. The rework process may include an ashing process to remove the failed patterned photoresist layer, and the floating gate 31 ' of the logic region 10b ' will be further oxidized in the ashing process (e.g., the thick oxide layer 35 ' is thickened to 8 angstroms in thickness), resulting in the floating gate 31 ' being difficult to remove, thereby forming a floating gate polysilicon residue 37 '.
Based on the research, the invention provides a manufacturing method of a memory device, which adopts a first wet process to remove the unqualified patterned photoresist layer, and the timely process temperature for executing the first wet process is less than or equal to 150 ℃, so that the oxidation of the floating gate polysilicon layer of the logic region is reduced by removing the unqualified photoresist layer at a lower temperature relative to the ashing process, the etching window of the first floating gate of the logic region is indirectly increased, the subsequent etching is facilitated to remove the first floating gate of the logic region, and the floating gate residue problem of the logic region is solved.
To further clarify the objects, advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is to be noted that the drawings are in greatly simplified form and are not to scale, but are merely intended to facilitate and clarify the explanation of the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
As used in this disclosure, the singular forms "a," "an," and "the" include plural referents, the term "or" is generally employed in a sense including "and/or," the terms "a," "an," and "the" are generally employed in a sense including "at least one," the terms "at least two" are generally employed in a sense including "two or more," and further, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to imply that the number of indicated technical features is essential. Thus, features defined as "first," "second," and "third" may explicitly or implicitly include one or at least two of the features unless the content clearly dictates otherwise.
Fig. 2 is a flowchart of a method for manufacturing a memory device according to an embodiment of the present application.
As shown in fig. 2, the method for manufacturing a memory device according to the present embodiment includes:
s01: providing a substrate, wherein the substrate comprises a storage region and a logic region, floating gate polycrystalline silicon layers and side wall material layers are arranged on the storage region and the logic region, and the logic region is provided with a shallow trench isolation structure;
s02: forming a first side wall and a first floating gate in the logic area, and forming a second side wall and a second floating gate in the storage area, wherein the first side wall and the first floating gate are positioned on the side wall of the shallow trench isolation structure of the logic area;
s03: forming a graphical photoresist layer to cover the storage region;
s04: detecting whether the patterned photoresist layer is qualified or not, and performing a rework process on the unqualified patterned photoresist layer, wherein the rework process comprises the step of removing the unqualified patterned photoresist layer by adopting a first wet process, and the process temperature of the first wet process is lower than or equal to 150 ℃; and (c) a second step of,
s05: and sequentially removing the first floating gate, the first side wall and the patterned photoresist layer.
Fig. 3a to 3f are schematic structural diagrams corresponding to respective steps of a method for manufacturing a memory device provided in this embodiment, and next, the method for manufacturing the memory device will be described in detail with reference to fig. 3a to 3 f.
Referring to fig. 3a, step S01 is executed to provide a substrate 10, where the substrate 10 includes a storage region 10a and a logic region 10b, floating gate polysilicon layer 23 and spacer material layer 24 are disposed on the storage region 10a and the logic region 10b, and the logic region 10b is disposed with a shallow trench isolation structure 21.
The substrate 10 may be any suitable semiconductor substrate 10, such as a silicon-based semiconductor. The substrate 10 includes a plurality of memory areas 10a for forming memory cells 22 thereon and a plurality of logic areas 10b, the logic areas 10b being located between the memory areas 10a for forming logic cells (not shown) on the logic areas 10 b. The logic region 10b has a plurality of active regions, shallow trench isolation structures 21(STI) are disposed between the active regions, the shallow trench isolation structures 21 protrude from the surface of the substrate 10, and the shallow trench isolation structures 21 are used to isolate adjacent active regions; the memory unit 22 may be any suitable type of memory unit.
Specifically, the memory device in the present embodiment may be a split gate flash memory, and the forming process thereof may be, for example: firstly, a floating gate dielectric layer (not shown), a floating gate polysilicon layer 23, a control gate dielectric layer (not shown) and a control gate polysilicon layer (not shown) are sequentially formed on the surface of the substrate 10 from bottom to top, then, a memory cell 22 is formed in the above multilayer structure of the storage region 10a, the memory cell 22 protrudes out of the surface of the substrate 10, the floating gate polysilicon layer 23 is located at the bottom of the memory cell 22, and then, a sidewall material layer 24 is formed to cover the surface of the substrate 10, the outer wall of the memory cell 22 and the outer wall of the shallow trench isolation structure 21. The spacer material layer 24 may be, for example, a silicon oxide-silicon nitride-silicon oxide structure (ONO structure).
Referring to fig. 3b and fig. 3c, step S02 is executed to form a first sidewall 32 and a first floating gate 31 in the logic region 10b, and form a second sidewall 34 and a second floating gate 35 in the storage region 10a, where the first sidewall 32 and the first floating gate 31 are located on the sidewall of the shallow trench isolation structure 21 in the logic region 10 b.
The specific forming steps may include, for example: first, as shown in fig. 3b, a suitable dry etching process may be selected according to the type of the sidewall material layer 24 to perform dry etching along a direction perpendicular to the surface of the substrate 10 until the sidewall material layer 24 on the substrate 10, the memory unit 22, and the shallow trench isolation structure 21 is removed, and the sidewall material layer 24 remaining on the sidewall of the memory unit 22 is used as the second sidewall 35, and the sidewall material layer 24 remaining on the sidewall of the shallow trench isolation structure 21 is used as the first sidewall 32. Then, using the memory cell 22, the first sidewall 32 and the second sidewall 35 as masks, dry etching is performed on the floating gate polysilicon layer 23 along the surface perpendicular to the substrate 10, and the floating gate polysilicon layer 23 remaining under the memory cell 22 and the second sidewall 35 is used as the second floating gate 34, i.e., the floating gate of the memory cell 22, the floating gate polysilicon layer 23 remaining under the first sidewall 32 is used as the first floating gate 31, the side of the first floating gate 31 away from the shallow trench isolation structure 21 is used as a subsequent etching window 36, and the etching window 36 is exposed to the outside. The polymer 33 generated by dry etching the sidewall material layer 24 and the floating gate polysilicon layer 23 is attached to the surface of the substrate 10 and the outer walls of the first sidewall 32 and the second sidewall 35.
Next, as shown in fig. 3c, a second wet process is performed to remove the polymer 33, and the process temperature of the second wet process is lower than or equal to 150 ℃. A corresponding wet process may be selected to remove the polymer according to the kind of the polymer, and then a wet cleaning process may be performed to clean the surface of the substrate 10. With the etching gas comprising CH 2 F 2 For example, the polymer 33 includes a silicon-carbon fluorine-oxygen polymer (organic polymer), the solution of the second wet process may be an SPM solution, and the ratio of the SPM solution may be, for example, sulfuric acid: hydrogen peroxide: the process temperature of the SPM solution may be 80-150 deg.c, with water being 4:1: 1. The wet clean process may comprise any suitable clean process in an RCA clean step.
Compared with the high-temperature ashing process (the process temperature is higher than 250 ℃ for example), the second wet process is used for removing the polymer, so that the process temperature is lower, the oxidation of the first floating gate 31 in the etching window 36 is reduced, and the cleanness of the surface of the substrate 10 can be improved by two times of cleaning. It is understood that the lower the temperature of the second wet process is, the better the effect of reducing the oxidation of the first floating gate 31 is, while ensuring the removal effect and removal efficiency of the polymer 33 by the second wet process.
Next, referring to fig. 3d, step S03 is executed to form a patterned photoresist layer 40, wherein the patterned photoresist layer 40 covers the storage area 10 a.
The patterned photoresist layer 40 covers the memory region 10a and exposes the logic region 10b, and the patterned photoresist layer 40 has a thickness greater than the height of the memory cell 22 on the substrate 10, i.e. the patterned photoresist layer 40 completely covers the structural unit on the memory region 10a for protecting the memory region 10a in the subsequent etching process.
Next, step S05 is executed, the patterned photoresist layer 40 is detected, and if the patterned photoresist layer 40 is determined to be unqualified, a rework process is executed on the unqualified patterned photoresist layer 40, where the rework process includes removing the unqualified patterned photoresist layer 40 by using a first wet process, and the temperature when the first wet process is executed is lower than or equal to 150 ℃.
Specifically, the formed patterned photoresist layer 40 may be subjected to critical dimension detection and appearance defect detection to determine whether the patterned photoresist layer 40 meets the process requirements, if both meet the process requirements (pass), the substrate 10 may enter the next process, and if not, the unqualified patterned photoresist layer 40 may be subjected to rework process.
Wherein, the rework process performed on the failed patterned photoresist layer 40 includes: first, a first wet process is used to remove the unqualified patterned photoresist layer 40, then a wet cleaning process is performed on the substrate 10, and then the patterned photoresist layer 40 is formed again in the storage region 10a of the substrate 10. Of course, the detection step can be performed again on the reformed patterned photoresist layer 40.
Preferably, the second wet process may include removing the defective patterned photoresist layer 40 using a photoresist thinner. The specific steps may include, for example:
s051: placing the substrate 10 on a vacuum chuck of a spin coating apparatus;
s052: spraying a photoresist diluent on the surface of the substrate 10;
s053: stopping spraying the photoresist thinner and spin-drying the substrate 10;
s054: the substrate 10 is taken out of the spin coating apparatus.
In step S052, the substrate 10 may be rotated at a low speed, and a photoresist thinner may be sprayed from a central region of the surface of the substrate 10 to an edge region of the surface of the substrate 10, so that the photoresist thinner is uniformly coated on the surface of the substrate 10, thereby dissolving the unqualified patterned photoresist layer 40. The photoresist thinner can comprise one or two of propylene glycol methyl ether, propylene glycol methyl acetate, OK73 thinner, cyclohexanone and v-butyrolactone, and the rotating speed of the low-speed rotating substrate 10 can be 100 rpm-500 rpm. In addition, the temperature of the sprayed photoresist thinner can be increased to 50 ℃ to 80 ℃ to improve the above-mentioned dissolution effect (etching effect) under the condition of better controlling the oxidation of the first floating gate 32.
In step S053, the photoresist thinner is sprayed for 60 seconds to 300 seconds, and after the spraying of the photoresist thinner is stopped, the substrate 10 may be rotated at a high speed so as to spin-dry the photoresist and the photoresist thinner dissolved on the surface of the substrate 10.
It should be noted that the solution of the first wet process may also be other solutions that can remove the photoresist below 150 ℃ and are less harmful to the substrate 10, such as a weak alkaline photoresist stripping solution. Compared with the high-temperature ashing process (at a temperature greater than 250 ℃, for example), the first wet process is used to remove the unqualified patterned photoresist layer 40, and the oxidation of the first floating gate 31 of the etching window 36 can be reduced by using the lower process temperature, which is beneficial to the subsequent removal of the first floating gate 31.
Referring to fig. 3e, step S05 is executed to remove the first floating gate 31 in the logic region 10b by using the patterned photoresist layer 40 as a mask and an isotropic dry etching, which may be a reactive ion etching including fluorocarbon gas, through the etching window 36 to etch the first floating gate 31 until the first floating gate 31 is completely removed and the lower portion of the first sidewall 32 is suspended for subsequent removal of the first sidewall 32.
Next, referring to fig. 3f, the first sidewalls 32 and the patterned photoresist layer 40 are sequentially removed.
Specifically, the first sidewall 32 may be removed by a wet cleaning process including ultrasonic cleaning, and wet cleaning may be performed on the substrate 10; next, the patterned photoresist layer 40 may be removed by an ashing process or a wet process.
Of course, the manufacturing method of the memory device exemplified in this embodiment further includes other subsequent process processes, and in other embodiments of the present application, other corresponding process steps are also included, but the steps are formed by methods commonly used in the art, and are not described herein again.
In summary, the first wet process is adopted to remove the unqualified patterned photoresist layer, and the process temperature in time for executing the first wet process is less than or equal to 150 ℃, so that the oxidation of the floating gate polysilicon layer of the logic region is reduced by removing the unqualified photoresist layer at a lower temperature relative to the ashing process, thereby indirectly increasing the etching window of the first floating gate of the logic region, facilitating the subsequent etching to remove the first floating gate of the logic region, and solving the floating gate residue problem of the logic region.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (10)

1. A method of manufacturing a memory device, comprising:
providing a substrate, wherein the substrate comprises a storage region and a logic region, floating gate polycrystalline silicon layers and side wall material layers are arranged on the storage region and the logic region, and the logic region is provided with a shallow trench isolation structure;
forming a first side wall and a first floating gate in the logic area, and forming a second side wall and a second floating gate in the storage area, wherein the first side wall and the first floating gate are positioned on the side wall of the shallow trench isolation structure of the logic area;
forming a graphical photoresist layer to cover the storage region;
detecting whether the patterned photoresist layer is qualified or not, and performing a rework process on the unqualified patterned photoresist layer, wherein the rework process comprises the step of removing the unqualified patterned photoresist layer by adopting a first wet process, and the process temperature of the first wet process is lower than or equal to 150 ℃; and the number of the first and second groups,
and sequentially removing the first floating gate, the first side wall and the patterned photoresist layer.
2. The method of claim 1, wherein a polymer is formed on the surfaces of the substrate, the first sidewall and the second sidewall when the second sidewall, the second floating gate, the first sidewall and the first floating gate are formed by etching, and a second wet process is used to remove the polymer, wherein a process temperature of the second wet process is lower than or equal to 150 ℃.
3. The method of claim 2, wherein the etching solution of the second wet process package comprises an SPM solution, and the process temperature of the second wet process is 80-150 ℃.
4. The method of claim 1, wherein the spacer material layer comprises a silicon oxide-silicon nitride-silicon oxide structure.
5. The method of claim 1, wherein the first wet process comprises removing the failed patterned photoresist layer using a photoresist thinner.
6. The method of manufacturing a memory device of claim 5, wherein the step of removing the failed patterned photoresist layer using the photoresist thinner comprises: placing the substrate on a vacuum chuck of a spin coating device; spraying the photoresist thinner on the surface of the substrate; stopping spraying the photoresist thinner, and spin-drying the substrate; and taking the substrate out of the spin coating equipment.
7. The method of manufacturing a memory device according to claim 6, wherein the photoresist thinner is sprayed for a time of 60 seconds to 300 seconds.
8. The method of claim 7, further comprising performing a wet clean process on the substrate after removing the failed patterned photoresist layer, and reforming the patterned photoresist layer on the substrate.
9. The method of claim 1, wherein the first floating gate is removed by isotropic dry etching using the patterned photoresist layer as a mask.
10. The method for manufacturing a memory device according to any one of claims 1 to 9, wherein the memory device is a split gate flash memory device.
CN202210759381.6A 2022-06-29 2022-06-29 Method for manufacturing memory device Pending CN115101527A (en)

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CN202210759381.6A CN115101527A (en) 2022-06-29 2022-06-29 Method for manufacturing memory device

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Application Number Priority Date Filing Date Title
CN202210759381.6A CN115101527A (en) 2022-06-29 2022-06-29 Method for manufacturing memory device

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CN115101527A true CN115101527A (en) 2022-09-23

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