CN115101021B

CN115101021B - Circuit for selecting charge sharing mode, TCON and display device

Info

Publication number: CN115101021B
Application number: CN202210742947.4A
Authority: CN
Inventors: 张好聪; 马柯; 李年
Original assignee: Qingdao Xinxin Microelectronics Technology Co Ltd
Current assignee: Qingdao Xinxin Microelectronics Technology Co Ltd
Priority date: 2022-06-27
Filing date: 2022-06-27
Publication date: 2024-03-08
Anticipated expiration: 2042-06-27
Also published as: CN115101021A

Abstract

The invention discloses a circuit for selecting a charge sharing mode, TCON and display equipment, wherein when a display picture is switched, a summation module calculates the sub-pixel summation value of sub-pixels which do not participate in charge sharing in a previous display line in a current frame aiming at each preset charge sharing mode, calculates the absolute value of the difference value of a positive sub-pixel and a negative sub-pixel, calculates the total summation value of the absolute value of the sum value and the difference value of the sub-pixels, a minimum value determination module selects the minimum total summation value, outputs the minimum summation value and an identification corresponding to the minimum summation value to a source electrode driving circuit, and the source electrode driving circuit controls the enabling of the target charge sharing mode according to the identification so as to realize charge sharing of the previous display line and the current display line. Because the target charge sharing mode is selected according to the sub-pixel value of the sub-pixel which does not participate in charge sharing, the sub-pixel value of the positive sub-pixel and the sub-pixel value of the negative sub-pixel, compared with the single charge sharing mode, the charge sharing requirement in the dynamic display of the display panel can be met, and the power consumption is reduced.

Description

Circuit for selecting charge sharing mode, TCON and display device

Technical Field

The present invention relates to the field of liquid crystal display technologies, and in particular, to a circuit for selecting a charge sharing mode, TCON, and a display device.

Background

Thin film transistor liquid crystal displays (Thin Film Transistor-Liquid Crystal Display, TFT-LCDs) are display panels that are currently in widespread use, which use thin film transistor technology to improve image quality, and, as a typical representative of active matrix liquid crystal displays, the driving circuits in TFT-LCDs are particularly important.

The timing control circuit (Time Schedule Controller, TCON) is a core circuit controlling the timing of the display panel, controlling when the scan driving circuit is activated, and providing information required for charge sharing to a Source driving (Source Driver) circuit of the TFT-LCD, the charge sharing circuit being an important part of the structure of the Source driving circuit.

However, the charge sharing mode provided by the conventional TCON is single, and in the actual driving process, the difference between the gray scale voltages of the positive and negative polarities under the high frequency effect is large, the dynamic power consumption of the driving circuit is large, and the purpose of reducing the power consumption cannot be satisfied by the single charge sharing mode.

Disclosure of Invention

The invention provides a circuit for selecting a charge sharing mode, TCON and TFT-LCD display panel, which are used for solving the problem that the power consumption cannot be reduced by using a single charge sharing mode in the prior art.

In a first aspect, an embodiment of the present invention provides a charge sharing circuit, applied to a display device, including:

a summation module, configured to calculate, for each preset charge sharing mode and each display line in a current frame image, a subpixel summation value of subpixels in a previous display line that do not participate in charge sharing in the preset charge sharing mode, and calculate an absolute value of a difference value between a positive subpixel and a negative subpixel in the previous display line, and calculate a total summation value of the subpixel summation value and the absolute value of the difference value;

the minimum value determining module is used for selecting a minimum total sum value from total sum values corresponding to a plurality of preset charge sharing modes, and outputting the minimum total sum value and an identification corresponding to the minimum total sum value to a source driving circuit of the display device so that the source driving circuit controls a target charge sharing mode to enable according to the identification, and the charge sharing of the previous display line and the current display line is performed.

In one possible implementation, the summing module includes a first computing unit, a second computing unit, and a total computing unit;

the first calculating unit is configured to select a first sub-pixel that does not participate in charge sharing from the previous display line according to the preset charge sharing mode, and calculate a sub-pixel sum of a plurality of the first sub-pixels;

The second calculating unit is configured to select a positive sub-pixel and a negative sub-pixel from the previous display row, calculate positive sub-pixel accumulated values of all positive sub-pixels and negative sub-pixel accumulated values of all negative sub-pixels, and calculate absolute values of differences between the positive sub-pixel accumulated values and the negative sub-pixel accumulated values, where the positive sub-pixel is a second sub-pixel whose pixel electrode is positive, and the negative sub-pixel is a second sub-pixel whose pixel electrode is negative;

the total calculation unit is used for calculating the total sum of the sub-pixel sum and the absolute value of the difference.

In one possible implementation, the method further comprises a comparison module;

and the comparison module is used for comparing the minimum sum value with a preset threshold value and sending the comparison result to the source electrode driving circuit so that the source electrode driving circuit can control the target charge sharing mode to be enabled according to the identification.

In one possible implementation, the comparison module includes a third comparator;

the first input end of the third comparator is used for inputting the minimum sum value and the identifier corresponding to the minimum sum value, the second input end of the third comparator is used for inputting the preset threshold value, and the output end of the third comparator is used for outputting the comparison result.

In one possible implementation, the first computing unit includes a first selector, a second selector, and a first adder;

the input end of the first selector is used for inputting the shared value stored in the mode register, the control end of the first selector is connected with the first output end of the counter, and the output end of the first selector is connected with the control end of the second selector and used for outputting the shared value stored in the mode register under the control of the first count value output by the counter;

the input end of the second selector is used for inputting sub-pixel values in a plurality of first preset combinations, the output end of the second selector is connected with the first input end of the first adder and is used for selecting one preset combination from the plurality of first preset combinations to output according to the input shared value, and the first preset combination is a combination determined according to the sub-pixel values in each pixel unit in the previous display row;

the output end of the first adder is connected with the second input end of the first adder and is used for accumulating the input sub-pixel values and outputting the sub-pixel addition value.

In one possible implementation, the second computing unit includes a third selector, a fourth selector, a fifth selector, a second adder, a third adder, a first comparator, and a subtractor;

The input end of the third selector is used for inputting the polarity value stored in the polarity register, the control end of the third selector is connected with the second output end of the counter, and the output end of the third selector is connected with the control end of the fourth selector and used for outputting the polarity value stored in the polarity register under the control of the second count value output by the counter;

the input end of the fourth selector is used for inputting a second preset combination sub-pixel value, the first output end of the fourth selector is connected with the first input end of the second adder, the second output end of the fourth selector is connected with the first input end of the third adder, and the input end of the fourth selector is used for selecting a second preset combination from the second preset combinations according to the input polarity value and outputting a positive sub-pixel value and a negative sub-pixel value according to the selected second preset combination sub-pixel value, wherein the second preset combination is a combination determined according to the sub-pixel value of each pixel unit in the previous display row;

the output end of the second adder is connected with the second input end of the second adder, the first input end of the first comparator and the first input end of the subtracter and is used for outputting the positive sub-pixel accumulated value;

The output end of the third adder is connected with the second input end of the third adder, the second input end of the first comparator and the second input end of the subtracter and is used for outputting the negative sub-pixel accumulated value;

the output end of the first comparator is connected with the control end of the fifth selector and is used for comparing the positive sub-pixel accumulated value with the negative sub-pixel accumulated value and outputting a comparison result;

the first output end of the subtracter is connected with the first input end of the fifth selector and is used for outputting a first difference value of the positive sub-pixel accumulated value and the negative sub-pixel accumulated value, and the second output end of the subtracter is connected with the second input end of the fifth selector and is used for outputting a second difference value of the negative sub-pixel accumulated value and the positive sub-pixel accumulated value;

the fifth selector is configured to output an absolute value of the difference under control of the comparison result. In one possible implementation, the total computation unit includes a fourth adder;

the first input end of the fourth adder is used for inputting the sub-pixel addition value, the second input end of the fourth adder is used for inputting the absolute value of the difference value, and the output end of the fourth adder is used for outputting the total addition value.

In one possible implementation, the minimum determination module includes a plurality of second comparators;

the input end of the first-stage second comparator is used for inputting a total sum value corresponding to each preset charge sharing mode and an identifier corresponding to the total sum value, and the output end of the former-stage second comparator is connected with the input end of the latter-stage second comparator;

and each second comparator is used for comparing the input total sum values in pairs to obtain a comparison result, wherein the comparison result output by the output end of the second comparator of the last stage is the minimum total sum value and an identifier corresponding to the minimum total sum value.

In a second aspect, an embodiment of the present invention provides a timing controller TCON, including a circuit for selecting a charge sharing mode as described in any one of the first aspects.

In a third aspect, an embodiment of the present invention provides a display device, including the timing controller TCON as described in the second aspect.

The invention has the following beneficial effects:

the circuit for selecting a charge sharing mode, the TCON and the display device provided in the embodiments of the present invention are configured to, when a display frame is switched, calculate, for each preset charge sharing mode and each display line in a current frame image, a subpixel addition value of a subpixel which does not participate in charge sharing in a previous display line, calculate an absolute value of a difference between a positive subpixel and a negative subpixel in the previous display line, and calculate a total addition value of the subpixel addition value and the absolute value of the difference, where the minimum value determining module is configured to select a minimum total addition value from total addition values corresponding to a plurality of preset charge sharing modes, and send, to a source driving circuit of the display device, a minimum total addition value and an identifier corresponding to the minimum total addition value to enable the source driving circuit to charge share the previous display line and the current display line according to an identifier control target charge sharing mode. According to the invention, the target charge sharing mode is selected from a plurality of preset charge sharing modes according to the pixel value of the sub-pixel which does not participate in charge sharing in each display line in the current frame image and the absolute value of the difference value of the positive sub-pixel and the negative sub-pixel in each preset charge sharing mode, and the charge sharing of the last display line and the current display line is carried out by using the target charge sharing mode.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it will be apparent that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a related art driving circuit of a TFT-LCD;

fig. 2 is a schematic structural diagram of TCON in the related art;

FIG. 3 is a schematic diagram of a Source Driver circuit in the related art;

FIG. 4 is a schematic diagram showing polarity inversion of gray scale voltages in the related art;

FIG. 5 is a schematic diagram of a charge sharing switch in the related art;

FIG. 6 is a schematic diagram of a charge sharing state of a dot inversion driving method according to the related art;

FIG. 7 is a schematic diagram of a circuit for selecting charge sharing mode according to an embodiment of the present invention;

FIG. 8 is a schematic diagram showing the arrangement of sub-pixels in a TFT-LCD display panel according to an embodiment of the invention;

fig. 9 is a schematic structural diagram of a summing module according to an embodiment of the present invention;

FIG. 10 is a schematic diagram showing an arrangement of subpixels in a TFT-LCD display panel according to another embodiment of the present disclosure;

FIG. 11 is a schematic diagram of a first computing unit according to an embodiment of the present invention;

FIG. 12 is a schematic diagram of a first preset combination according to an embodiment of the present invention;

FIG. 13 is a schematic diagram illustrating a storage relationship between a sub-pixel and a mode register according to an embodiment of the present invention;

fig. 14 is a schematic structural diagram of a second computing unit according to an embodiment of the present invention;

FIG. 15 is a schematic diagram of a second preset combination according to an embodiment of the present invention;

FIG. 16 is a schematic diagram of a sub-pixel and polarity register memory relationship according to an embodiment of the present invention;

FIG. 17 is a schematic diagram of a total calculation unit according to an embodiment of the present invention;

FIG. 18 is a schematic diagram of a minimum value determining module according to an embodiment of the present invention;

FIG. 19 is a schematic diagram of a circuit for selecting charge sharing mode according to an embodiment of the present invention;

FIG. 20 is a schematic diagram of another minimum determining module according to an embodiment of the present invention;

FIG. 21 is a schematic circuit diagram of a comparison module according to an embodiment of the present invention;

FIG. 22 is a schematic diagram illustrating another exemplary storage relationship between sub-pixels and a mode register according to an embodiment of the present invention;

FIG. 23 is a schematic diagram illustrating another exemplary storage relationship between sub-pixels and a polarity register according to an embodiment of the present invention;

Fig. 24 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The driving circuit in the display device is particularly important, as shown in fig. 1, and is a schematic structural diagram of the driving circuit in the display device, where the driving circuit includes a power supply circuit 101, a timing controller 102, a gray scale circuit 103, a source driving circuit 104, a gate driving circuit 105, and a system interface 106.

Signals from the system, some of which are transmitted to the power supply circuit 101 and some of which are transmitted to the timing controller 102, are supplied to the driving circuit via the system interface 106. After receiving the data and signals from the system interface 106, the power supply circuit 101 generates voltages (an operation voltage 1, an operation voltage 2, and an operation voltage 3) necessary for operation of other circuits, and a liquid crystal deflection reference voltage Vcom; the timing controller 102, upon receiving the data and signals from the system interface 106, generates timing control signals (timing control signal 1 and timing control signal 2) that control the operation timings of the source driving circuit 104, the gate driving circuit 105, and other circuits (not shown in fig. 1) in the display device. The gate driving circuit 105 is used for generating high-low digital voltage, outputting the high-low digital voltage to the gate of the TFT switch, and controlling the switching state of each row of pixels.

When the gate driving circuit 105 turns on the thin film transistors of the liquid crystal display panel line by line, the source driving circuit 104 converts a signal related to display data from the timing controller 102 into an analog voltage, and charges the liquid crystal capacitor Clc and the storage capacitor Cs on the liquid crystal display panel to a desired gray scale voltage.

The timing controller 102 is a core circuit for controlling timing in the display device, and is used for controlling when the gate driving circuit 105 and the source driving circuit 104 are activated. As shown in fig. 2, the timing controller 102 converts the image data signal (VX 1/eDP/LVDS) received through the system interface 106 into the timing control signal 1 and the timing control signal 2, and provides the gate driving circuit 105 and the source driving circuit 104 with the required control signals and levels, so that the liquid crystal display panel of the display device can display correctly. Meanwhile, it includes various image processing circuit modules (not shown in fig. 1 and 2) for the liquid crystal display panel to improve defects generated in production of the display panel and existing in principle.

It should be noted that VX1 is also called V-by-One HS, which is a signal transmission interface standard suitable for flat panel displays. eDP (Embedded Display Port, embedded display interface) is an internal digital interface based on DisplayPort architecture and protocol. LVDS (Low-Voltage Differential Signaling, low voltage differential signaling) is a differential signaling technology with Low power consumption, low bit error rate, low crosstalk, and Low radiation.

Wherein the source driving circuit 104 supplies a signal to the source line after the TFT is turned on to charge the pixel electrode to a corresponding gray scale voltage. The structure of the source driving circuit 104 is divided into two large blocks, namely a digital part and an analog part, as shown in fig. 3. The digital section includes a Bi-directional shift Register (Bi-directional Shift Register, S/R) 301, an Input Register (Input Register) 302, a Data Register (Data layer) 303, a Level Shifter (L/S) 304; the analog portion includes a digital-to-analog conversion circuit (Digital Analog Converter, DAC) 305, an Output Buffer circuit (Output Buffer) 306, and a Charge Sharing circuit (Charge Sharing) 307.

In the driving process of the TFT-LCD in the liquid crystal display panel, the difference between the positive and negative polarity gray scale voltages is larger, the dynamic power consumption of the source electrode driving circuit 104 is larger under the high frequency effect of hundreds of MHz, and the charge sharing technology can reduce the power consumption. During the STB (Latch of the Input Register) signal (high-resistance state) high level period shown in fig. 4, which simultaneously controls the output of the Data Latch signal, the gray scale voltages on the connected parity channels are short-circuited by the charge sharing switch SW3 before and after polarity inversion occurs, as shown in fig. 5. During this period, the gray scale voltages of positive and negative polarities of the previous frame image are respectively restored to the vicinity of the Vcom potential by neutralization. When the gray scale voltage of the next frame of image is inverted, the positive and negative gray scale voltages are charged and discharged from the vicinity of the Vcom potential to the target voltage, namely, the voltage only needs to drive half of the amplitude, full swing is not needed, and the power consumption can be reduced.

In fig. 5, the switch SW1 and the switch SW2 are charging switches, and when the switch SW1 is closed, the pixel electrode corresponding to the switch SW1 is charged, and when the switch SW2 is closed, the pixel electrode corresponding to the switch SW2 is charged.

As shown in fig. 6, the charge sharing state of the dot inversion driving method is shown.

The charge sharing mode provided by the conventional TCON is single, and the single charge sharing mode cannot meet the requirement of sufficiently reducing power consumption according to the real-time display state of the TFT-LCD display panel.

In view of the above problems, the present invention provides a circuit for selecting a charge sharing mode, which is applied to a display device, as shown in fig. 7, the circuit comprising: a summing module 61 and a minimum determination module 62;

a summing module 61, configured to calculate, for each preset charge sharing mode and each display line in the current frame image, a subpixel addition value of a subpixel in a previous display line that does not participate in charge sharing in the preset charge sharing mode, and calculate an absolute value of a difference value between a positive subpixel and a negative subpixel in the previous display line, and calculate a total addition value of the subpixel addition value and the absolute value of the difference value;

the minimum value determining module 62 is configured to select a minimum total sum value from total sum values corresponding to a plurality of preset charge sharing modes, and output the minimum total sum value and an identifier corresponding to the minimum total sum value to a source driving circuit of the display device, so that the source driving circuit controls the target charge sharing mode to enable according to the identifier, and charge sharing is performed on a previous display line and a current display line.

When the display picture is switched, the summation module is used for calculating the sub-pixel summation value of the sub-pixels which do not participate in charge sharing in the element and charge sharing mode in the previous display row and calculating the absolute value of the difference value of the positive sub-pixel summation value and the negative sub-pixel summation value, and calculating the total summation value of the absolute value of the sub-pixel summation value and the difference value, wherein the positive sub-pixel summation value is the pixel summation value of the sub-pixel with the positive pixel electrode in the previous display row, the negative sub-pixel summation value is the pixel summation value of the sub-pixel with the negative pixel electrode in the previous display row, and the minimum value determination module is used for selecting the minimum total summation value from the total summation values corresponding to the preset charge sharing modes and outputting the mark corresponding to the minimum total summation value to the source driving circuit of the display device so that the source driving circuit controls the target charge sharing mode according to the mark to enable the current display and charge sharing of the previous display row. According to the invention, the target charge sharing mode is selected from a plurality of preset charge sharing modes according to the pixel values of the sub-pixels participating in charge sharing in each preset charge sharing mode and the pixel values of all the sub-pixels in the display line in each display line in the current frame image, and the charge sharing of the previous display line and the current display line is carried out by using the target charge sharing mode.

It should be noted that, in the embodiment of the present invention, the number of the preset charge sharing modes is plural, and when the charge sharing mode is selected, one of the preset charge sharing modes is selected as the target charge sharing mode, and the preset charge sharing mode in the embodiment of the present invention is illustrated below.

As shown in fig. 8, the TFT-LCD display panel in the display device includes 4 rows of sub-pixels, each row includes 6 sub-pixels, each 3 sub-pixels is a pixel unit, the data lines, which may also be called source lines, are arranged along a first direction, the pixel electrodes of the first sub-pixel in the first display row are positive, the pixel electrodes of the second sub-pixel are negative, the pixel electrodes of the third sub-pixel are positive, the pixel electrodes of the fourth sub-pixel are negative, the pixel electrodes of the fifth sub-pixel are positive, and the pixel electrodes of the sixth sub-pixel are negative.

Referring to fig. 8, a charge sharing switch is disposed between two corresponding sub-pixels between two display rows, for example, a charge sharing switch is disposed between a first sub-pixel of a first display row and a first sub-pixel of a second display row, and when the first sub-pixel of the first display row and the first sub-pixel of the second display row need to share charges, the charge sharing switch is closed to realize charge sharing.

It should be noted that the charge sharing switch may be designed according to actual needs, for example, a charge sharing switch is disposed between the sub-pixels corresponding to each two adjacent display rows, then the charge sharing switch that needs to be closed is selected according to the charge sharing mode, for example, a charge sharing switch is disposed between the sub-pixels corresponding to the odd display rows and the even display rows, and then the charge sharing switch that needs to be closed is selected according to the charge sharing mode.

In the embodiment of the present invention, the charge sharing mode, that is, the mode in which the charge sharing switch is opened and closed, for example, the charge sharing switch between the first subpixel of the first display line and the first subpixel of the second display line is the charge sharing switch 1, the charge sharing switch between the second subpixel of the first display line and the second subpixel of the second display line is the charge sharing switch 2, the charge sharing switch between the third subpixel of the first display line and the third subpixel of the second display line is the charge sharing switch 3, the charge sharing switch between the fourth subpixel of the first display line and the fourth subpixel of the second display line is the charge sharing switch 4, the charge sharing switch between the fifth subpixel of the first display line and the fifth subpixel of the second display line is the charge sharing switch 5, the charge sharing switch between the sixth subpixel of the first display line and the sixth subpixel of the second display line is the charge sharing switch 6, and in the charge sharing mode 1, the charge sharing switch 2 and the charge sharing switch 4 are closed, and the charge sharing switch 5 and the charge sharing switch 6 are opened; in the charge sharing mode 2, the charge sharing switch 1, the charge sharing switch 3, and the charge sharing switch 6 are closed, and the charge sharing switch 2, the charge sharing switch 4, and the charge sharing switch 5 are open.

In a certain charge sharing mode, the charge sharing switch is turned on, which indicates that the two sub-pixels corresponding to the charge sharing switch do not need to share charges, and the charge sharing switch is turned off, which indicates that the two sub-pixels corresponding to the charge sharing switch need to share charges.

The circuit for selecting the charge sharing mode provided by the embodiment of the invention can be integrated in an intelligent source electrode driving control (Smart Source Driver Control) module in TCON.

In a specific implementation, as shown in fig. 9, the summing module 61 provided by an embodiment of the present invention may include a first calculating unit 611, a second calculating unit 612, and a total calculating unit 613;

a first calculating unit 611, configured to select a first sub-pixel not participating in charge sharing from a previous display line according to a preset charge sharing mode, and calculate a sub-pixel addition value of a plurality of first sub-pixels;

a second calculation unit 612 for selecting positive and negative sub-pixels from the previous display line, calculating positive and negative sub-pixel accumulated values of all positive sub-pixels, and calculating absolute values of differences between the positive and negative sub-pixel accumulated values;

a total calculation unit 613 for calculating a total sum of sub-pixel sum and an absolute value of the difference.

For example, as shown in fig. 10, in the previous display line of the first display line, the preset charge sharing mode includes a charge sharing mode 1 and a charge sharing mode 2, in the charge sharing mode 1, the sub-pixel a+, the sub-pixel B-and the sub-pixel D-participate in the charge sharing, the sub-pixel c+, the sub-pixel e+ and the sub-pixel F-do not participate in the charge sharing, and then the first calculating unit selects a first sub-pixel not participating in the charge sharing, that is, the sub-pixel c+, the sub-pixel e+ and the sub-pixel F-, from the first display line according to the charge sharing mode 1, and calculates the sub-pixel addition value of the sub-pixel c+, the sub-pixel e+ and the sub-pixel F-; the second calculating unit selects a sub-pixel with positive polarity and a sub-pixel with negative polarity according to the polarity of the sub-pixel in the first display row, wherein the sub-pixel with positive polarity is: subpixel a+, subpixel c+ and subpixel e+, the subpixels with negative polarity are: sub-pixel B-, sub-pixel D-and sub-pixel F-, accumulating the sub-pixel value of sub-pixel A+, the sub-pixel value of sub-pixel C+ and the sub-pixel value of sub-pixel E+ to obtain a positive sub-pixel accumulated value, accumulating the sub-pixel value of sub-pixel B-, the sub-pixel of sub-pixel D-and the sub-pixel of sub-pixel F-, to obtain a negative sub-pixel accumulated value, and then calculating the absolute value of the difference value of the positive sub-pixel accumulated value and the negative sub-pixel accumulated value.

In the charge sharing mode 2, the sub-pixel A+, the sub-pixel C+ and the sub-pixel F-participate in charge sharing, the sub-pixel B-, the sub-pixel D-and the sub-pixel E+ do not participate in charge sharing, and then the first calculating unit selects a first sub-pixel which does not participate in charge sharing, namely the sub-pixel B-, the sub-pixel D-and the sub-pixel E+ from a first display row according to the charge sharing mode 2, and adds up the sub-pixel value of the sub-pixel B-, the sub-pixel value of the sub-pixel D-and the sub-pixel value of the sub-pixel E+ to obtain a sub-pixel addition value; the second calculating unit selects a sub-pixel with positive polarity and a sub-pixel with negative polarity according to the polarity of the sub-pixel in the first display row, wherein the sub-pixel with positive polarity is: subpixel a+, subpixel c+ and subpixel e+, the subpixels with negative polarity are: sub-pixel B-, sub-pixel D-and sub-pixel F-, accumulating the sub-pixel value of sub-pixel A+, the sub-pixel value of sub-pixel C+ and the sub-pixel value of sub-pixel E+ to obtain a positive sub-pixel accumulated value, accumulating the sub-pixel value of sub-pixel B-, the sub-pixel of sub-pixel D-and the sub-pixel of sub-pixel F-, to obtain a negative sub-pixel accumulated value, and then calculating the absolute value of the difference value of the positive sub-pixel accumulated value and the negative sub-pixel accumulated value.

In a specific implementation, as shown in fig. 11, the first computing unit 611 may include a first selector 6111, a second selector 6112, and a first adder 6113;

the input end of the first selector 6111 is used for inputting the shared value stored in the mode register, the control end of the first selector 6111 is connected with the first output end of the counter, and the output end of the first selector 6111 is connected with the control end of the second selector 6112 and used for outputting the shared value stored in the mode register under the control of the first count value output by the counter;

the input end of the second selector 6112 is used for inputting sub-pixel values in a plurality of first preset combinations, the output end of the second selector 6112 is connected with the first input end of the first adder 6113, and is used for selecting one first preset combination output from the plurality of first preset combinations according to the inputted shared value, wherein the sub-pixel value of the first preset combination is a combined sub-pixel value of the sub-pixel value of each pixel unit in the previous display row;

the output end of the first adder 6113 is connected with the second input end of the first adder 6113, and is used for accumulating the pixel values of the first sub-pixels of the last display line which are input, and outputting the sub-pixel summation value.

In the embodiment of the present invention, each pixel unit includes 3 sub-pixels for illustration.

For a pixel unit including RGB, after combining the 3 sub-pixels RGB, 8 first preset combinations are obtained, which are respectively set as combination 1: "R+G+B", combination 2: "R+G", combination 3: "R+B", combination 4: "R", combination 5: "G+B", combination 6: "G", combination 7: "B", combination 8: "0", if the pixel value of a sub-pixel occupies 8 bits in the register, then storing 3 sub-pixel values in a pixel unit requires 24 bits, for example, pre_line_ [7:0] represents the sub-pixel value of the B sub-pixel in a pixel unit, pre_line_ [15:8] represents the sub-pixel value of the G sub-pixel in the pixel unit, pre_line_ [23:16] represents the sub-pixel value of the R sub-pixel in the pixel unit, then combination 1 is pre_line_ [23:16] +pre_line_ [15:8] +pre_line_ [7:0], combination 2 is pre_line_ [23:16] +pre_line_ [15:8], combination 3 is pre_line_ [23:16] +pre_line_ [7:0], combination 4 is pre_line_ [23:16] +pre_line_ [7:0], and combination [ 4 ] is pre_line_ [15:8] +7:0 ] combination [15:8] [ 7:8 ] _.

Fig. 12 is a schematic diagram of a first preset combination according to an embodiment of the present invention.

If 0 represents not participating in charge sharing, 1 represents participating in charge sharing, when the result output by the first selector 6111 is 000, it indicates that none of the three sub-pixels participate in charge sharing, and the result output by the second selector 6112 is the result of adding the sub-pixel values of the three sub-pixels, namely pre_line_ [23:16] +pre_line_ [15:8] +pre_line_ [7:0]; if the result output by the first selector 6111 is 111, which indicates that all three sub-pixels participate in charge sharing, the result output by the second selector 6112 is 0; if the result output by the first selector 6111 is 011, it is indicated that the sub-pixels corresponding to pre_line_ [15:8] in the three sub-pixels do not participate in charge sharing, and the result output by the second selector 6112 is pre_line_ [15:8], and other combinations are selected by referring to the above manner, and will not be described in detail here.

In implementations, the subpixel values may be stored in 24-bit subpixel registers.

In the embodiment of the invention, the mode register adopts a 6-bit register.

For example, as shown in fig. 13, the sharing information stored in each bit of the mode register indicates a value of whether the corresponding sub-pixel in a certain display line participates in charge sharing, each 6 sub-pixels are a loop, the 6 sub-pixels of the sub-pixels R0, G0, B0, R1, G1 and B1 are a loop, the information of whether the sub-pixel corresponding to the loop participates in charge sharing is stored in the mode register, similarly, the 6 sub-pixels of the sub-pixels R2, G2, B2, R3, G3 and B3 are a loop, the information … … of whether the sub-pixel corresponding to the loop participates in charge sharing is also stored in the mode register, and so on until the information of whether all the sub-pixels (1920) participate in charge sharing are all stored.

The shared information stored in the mode register is the shared information corresponding to every 6 sub-pixels in the previous display row, if the counter inputs a first value to the first selector 6111, the first input end of the first selector 6111 inputs the shared information in the first 3 bits in the mode register, namely dot_mode [2:0], and if the counter inputs a second value to the first selector 6111, the first input end of the first selector 6111 inputs the shared information in the last 3 bits in the mode register, namely dot_mode [5:3], wherein the first value may be 0, the second value may be 1, the first value may also be 1, and the second value may also be 0.

After the second selector 6112 receives the sharing information, it determines whether each sub-pixel in the pixel unit input to the second selector 6112 participates in charge sharing according to the sharing information, 0 represents not participating in charge sharing, 1 represents participating in charge sharing, the currently input sharing information is 001, which indicates that the first sub-pixel does not participate in charge sharing, the second sub-pixel does not participate in charge sharing, the third sub-pixel participates in charge sharing, combination 2 is selected, when the sub-pixel value is input to the first input end of the first adder 6113, the output end of the first adder 6113 outputs the sub-pixel value, then the sub-pixel value is fed back to the second input end of the first adder 6113, at this time, the first input end of the first adder 6113 inputs another sub-pixel value, the output end of the first adder 6113 outputs the sum of the sub-pixel value and the other sub-pixel value, and the subsequent steps may refer to the foregoing steps until all the sub-pixel values are input.

In a specific implementation, as shown in fig. 14, the second computing unit 612 may include a third selector 6121, a fourth selector 6122, a fifth selector 6127, a second adder 6123, a third adder 6124, a first comparator 6125, and a subtractor 6126;

the input end of the third selector 6121 is used for inputting the polarity value stored in the polarity register, the control end of the third selector 6121 is connected with the second output end of the counter, and the output end of the third selector 6121 is connected with the control end of the fourth selector 6122 and used for outputting the polarity value stored in the polarity register under the control of the second count value output by the counter;

the second input end of the fourth selector 6122 is used for inputting the sub-pixel value of the sub-pixel of the previous display row, and the output end of the fourth selector 6122 is connected with the first input end of the second adder 6123 and the first input end of the third adder 6124, and is used for inputting the positive sub-pixel value to the first input end of the second adder 6123 and inputting the negative sub-pixel value to the first input end of the third adder 6124 according to the inputted polarity value;

the output end of the second adder 6123 is connected with the second input end of the second adder 6123, the first input end of the first comparator 6125 and the first input end of the subtracter 6126, and is used for outputting a positive sub-pixel accumulated value;

The output end of the third adder 6124 is connected with the second input end of the third adder 6124, the second input end of the first comparator 6125 and the second input end of the subtracter 6126, and is used for outputting a negative sub-pixel accumulated value;

the output end of the first comparator 6125 is connected with the control end of the fifth selector 6127, and is used for comparing the positive sub-pixel accumulated value with the negative sub-pixel accumulated value and outputting a comparison result;

a first output end of the subtracter 6126 is connected with a first input end of the fifth selector 6127 and is used for outputting a first difference value of the positive sub-pixel accumulated value and the negative sub-pixel accumulated value, and a second output end of the subtracter 6126 is connected with a second input end of the fifth selector 6127 and is used for outputting a second difference value of the negative sub-pixel accumulated value and the positive sub-pixel accumulated value;

a fifth selector 6127 for outputting the absolute value of the difference value under control of the comparison result.

For a pixel unit including three sub-pixels of RGB, after combining the three sub-pixels of RGB, 8 second preset combinations are obtained, which are respectively 9: "{0, R+G+B }", combination 2: "{ B, R+G }", combination 3: "{ G, R+B }", combination 4: "{ G+B, R }", combination 5: "{ R, G+B }", combination 6: "{ R+B, G }", combination 7: "{ R+G, B }", combination 8: "{ R+G+B,0}", if the pixel value of one sub-pixel occupies 8 bits in the register, then storing 3 sub-pixel values in one pixel unit requires 24 bits, e.g., pre_line_ [7:0] represents the sub-pixel value of the B sub-pixel in one pixel unit, pre_line_ [15:8] represents the sub-pixel value of the G sub-pixel in the pixel unit, pre_line_ [23:16] represents the sub-pixel value of the R sub-pixel in the pixel unit, then the combination 9 is {0, pre_line_ [23:16] +pre_line_ [15:8] +pre_line_ [7:0] }, the combination 10 is { pre_line_ [7:0], the pre_line_ [23:16] +pre_line_ [15:8] }, the combination 11 is { pre_line_ [15:8], the pre_line_ [23:16] +pre_line_ [7:0] }, the combination 12 is { pre_line_ [15:8] +pre_line_ [7:0], the pre_line_ [23:16] }, the combination 13 is { pre_line_ [23:16], the pre_line_ [15:8] +pre_line_ [7:0] }, the combination 14 is { pre_line_ [23:16] +pre_line_ [7:0], the pre_line_ [15:8] }, the combination 15 is { pre_line_ [23:16] +pre_line_ [15:8] }, the combination 13 is { pre_line_ [23:16] +pre_line_ [ 15:0 ] +pre_line_ [23:16] +pre_line_ [7:0] }, the combination 14 is { pre_line_ [23:16] +pre_line_ [ 0:0 ] }.

Fig. 15 is a schematic diagram of a second preset combination according to an embodiment of the present invention.

As can be seen from the above examples, the second preset combination in the embodiment of the present invention includes two parts, that is, two parts before and after the comma in the bracket, where the first part, that is, the part before the comma in the bracket, is the part output to the first input end of the second adder 6123, and the second part, that is, the part after the comma in the bracket, is the part output to the first input end of the third adder 6124, that is, the first part corresponds to the positive sub-pixel value in the second preset combination, and the second part corresponds to the negative sub-pixel value.

If 0 represents the pixel electrode of the sub-pixel is negative, 1 represents the pixel electrode of the sub-pixel is negative, when the result output by the third selector 6121 is 000, it means that the three sub-pixels are all negative sub-pixels, the third selector 6122 selects the combination 9 to output, that is, the result output to the second adder 6123 is 0, and the result output to the third adder 6124 is the sum of the sub-pixel values of the three sub-pixels, that is, pre_line_ [23:16] +pre_line_ [15:8] +pre_line_ [7:0]; if the result output by the third selector 6121 is 111, indicating that all three sub-pixels are positive sub-pixels, the fourth selector 6122 selects the combination 16 to output, that is, the result output to the second adder 6123 is the sum of the sub-pixel values of the three sub-pixels to be added, that is, pre_line_ [23:16] +pre_line_ [15:8] +pre_line_ [7:0], and the result output to the third adder 6124 is 0; if the result output by the third selector 6121 is 011, it indicates that the sub-pixel corresponding to pre_line_ [23:16] in the three sub-pixels is a negative sub-pixel, and the other two sub-pixels are positive sub-pixels, the fourth selector 6122 selects the combination 12 to output, that is, inputs pre_line_ [15:8] +pre_line_ [7:0] to the second adder 6123, and inputs pre_line_ [23:16] to the third adder 6124. Other combinations are selected with reference to the above and will not be described in detail here.

The polarity register in the embodiment of the invention can be an 8-bit register.

As shown in fig. 16, each bit of the polarity register represents positive and negative of the pixel polarity of each sub-pixel in the previous display row, each 8 sub-pixels are in a cycle, each 8 sub-pixels of the sub-pixels R0, G0, B0, R1, G1, B1, R2 and G2 are in a cycle, the polarity register stores the polarity information corresponding to each sub-pixel in the cycle, and each 8 sub-pixels of B2, R3, G3, B3, R4, G4, B4 and R5 are in a cycle in order, and likewise, the polarity register stores the polarity information … … corresponding to each sub-pixel in the cycle, and so on until all the polarity information of all the sub-pixels (1920) are completely stored.

The polarity information stored in the polarity register is the polarity information corresponding to every 8 sub-pixels in the previous display line, if the counter inputs the third value to the second selector 6121, the second selector 6121 outputs the polarity information in the first 3 bits stored in the polarity register, i.e., [2:0], if the counter inputs the fourth value to the second selector 6121, the second selector 6121 outputs the polarity information in the second 3 bits stored in the polarity register, i.e., [5:3], if the counter inputs the fifth value to the second selector 6121, the second selector 6121 outputs the polarity information in the last two bits stored in the polarity register and the polarity information in the first bit stored in the polarity register in the next cycle, i.e., { [0], [7:6] }, and so on.

As shown in fig. 17, the total calculation unit 613 may include a fourth adder 6131, a first input terminal of the fourth adder 6131 for inputting a subpixel addition value, a second input terminal of the fourth adder 6131 for inputting an absolute value of the difference value, and an output terminal of the fourth adder 6131 for outputting the total addition value.

The fourth adder 6131 adds the input sum value and the absolute value of the difference value to obtain a total sum value, which is used to characterize the suitability of the preset charge sharing mode, the smaller the total sum value is, the more suitable the preset charge sharing mode is.

In the embodiment of the present invention, each row in the TFT-LCD display panel is sequentially used as a previous display row, the first calculating unit 611 selects the first sub-pixels which do not participate in charge sharing from the previous display row according to the sharing information stored in the mode register, calculates the sub-pixel addition value of all the first sub-pixels in the previous display row, and simultaneously adds the sub-pixel values of the sub-pixels of which the pixel electrodes are positive in the previous display row according to the polarity information stored in the polarity register, so as to obtain a positive sub-pixel accumulation value, adds the sub-pixel values of the sub-pixels of which the pixel electrodes are negative in the previous display row, so as to obtain a negative sub-pixel accumulation value, calculates the absolute value of the difference between the positive sub-pixel accumulation value and the negative sub-pixel accumulation value, and the total calculating unit 613 calculates the total addition value of the pixel addition value and the absolute value of the difference.

In a specific embodiment, as shown in fig. 18, the minimum value determining module 62 may include a plurality of second comparators 621;

the input end of the first-stage second comparator 621 is used for inputting the total sum value corresponding to each preset charge sharing mode and the identifier corresponding to the sum value, and the output end of the previous-stage second comparator 621 is connected with the input end of the next-stage second comparator 621;

each second comparator 621 is configured to compare the input total sum values in pairs to obtain a comparison result and a corresponding identifier, where the comparison result output by the output terminal of the second comparator 621 of the last stage is the minimum total sum value and the identifier corresponding to the minimum total sum value.

In fig. 18, n, m, and j are positive integers greater than 1, and in [ x0, sum1_0], x0 represents a flag, sum1_0 represents a total addition value. The number of total addition values input by the input end of the first-stage second comparator 621 is the same as the number of preset charge sharing modes, that is, each preset charge sharing mode corresponds to one total addition value, the first-stage second comparator 621 compares the input total addition values two by two ((n+1)/2) times to obtain (m+1) comparison results, wherein m= ((n+1)/2) -1, (m+1) comparison results are input into the second-stage second comparator 621, the second-stage second comparator 621 compares the input (m+1) comparison results two by two, and ((m+1)/2) times to obtain ((m+1)/4) comparison results, … …) until the last-stage second comparator outputs one comparison result.

In the embodiment of the present invention, as shown in fig. 19, a plurality of summing modules are included, and each summing module corresponds to a preset charge sharing mode, so when the summing module inputs the calculated total sum value to the minimum value determining module, the identifier corresponding to the summing module is simultaneously input to the minimum value determining module.

The last stage second comparator 621 transmits the minimum sum value and an identification corresponding to the minimum sum value to the source driving circuit of the display device, so that the source driving circuit controls the target charge sharing mode to enable according to the identification, and the last display line and the current display line are subjected to charge sharing.

After receiving the minimum sum value and the identifier corresponding to the minimum sum value, the source driving circuit determines a charge sharing mode corresponding to the received identifier according to the corresponding relation between the identifier and the charge sharing mode, takes the charge sharing mode as a target charge sharing mode, and enables the target charge sharing mode. Wherein, the correspondence between the identification and the charge sharing mode is preset.

In a specific implementation, after the minimum value determining module 62 determines the minimum sum value and the identifier corresponding to the minimum sum value, the minimum sum value and the identifier corresponding to the minimum sum value may also be input to the comparing module 63, as shown in fig. 19, where the comparing module 63 compares the minimum sum value with a preset threshold value, and sends a comparison result to the source driving circuit, so that the source driving circuit controls the target charge sharing mode to enable according to the comparison result.

Specifically, the comparing module 63 may include a third comparator 631, as shown in fig. 21, where a first input terminal of the third comparator 631 is configured to input a minimum sum value and an identifier corresponding to the minimum sum value, a second input terminal of the third comparator 631 is configured to input a preset threshold, and an output terminal of the third comparator 631 is configured to output a comparison result, where the comparison result is the minimum sum value and the identifier corresponding to the minimum sum value if the minimum sum value is less than or equal to the preset threshold, and the comparison result is the preset threshold if the minimum sum value is greater than the preset threshold.

After receiving the minimum sum value and the corresponding identifier, the source driving circuit determines a charge sharing mode corresponding to the received identifier according to the corresponding relation between the identifier and the charge sharing mode, takes the charge sharing mode as a target charge sharing mode and enables the target charge sharing mode; after the source driving circuit receives the preset threshold, it indicates that the most suitable charge sharing mode is not selected, and any preset charge sharing mode is not enabled.

The invention is described below in terms of specific implementations for ease of understanding.

In the embodiment of the present invention, 16 preset charge sharing modes are included, as shown in fig. 19, a circuit for selecting a charge sharing mode provided in the embodiment of the present invention includes 16 summation modules, which are summation module 0, summation module 1, summation module 2 … … and summation module 15 respectively, where each summation module corresponds to one preset charge sharing mode, for example, summation module 0 corresponds to charge sharing mode 0, and the corresponding identifier is 0; the summing module 1 corresponds to a charge sharing mode 1, and the corresponding mark is 1; summing module 2 corresponds to charge sharing mode 2, corresponding identified as 2 … … summing module 15 corresponds to charge sharing mode 15, corresponding identified as 15.

Embodiments of the present invention will be described in detail with reference to fig. 11, 14, 17, 19, 20, 22, and 23.

The pixel values of the sub-pixels of the previous display line are input to the second selector 6112, meanwhile, the mode register inputs the stored mode information of the charge sharing mode 0 to the first selector 6111, the first selector 6111 outputs the mode information stored in the corresponding mode register to the second selector 6112 under the control of the first count value output by the counter, the second selector 6112 selects the output first preset combination according to the mode information, and the first adder 6113 adds the sub-pixel values in the output first preset combination to obtain a sub-pixel summation value sum_un.

The polarity register inputs the stored polarity of the sub-pixel in the previous display row to the third selector 6121, the third second selector 6121 outputs the polarity of the sub-pixel according to the second count value output by the counter, the fourth selector 6122 receives the pixel value of the sub-pixel in the previous display row, the fourth selector 6122 selects a second preset combination according to the received polarity of the sub-pixel, outputs the positive sub-pixel value in each pixel unit to the second adder 6123 according to the selected second preset combination, outputs the negative sub-pixel in each pixel unit to the third adder 6124, the second adder 6123 adds the received positive sub-pixel value to obtain a positive sub-pixel accumulated value sum_pos, and the third adder 6124 adds the received negative sub-pixel value to obtain a negative sub-pixel accumulated value sum_neg.

The second adder 6123 inputs the output positive sub-pixel accumulated value sum_pos and the negative sub-pixel accumulated value sum_neg to the first input terminal and the second input terminal of the first comparator 6125, and the first input terminal and the second input terminal of the subtractor 6124, the first comparator 6125 compares the positive sub-pixel accumulated value sum_pos and the negative sub-pixel accumulated value sum_neg, outputs a comparison result, and outputs the comparison result to the control terminal of the fifth selector 6127; after the subtractor 6126 receives the positive sub-pixel accumulated value sum_pos and the negative sub-pixel accumulated value sum_neg, the positive sub-pixel accumulated value sum_pos and the negative sub-pixel accumulated value sum_neg are subtracted to obtain a first difference value, the negative sub-pixel accumulated value sum_neg and the positive sub-pixel accumulated value sum_pos are subtracted to obtain a second difference value, and the first difference value and the second difference value are output to the fifth selector 6127.

The fifth selector 6127 outputs the absolute value abs_diff of the difference value under the control of the comparison result, and if the comparison result is greater than 0, the fifth selector 6127 takes the first difference value as the absolute value abs_diff of the difference value, otherwise takes the second difference value as the absolute value abs_diff of the difference value.

The fourth adder 6131 adds the sum_un of the sub-pixels obtained in the charge sharing mode 0 and the absolute value abs_diff of the difference to obtain a total sum_0, wherein 0 may represent the identification of the summing module or the identification of the charge sharing mode.

Since the number of the preset charge sharing modes is 16, that is, the number of the corresponding mode registers is 16, the above steps are repeated 16 times, and finally 16 accumulated values sum_x are obtained, wherein x is an integer from 0 to 15.

The minimum determination module 62 compares the 16 total sums entered to obtain a minimum total sum.

As shown in fig. 20, when there are 16 preset charge sharing modes, the minimum value determination module is structured schematically. The minimum value determining module 62 includes 4 second comparators 621, the first second comparator 621 inputs 16 total sum values and the identifiers corresponding to each total sum value, outputs 8 comparison results after comparing the 16 total sum values in pairs, inputs the 8 comparison results to the second comparator 621, outputs 4 comparison results after comparing the 8 comparison results in pairs by the second comparator 621, outputs 2 comparison results, inputs the 2 comparison results to the final second comparator 621, and outputs one comparison result as the minimum total sum value by the final comparator.

The comparison module 63 compares the minimum sum value with a preset threshold, if the minimum sum value is smaller than or equal to the preset threshold, the sum value and the corresponding identifier are output, otherwise, the preset threshold is output.

For example, if the minimum sum value is the sum module 0 output, then the target charge share flag is 0.

Specific mode registers and polarity registers are described below.

As shown in fig. 22, for example, the mode registers reg_dot_mode [5:0] = 6' B01_0101, R0, G0, B0, R1, G1, B1 and then the polarity of every 6 consecutive sub-pixels are stored in the 6-bit mode registers, i.e. 0, 1, respectively. 0 indicates that the corresponding sub-pixel does not participate in charge sharing, and 1 indicates that the corresponding sub-pixel participates in charge sharing.

When the first output end of the counter counts to 1 for the first time, the corresponding three sub-pixels are R0, G0 and B0 respectively, and the corresponding polarity modes are 0, 1 and 0 respectively, namely R0 and B0 do not participate in charge sharing, and G0 participates in charge sharing. Referring to fig. 11, the pixel values of R0 and B0 are added to sum_un by the second selector 6122 and the first adder 6113. When the first output end of the counter counts to 2 for the first time, the corresponding three sub-pixels are R1, G1, and B1 respectively, and the corresponding polarity modes are 1, 0, and 1 respectively, that is, G1 does not participate in charge sharing, and R1 and B1 participate in charge sharing, and the pixel value of G1 is added to sum_un through the second selector 6122 and the first adder 6113.

When the first output end of the counter counts to 1 for the second time, the corresponding three sub-pixels are R2, G2 and B2 respectively; when the first output end of the second time counts to 2 for the second time, the corresponding three sub-pixels are R3, G3 and B3 respectively; by analogy, if the entire row is 1920 pixels, the counter counts 960 groups, 2 times per group.

As shown in fig. 23, the polarity registers reg_dot_pol [7:0] = 8' B1011_1100, R0, G0, B0, R1, G1, B1, R2, G2 and then each 8 consecutive sub-pixels have a polarity corresponding to the 8-bit polarity register, i.e. 1, 0,1, 0,1 is positive, 0 indicates the pixel polarity is negative, and 1 indicates the pixel polarity is positive. The pixel value of the sub-pixel with positive pixel polarity is accumulated to the positive sub-pixel accumulated value sum_pos, and the pixel value of the sub-pixel with negative pixel polarity is accumulated to the negative sub-pixel accumulated value sum_neg.

When the second output end of the counter counts to 1 for the first time, the corresponding three sub-pixels are R0, G0 and B0 respectively, the corresponding polarities are 1, 0 and 1 respectively, namely the voltage polarities of R0 and B0 are positive, and the voltage polarity of G0 is negative. Referring to fig. 14, the sub-pixel values of R0 and B0 are accumulated to sum_pos by the third selector 6121, the fourth selector 6122, and the second adder 6123, and the sub-pixel value of G0 is accumulated to sum_neg by the third selector 6121, the fourth selector 6122, and the third adder 6124. When the second output end of the counter counts to 2 for the first time, the corresponding three sub-pixels are R1, G1 and B1 respectively, and the corresponding polarities are 1, 1 and 1 respectively, namely, the voltage polarities of R1, G1 and B1 are positive, and the pixel values of R1, G1 and B1 are accumulated to sum_pos through a third selector 6121, a fourth selector 6122 and a second adder 6123; when the second output terminal of the counter counts to 3 for the first time, the corresponding three sub-pixels are R2, G2, and B2, the corresponding polarities are 0, and 1, respectively, that is, the voltage polarity of B2 is positive, the voltage polarity of R2 and G2 is negative, the pixel value of B2 is accumulated to sum_pos through the third selector 6121, the fourth selector 6122, and the second adder 6123, and the pixel value of R2 and G2 is accumulated to sum_neg through the third selector 6121, the fourth selector 6122, and the third adder 6124.

When the second output end of the counter counts to 1 for the second time, the corresponding three sub-pixels are R8, G8 and B8 respectively; when the second output end of the counter counts to 2 for the second time, the corresponding three sub-pixels are R9, G9 and B9 respectively; by analogy, if the entire row is 1920 pixels, the counter counts 240 groups, 8 times each. After the charge sharing mode of the TFT-LCD display panel is determined, the TCON transmits the minimum sum value and the corresponding identification two data to the source driving circuit, and the source driving circuit converts the minimum sum value and the corresponding identification two data into analog signals for charge sharing.

It should be noted that, in the embodiment of the present invention, the polarity of the pixel electrode of the sub-pixel is equal to the voltage polarity of the sub-pixel.

Based on the same inventive concept, the embodiments of the present invention also provide a TCON including any of the above circuits for selecting a charge sharing mode. The principle of the TCON solution is similar to that of the aforementioned circuit for selecting the charge sharing mode, so that the implementation of the TCON can be referred to the implementation of the aforementioned circuit for selecting the charge sharing mode, and the repetition is not repeated here.

Based on the same inventive concept, an embodiment of the present invention also provides a display device, as shown in fig. 24, including any one of the TCONs 102 described above. The implementation of the display device may be referred to the implementation of TCON, and the repetition is not repeated here.

As can be further seen from fig. 24, the display device provided by the embodiment of the present invention further includes a source driving circuit 104, a gate driving circuit 105 and a display 241, where the tcon 102 provides timing control signals for the source driving circuit 104 and the gate driving circuit 105, so that the display 241 can correctly display images.

Various modifications and alterations of this invention may be made by those skilled in the art without departing from the spirit and scope of this invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A circuit for selecting a charge sharing mode for use in a display device, comprising:

a first calculating unit, configured to select a first sub-pixel not participating in charge sharing from a previous display line according to a preset charge sharing mode, and calculate a sub-pixel addition value of a plurality of first sub-pixels;

a second calculating unit, configured to select a positive sub-pixel and a negative sub-pixel from the previous display line, calculate positive sub-pixel accumulated values of all positive sub-pixels and negative sub-pixel accumulated values of all negative sub-pixels, and calculate absolute values of differences between the positive sub-pixel accumulated values and the negative sub-pixel accumulated values, where the positive sub-pixel is a positive second sub-pixel, and the negative sub-pixel is a negative second sub-pixel;

A total calculation unit for calculating a total sum of the sub-pixel sum and an absolute value of the difference;

a minimum value determining module, configured to select a minimum total sum value from total sum values corresponding to a plurality of preset charge sharing modes, and output, to a source driving circuit of the display device, a minimum total sum value and an identifier corresponding to the minimum total sum value, so that the source driving circuit controls a target charge sharing mode to enable according to the identifier, and charge sharing is performed on the previous display line and the current display line;

and the comparison module is used for comparing the minimum sum value with a preset threshold value and sending a comparison result to the source electrode driving circuit so that the source electrode driving circuit controls the enabling of the target charge sharing mode according to the identification.

2. The circuit of claim 1, wherein the comparison module comprises a third comparator;

3. The circuit of claim 1, wherein the first computing unit comprises a first selector, a second selector, and a first adder;

4. The circuit of claim 3, wherein the second computing unit comprises a third selector, a fourth selector, a fifth selector, a second adder, a third adder, a first comparator, and a subtractor;

the fifth selector is configured to output an absolute value of the difference under control of the comparison result.

5. The circuit of claim 1, wherein the total computation unit comprises a fourth adder;

6. The circuit of claim 1, wherein the minimum determination module comprises a plurality of second comparators;

7. A timing controller TCON comprising a circuit for selecting a charge sharing mode as claimed in any one of claims 1 to 6.

8. A display device comprising the timing controller TCON of claim 7.