CN115098245A

CN115098245A - Task processing method, electronic device, storage medium, and computer program product

Info

Publication number: CN115098245A
Application number: CN202210607821.6A
Authority: CN
Inventors: 宋攀云
Original assignee: Beijing Kuangshi Technology Co Ltd
Current assignee: Beijing Kuangshi Technology Co Ltd
Priority date: 2022-05-31
Filing date: 2022-05-31
Publication date: 2022-09-23

Abstract

The embodiment of the application discloses a task processing method, electronic equipment, a storage medium and a computer program product, wherein the method comprises the following steps: responding to a call request initiated by a CA in an REE, and dividing a target task into at least two subtasks, wherein the call request is used for requesting a TA in a TEE to execute the target task; distributing the at least two subtasks to a CPU arithmetic unit and a coprocessor respectively; instructing the CPU arithmetic unit and the coprocessor to run the sub-tasks distributed by the CPU arithmetic unit and the coprocessor to obtain a target running result; providing the target operation result to the CA.

Description

Task processing method, electronic device, storage medium, and computer program product

Technical Field

The present application relates to the field of artificial intelligence technologies, and in particular, to a task processing method, an electronic device, a storage medium, and a computer program product.

Background

The REE (Rich Execution Environment) is an Environment in which an operating system in the electronic device runs, and may run a general system such as Android and IOS, and an Application running under the REE is simply referred to as a CA (Client Application). The TEE (Trusted Execution Environment) is an independent processing Environment which has operation and storage functions and can provide security and integrity protection, is used for realizing isolation from the REEs in operation from software and hardware levels and ensuring that data and calculation are not interfered by a conventional operating system, taking a face recognition task as an example, the TEE is used for isolating processes of acquisition, storage, verification and the like of face data and preventing an attacker from tampering information such as face data, characteristics, an authentication result and the like, and an Application running under the TEE is called TA (Trusted Application) for short.

Under the TEE framework, an interface is provided for a CA in an REE inside the TEE, so that the CA in the REE can call a TA in the TEE to execute a corresponding task without leaking sensitive data. In the prior art, after receiving a call request of a CA, a TA responds to the call request and executes a corresponding task, however, because a TEE framework only supports serial execution of tasks running therein on a CPU, a processing flow of the whole task runs with long time consumption and high power consumption, resulting in low task processing efficiency.

Disclosure of Invention

The embodiment of the application provides a task processing method, an electronic device, a storage medium and a computer program product, so as to solve the technical problem that the task processing efficiency under a TEE framework is low in the prior art.

According to a first aspect of the present application, a task processing method is disclosed, the method comprising:

responding to a call request initiated by CA in REE, dividing a target task into at least two subtasks, wherein the call request is used for requesting TA in TEE to execute the target task;

distributing the at least two subtasks to a CPU arithmetic unit and a coprocessor respectively;

instructing the CPU arithmetic unit and the coprocessor to run the sub-tasks distributed by the CPU arithmetic unit and the coprocessor to obtain a target running result;

providing the target operation result to the CA.

According to a second aspect of the present application, there is disclosed a task processing apparatus, the apparatus comprising:

the dividing module is used for responding to a call request initiated by CA in REE and dividing a target task into at least two subtasks, wherein the call request is used for requesting TA in TEE to execute the target task;

the distribution module is used for distributing the at least two subtasks to the CPU arithmetic unit and the coprocessor respectively;

the indicating module is used for indicating the CPU arithmetic unit and the coprocessor to run the sub-tasks distributed by the CPU arithmetic unit and the coprocessor to obtain a target running result;

and the feedback module is used for providing the target operation result to the CA.

According to a third aspect of the present application, an electronic device is disclosed, comprising a memory, a processor and a computer program stored on the memory, the processor executing the computer program to implement the task processing method as in the first aspect.

According to a fourth aspect of the present application, a computer-readable storage medium is disclosed, having stored thereon a computer program/instructions which, when executed by a processor, implement the task processing method as in the first aspect.

According to a fifth aspect of the present application, a computer program product is disclosed, comprising computer programs/instructions which, when executed by a processor, implement the task processing method as in the first aspect.

In the embodiment of the application, after receiving a call request initiated by a CA in an REE, a TA in a TEE divides a target task into at least two subtasks, allocates each subtask to a CPU operator and a coprocessor respectively, instructs the CPU operator and the coprocessor to execute the allocated subtasks, obtains a target operation result, and provides the target operation result to the CA. Compared with the prior art, in the embodiment of the application, the coprocessor has advantages in calculation of some types of subtasks, the reasoning process of a single subtask can be accelerated, and the coprocessor has advantages in lower clock frequency and power consumption compared with a CPU (central processing unit), so that the task to be processed is divided into a plurality of subtasks, one part of the subtasks are distributed to a CPU arithmetic unit to run, the other part of the subtasks are distributed to the coprocessor to run, synchronous results are fed back to a CA (central processing unit) after the running of each subtask is finished, concurrent calculation can be logically realized, the running time consumption and the power consumption of the whole task are reduced, and the task processing efficiency is improved.

Drawings

FIG. 1 is a diagram illustrating a task processing procedure under a TEE framework in the prior art;

FIG. 2 is a flowchart of a task processing method provided in an embodiment of the present application;

FIG. 3 is one of the exemplary diagrams of the task processing procedure under the TEE framework provided by the embodiment of the present application;

FIG. 4 is a second exemplary diagram of a task processing procedure under the TEE framework provided by the embodiment of the present application;

FIG. 5 is a schematic structural diagram of a task processing device according to an embodiment of the present disclosure;

fig. 6 is a block diagram of an electronic device according to an embodiment of the present application.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and the detailed description.

It should be noted that, for simplicity of description, the method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the embodiments are not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required of the embodiments described herein.

In recent years, technical research based on artificial intelligence, such as computer vision, deep learning, machine learning, image processing, and image recognition, has been actively developed. Artificial Intelligence (AI) is an emerging scientific technology for studying and developing theories, methods, techniques and application systems for simulating and extending human Intelligence. The artificial intelligence subject is a comprehensive subject and relates to various technical categories such as chips, big data, cloud computing, internet of things, distributed storage, deep learning, machine learning and neural networks. Computer vision is an important branch of artificial intelligence, particularly a machine is used for identifying the world, and computer vision technology generally comprises technologies such as face identification, living body detection, fingerprint identification and anti-counterfeiting verification, biological feature identification, face detection, pedestrian detection, target detection, pedestrian identification, image processing, image identification, image semantic understanding, image retrieval, character identification, video processing, video content identification, behavior identification, three-dimensional reconstruction, virtual reality, augmented reality, synchronous positioning and map construction (SLAM), computational photography, robot navigation and positioning and the like. With the research and progress of artificial intelligence technology, the technology is applied to various fields, such as security, city management, traffic management, building management, park management, face passage, face attendance, logistics management, warehouse management, robots, intelligent marketing, computational photography, mobile phone images, cloud services, smart homes, wearable equipment, unmanned driving, automatic driving, smart medical treatment, face payment, face unlocking, fingerprint unlocking, testimony verification, smart screens, smart televisions, cameras, mobile internet, live webcasts, beauty treatment, medical beauty treatment, intelligent temperature measurement and the like.

Currently, under the TEE framework, the internal of the TEE provides an interface for the CA in the REE, so that the CA in the REE can call the TA in the TEE to perform related tasks without leaking sensitive data. As shown in fig. 1, in the prior art, a CA side in an REE initiates a call request, a TA in a TEE responds to the call request, and executes a related task, and since a TEE framework runs on a CPU single core, concurrent execution cannot be implemented in the TA, and all subtasks of the related task: and sequentially and serially running the subtask A, the subtask B, the subtask C and the subtask D on the CPU, and then feeding back a final running result to a CA (central authority) in the REE, wherein the CA acquires the running result.

Therefore, in the prior art, the operation of the whole task processing flow is long in time consumption and high in power consumption, and the task processing efficiency is low. To solve the foregoing technical problem, embodiments of the present application provide a task processing method, an electronic device, a storage medium, and a computer program product.

For ease of understanding, the concepts involved in the embodiments of the present application will first be explained in detail.

The TEE (Trusted execution environment) is an independent processing environment with operation and storage functions and capable of providing security and integrity protection, and the basic idea is as follows: and a block of isolated memory is separately allocated to the sensitive data in the hardware, all the sensitive data calculation is carried out in the block of memory, and except for an authorized interface, other parts in the hardware cannot access information in the block of isolated memory, so that the privacy calculation of the sensitive data is realized.

The REE (Rich Execution Environment) is an Environment in which an operating system runs, and can run a general operating system such as Android and IOS, and the REE is an open Environment which is easily attacked, such as stealing of sensitive data, stealing of mobile payment, and the like.

Relationship of TEE to REE: the TEE is a secure area on the central processor that ensures that sensitive data is processed in an isolated and trusted environment, thereby protecting against software attacks from the REE. The TEE interior provides an interface for software in the REE, so that the software in the REE can call the TEE to process data, but sensitive data cannot be leaked.

A TA (Trusted Application) is an Application running in the TEE. The TEE can protect the integrity and confidentiality of the TA end-to-end, and can provide stronger processing power and larger memory space.

A CA (Client Application) is an Application running in the REE.

A coprocessor refers to a special-purpose processor other than a CPU (Central Processing Unit), and may include: a GPU (Graphics Processing Unit), a DSP (Digital Signal Processing), an NPU (Neural-network Processing Unit), and the like.

Next, a task processing method provided in an embodiment of the present application is described.

In the embodiment of the present application, the TA in the TEE runs on a secure area of the CPU, and the secure area includes a CPU controller, a CPU operator and a CPU memory dedicated to the TA. And the TA special CPU controller instructs the TA special CPU arithmetic unit and the CPU memory to execute corresponding actions, and the TA special CPU arithmetic unit, the TA special CPU memory and the TA special CPU memory are mutually matched to realize task processing under a TEE framework.

Fig. 2 is a flowchart of a task processing method provided in an embodiment of the present application, and as shown in fig. 2, the method may include the following steps: step 201, step 202, step 203 and step 204, wherein,

in step 201, in response to a call request initiated by a CA in an REE, a target task is divided into at least two subtasks, where the call request is used to request a TA in a TEE to execute the target task.

In the embodiment of the application, the target task may be a task with a high requirement on data security, such as a face recognition task, a payment task, or an iris recognition task.

In step 202, at least two subtasks are assigned to the CPU operator and the coprocessor, respectively.

In an embodiment of the present application, the coprocessor may include at least one of: GPU, DSP and NPU.

In the embodiment of the application, part of subtasks of the target task can be distributed to the CPU arithmetic unit, and the rest part of subtasks can be distributed to the same coprocessor; alternatively, part of the subtasks of the target task may be distributed to the CPU operators, and the remaining part of the subtasks may be distributed to different coprocessors.

In step 203, the CPU operator and the coprocessor are instructed to run their assigned subtasks, resulting in a target run result.

In the embodiment of the application, the CPU arithmetic unit and the coprocessor are instructed to run the distributed subtasks to obtain the running result of each subtask, and the target running result is generated based on the running result of each subtask.

In step 204, the target operation result is provided to the CA.

For convenience of understanding, steps 201 to 204 are described with reference to the exemplary diagram shown in fig. 3, as shown in fig. 3, a CA side in an REE initiates a call request, a TA in a TEE responds to the call request, and executes a related task, for all subtasks of the related task: the method comprises the following steps that a subtask A, a subtask B, a subtask C and a subtask D are distributed to a CPU (specifically a CPU arithmetic unit), the task C is distributed to a coprocessor, the TA utilizes a secure data transmission channel to carry out data interaction with the coprocessor, information such as input, output and state of a model is synchronized, then a final operation result is fed back to a CA (central authority) in the REE, and the CA acquires the operation result.

Comparing the task processing mode under the TEE framework in the prior art shown in fig. 1 with the task processing mode under the TEE framework in the embodiment of the present application shown in fig. 3, it is found that:

the subtask C is distributed to run on the coprocessor at present compared with the original CPU, so that the task processing speed can be improved; the subtask C and the subtask B logically realize parallel operation, and the CPU and the coprocessor separately operate and are distributed in respective subtasks.

As can be seen from the above embodiments, in this embodiment, after receiving a call request initiated by a CA in an REE, a TA in a TEE divides a target task into at least two subtasks, allocates each subtask to a CPU operator and a coprocessor, instructs the CPU operator and the coprocessor to execute the allocated subtasks, obtains a target operation result, and provides the target operation result to the CA. Compared with the prior art, in the embodiment of the application, the coprocessor has advantages in calculation of some types of subtasks, the reasoning process of a single subtask can be accelerated, and the coprocessor has advantages in lower clock frequency and power consumption compared with a CPU (central processing unit), so that the task to be processed is divided into a plurality of subtasks, one part of the subtasks are distributed to a CPU arithmetic unit to run, the other part of the subtasks are distributed to the coprocessor to run, synchronous results are fed back to a CA (central processing unit) after the running of each subtask is finished, concurrent calculation can be logically realized, the running time consumption and the power consumption of the whole task are reduced, and the task processing efficiency is improved.

In another embodiment provided by the present application, when sub-tasks of a target task are divided, there may be no logical dependency relationship between the sub-tasks of the target task; alternatively, there may be logical dependencies between partial subtasks of the target task and no logical dependencies between partial subtasks.

In one example, the target task is a face recognition task, and the subtasks of the face recognition task include: the system comprises a face key point detection subtask, a living body detection subtask and a face feature extraction subtask, wherein a logical dependency relationship exists between the living body detection subtask and the face key point detection subtask, a logical dependency relationship also exists between the face feature extraction subtask and the face key point detection subtask, and a logical dependency relationship does not exist between the living body detection subtask and the face feature extraction subtask.

In practical application, the face key point detection subtask may correspond to a face detection model, the living body detection subtask may correspond to a living body detection model, the face feature extraction subtask may correspond to a face feature extraction model, and the three models may be models constructed based on a neural network.

In another embodiment provided by the present application, considering that some subtasks involve neural network models, these subtasks can be distributed to the coprocessors due to the computational advantage of the neural network by the coprocessors themselves; also, considering that some subtasks must depend on the CPU for execution, these subtasks need to be distributed to the CPU. In view of the above, the step 202 may include the steps of: and respectively distributing at least two subtasks to the CPU arithmetic unit and the coprocessor according to the service requirements of the subtasks.

In some embodiments, when the target task is a face recognition task, the step 202 may include the following steps: and distributing the human face key point detection subtask to a CPU (central processing unit), and distributing the human face feature extraction subtask and the living body detection subtask to different coprocessors respectively.

For example, the face key point detection subtask is distributed to the CPU, the face feature extraction subtask is distributed to the GPU, and the live body detection subtask is distributed to the DSP.

In some embodiments, when the target task is a face recognition task, the step 202 may include the following steps: and distributing the face key point detection subtask to a CPU (central processing unit), and distributing the face feature extraction subtask and the living body detection subtask to the CPU and the coprocessor respectively.

For example, the face key point detection subtask is distributed to the CPU, the living body detection subtask is distributed to the CPU, and the face feature extraction subtask is distributed to the coprocessor. For the face recognition task, a face detection model and a living body detection model are deployed on a CPU arithmetic unit, and a face feature extraction model is deployed on a coprocessor, so that parallel calculation of the face feature extraction model and the living body detection model is realized logically, and the whole face recognition processing process is accelerated.

For another example, as shown in fig. 4, the face key point detection subtask is assigned to the CPU, the face feature extraction subtask is assigned to the CPU, and the living body detection subtask is assigned to the coprocessor. For the face recognition task, a face detection model and a face feature extraction model are deployed on a CPU arithmetic unit, and a living body detection model is deployed on a coprocessor, so that parallel calculation of the face feature extraction model and the living body detection model is realized logically, and the whole face recognition processing process is accelerated.

For ease of understanding, the processing procedure of the face recognition task is described in detail in connection with the example shown in fig. 4. Firstly, a CA side initiates a calling request and waits for a TA to feed back a face authentication result; the TA responds to the call request, allocates a face key point detection subtask and a face feature extraction subtask to a CPU arithmetic unit, and allocates a living body detection subtask to a coprocessor; after acquiring input data of a user from a security camera, the TA runs a face key point detection subtask on a CPU arithmetic unit and obtains a running result; the TA transmits input data which depends on the in-vivo detection subtask to the coprocessor by using a safety data channel; the TA runs a face feature extraction subtask on a CPU arithmetic unit and obtains a running result, and simultaneously runs a living body detection subtask on a coprocessor and obtains a running result; the TA acquires the operation result of the in-vivo detection subtask by using a safe transmission channel; and the TA synchronously processes the operation result of the face feature extraction subtask and the operation result of the living body detection subtask to obtain a final face recognition result, and provides the face recognition result to the CA.

In the first step, the face key point detection subtask can detect a face and face key points from an input image by using a face detection model; and then, the living body detection subtask uses a living body detection model to perform living body detection, the face feature extraction subtask uses a face feature extraction model to perform face feature extraction, the model inputs corresponding to the two steps are key points output in the first step, and the two models do not have logical dependence and can be asynchronously executed, so that parallel computation can be realized in business.

In another embodiment provided by the present application, data dependent on each subtask may be read into the CPU memory in advance so as to form data isolation from the REE environment, and at this time, the CPU memory stores data dependent on each subtask during operation; and then, instructing the CPU arithmetic unit and the coprocessor to run the distributed subtasks based on the data in the CPU memory to obtain the running result of each subtask, and generating a target running result based on the running result of each subtask.

Accordingly, the step 203 may include the following steps (not shown in the figure): step 2031, step 2032, step 2033 and step 2034, wherein,

in step 2031, the CPU memory is instructed to transfer the data, which is dependent on the subtasks allocated by the coprocessor in the CPU memory, to the coprocessor through a secure data channel between the CPU and the coprocessor.

In the embodiment of the present application, the secure data channel may be constructed in the following manner: creating a target shared memory space on a CPU memory; and mapping the physical address of the target shared memory space to the coprocessor to obtain a secure data channel between the CPU and the coprocessor.

In practical application, any mapping method in the prior art may be used to map the physical address of the target shared memory space to the coprocessor, which is not limited herein.

In the embodiment of the application, besides transferring the data depending on the subtasks, various states between the CPU and the coprocessor can be synchronized through the secure data transmission channel.

In step 2032, instruct the coprocessor to run its assigned subtasks based on the data transferred by the CPU memory, obtain a first running result; and instructing the CPU arithmetic unit to run the sub-tasks allocated to the CPU arithmetic unit based on the sub-task dependency data stored in the CPU memory to obtain a second running result.

In the embodiment of the application, when the coprocessor starts to run the distributed subtasks, the coprocessor can transmit the starting state to the CPU controller through the safety data channel, and the CPU controller instructs the CPU arithmetic unit to start to run the distributed subtasks at the same time, so that the parallel running of the coprocessor and the CPU arithmetic unit is realized.

In step 2033, the coprocessor is instructed to pass the first operation result to the CPU operator over the secure data channel.

In step 2034, the CPU operator is instructed to generate a target operation result based on the first operation result and the second operation result.

In the embodiment of the application, for a simple task, a target operation result can be generated by simply and/or operating the first operation result and the second operation result; for complex tasks, complex processing can be performed on the first operation result and the second operation result to obtain a target operation result.

It can be seen that, in the embodiment of the present application, the existing mechanism of the TEE can be utilized to expand the functions thereof according to the actual service, specifically, taking the DSP as an example, the secure DSP of the high-pass platform transmits data and models to the DSP through the secure data channel from the TEE to the DSP, and the DSP uses a self-defined PD (process) specially used for neural network inference to complete the corresponding work. The secure data channel mainly utilizes a data channel from TEE to DSP, which is realized on a high-pass platform, and specifically comprises the following steps: a block of shared memory (ion/dma) is created, and the TEE framework realizes the characteristic of 'safe' access for data interaction, and the safety of the TEE framework is ensured by a platform TEE mechanism.

In some embodiments, in a TEE framework, when a target task is relatively simple and cannot be further divided into subtasks, the target task may also be allocated to a coprocessor to run, and in a process of allocating the target task to the coprocessor to run, a data and state transmission manner is similar to that in the embodiment shown in fig. 2, and is not described herein again.

Fig. 5 is a schematic structural diagram of a task processing device according to an embodiment of the present application, and as shown in fig. 5, the task processing device 500 may include: a partitioning module 501, an allocation module 502, an indication module 503, and a feedback module 504, wherein,

a dividing module 501, configured to divide a target task into at least two subtasks in response to a call request initiated by a CA in an REE, where the call request is used to request a TA in a TEE to execute the target task;

an allocating module 502, configured to allocate the at least two subtasks to the CPU arithmetic unit and the coprocessor respectively;

an indicating module 503, configured to instruct the CPU operator and the coprocessor to execute the sub-tasks allocated to the CPU operator and the coprocessor to obtain a target operation result;

a feedback module 504 configured to provide the target operation result to the CA.

As can be seen from the foregoing embodiment, in this embodiment, after receiving a call request initiated by a CA in an REE, a TA in a TEE divides a target task into at least two subtasks, allocates each subtask to a CPU operator and a coprocessor, instructs the CPU operator and the coprocessor to execute the allocated subtasks, obtains a target operation result, and provides the target operation result to the CA. Compared with the prior art, in the embodiment of the application, the coprocessor has advantages in calculation of some types of subtasks, the inference process of a single subtask can be accelerated, and the coprocessor has advantages of lower clock frequency and power consumption compared with a CPU (central processing unit), so that the task to be processed is divided into a plurality of subtasks, one part of subtasks are distributed to a CPU arithmetic unit to operate, the other part of subtasks are distributed to the coprocessor to operate, synchronous results are fed back to a CA (central processing unit) after the operation of each subtask is finished, concurrent calculation can be logically realized, the operation time consumption and the power consumption of the whole task are reduced, and the task processing efficiency is improved.

Optionally, as an embodiment, the indicating module 503 may include:

the first indication submodule is used for indicating a CPU memory to transfer data, which are depended by subtasks distributed by a coprocessor, in the CPU memory to the coprocessor through a security data channel between the CPU and the coprocessor;

the second indication submodule is used for indicating the coprocessor to run the distributed subtasks based on the data transmitted by the CPU memory to obtain a first running result; and instructing the CPU arithmetic unit to run the distributed subtasks based on the subtask dependent data stored in the CPU memory to obtain a second running result;

the third indication submodule is used for indicating the coprocessor to transmit the first operation result to the CPU arithmetic unit through the secure data channel;

and the fourth indicating submodule is used for indicating the CPU arithmetic unit to generate a target operation result based on the first operation result and the second operation result.

Optionally, as an embodiment, the secure data channel is constructed by:

creating a target shared memory space on the CPU memory;

and mapping the physical address of the target shared memory space to the coprocessor to obtain a secure data channel between the CPU and the coprocessor.

Optionally, as an embodiment, the allocating module 502 may include:

and the first distributing submodule is used for distributing the at least two subtasks to the CPU arithmetic unit and the coprocessor respectively according to the service requirements of the subtasks.

Optionally, as an embodiment, there is no logical dependency relationship between the subtasks of the target task; or, a logical dependency relationship exists between partial subtasks of the target task, and a logical dependency relationship does not exist between partial subtasks.

Optionally, as an embodiment, the target task is a face recognition task, and the subtasks of the face recognition task include: a face key point detection subtask, a living body detection subtask and a face feature extraction subtask; the allocating module 502 may include:

the second distribution sub-module is used for distributing the face key point detection sub-task to a CPU (central processing unit), and respectively distributing the face feature extraction sub-task and the living body detection sub-task to the CPU and the coprocessor; alternatively, the first and second electrodes may be,

and the third sub-module is used for distributing the human face key point detection sub-task to a CPU (central processing unit), and respectively distributing the human face feature extraction sub-task and the living body detection sub-task to different coprocessors.

Optionally, as an embodiment, the coprocessor includes at least one of: GPU, DSP and NPU.

Any step and specific operation in any step in the embodiments of the task processing method provided by the present application can be completed by a corresponding module in the task processing device. The process of the corresponding operation performed by each module in the task processing device refers to the process of the corresponding operation described in the embodiment of the task processing method.

For the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and reference may be made to the partial description of the method embodiment for relevant points.

Fig. 6 is a block diagram of an electronic device according to an embodiment of the present application. The electronic device includes a processing component 622 that further includes one or more processors, and memory resources, represented by memory 632, for storing instructions, such as application programs, that are executable by the processing component 622. The application programs stored in memory 632 may include one or more modules that each correspond to a set of instructions. Further, the processing component 622 is configured to execute instructions to perform the above-described methods.

The electronic device may also include a power component 626 configured to perform power management of the electronic device, a wired or wireless network interface 650 configured to connect the electronic device to a network, and an input/output (I/O) interface 658. The electronic device may operate based on an operating system stored in memory 632, such as Windows Server, MacOS XTM, UnixTM, LinuxTM, FreeBSDTM, or the like.

According to yet another embodiment of the present application, there is also provided a computer-readable storage medium having stored thereon a computer program/instructions which, when executed by a processor, implement the steps in the task processing method according to any one of the above-mentioned embodiments.

According to yet another embodiment of the present application, there is also provided a computer program product including a computer program/instructions, which when executed by a processor, implement the steps in the task processing method according to any one of the above embodiments.

The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts in the embodiments are referred to each other.

As will be appreciated by one of skill in the art, embodiments of the present application may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

Embodiments of the present application are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

While preferred embodiments of the present application have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the true scope of the embodiments of the application.

Finally, it should also be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.

The task processing method, the electronic device, the storage medium, and the computer program product provided by the present application are introduced in detail, and a specific example is applied to illustrate the principles and embodiments of the present application, and the description of the embodiment is only used to help understand the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. A method for processing a task, the method comprising:

providing the target operation result to the CA.

2. The method of claim 1, wherein instructing the CPU operator and the coprocessor to run their assigned subtasks to obtain a target run result comprises:

instructing a CPU memory to transfer data, which are dependent on subtasks allocated to the coprocessor, in the CPU memory to the coprocessor through a secure data channel between the CPU and the coprocessor;

instructing the coprocessor to run the distributed subtasks based on the data transferred by the CPU memory to obtain a first running result; and instructing the CPU arithmetic unit to run the distributed subtasks based on the subtask-dependent data stored in the CPU memory to obtain a second running result;

instructing the coprocessor to pass the first operation result to the CPU operator through the secure data channel;

instructing the CPU operator to generate a target operation result based on the first operation result and the second operation result.

3. The method of claim 2, wherein the secure data channel is constructed by:

creating a target shared memory space on the CPU memory;

4. The method according to any of claims 1-3, wherein said distributing said at least two subtasks to a CPU operator and a coprocessor, respectively, comprises:

and respectively distributing the at least two subtasks to a CPU arithmetic unit and a coprocessor according to the service requirements of the subtasks.

5. The method of any of claims 1-4, wherein there are no logical dependencies between subtasks of the target task; or, a logical dependency relationship exists between partial subtasks of the target task, and a logical dependency relationship does not exist between partial subtasks.

6. The method of claim 5, wherein the target task is a face recognition task, and wherein the subtasks of the face recognition task include: a face key point detection subtask, a living body detection subtask and a face feature extraction subtask;

the allocating the at least two subtasks to the CPU operator and the coprocessor, respectively, includes:

distributing the face key point detection subtask to a CPU, and distributing the face feature extraction subtask and the living body detection subtask to the CPU and a coprocessor respectively; alternatively, the first and second electrodes may be,

and distributing the face key point detection subtask to a CPU (central processing unit), and distributing the face feature extraction subtask and the living body detection subtask to different coprocessors respectively.

7. The method of any of claims 1-6, wherein the coprocessor comprises at least one of: GPU, DSP and NPU.

8. An electronic device comprising a memory, a processor and a computer program stored on the memory, wherein the processor executes the computer program to implement the method of any of claims 1-7.

9. A computer-readable storage medium on which is stored a computer program/instructions, characterized in that the computer program/instructions, when executed by a processor, implement the method of any one of claims 1-7.

10. A computer program product comprising computer programs/instructions, characterized in that the computer programs/instructions, when executed by a processor, implement the method of any of claims 1-7.