CN115085745A

CN115085745A - VDE-TER-based digital diversity communication system

Info

Publication number: CN115085745A
Application number: CN202210493723.4A
Authority: CN
Inventors: 张钦; 周怡靖; 李海; 侯舒娟; 武毅
Original assignee: Beijing Institute of Technology BIT
Current assignee: Beijing Institute of Technology BIT
Priority date: 2022-04-27
Filing date: 2022-04-27
Publication date: 2022-09-20
Anticipated expiration: 2042-04-27
Also published as: CN115085745B

Abstract

The invention discloses a digital diversity communication system based on VDE-TER, which is used for realizing ship-shore communication according to a VDES G1139 protocol. The transceivers of the communication system all provide various modulation modes (pi/4-QPSK and 16QAM), provide various communication bandwidths (100KHz and 25KHz), the transmission rate can reach 307.2kbps and 76.8kbps theoretically, and the communication modes can be switched at any time through an upper computer interface in the using process, and the performance of the receiver is improved by adopting the diversity reception technology so as to adapt to the communication requirements under different scenes. The invention carries out the design of a communication system based on the VDES protocol requirement, has the advantages of multiple modulation modes, selectable communication bandwidth, good performance index of a transceiver and the like, reduces the resource occupation by the FPGA design, and can bear the requirement of the communication service between VDES offshore ships and shore.

Description

VDE-TER-based digital diversity communication system

Technical Field

The invention relates to the technical field of water communication, in particular to a digital diversity communication system based on VDE-TER.

Background

VDES is mainly used for carrying on the automatic recognition of the vessel in the field of the water mobile business, on the basis of keeping AIS function of the original maritime communication system, VDES system has introduced the function of special application message (ASM) and very high frequency data exchange function of broadband (VDE), has strengthened the communication capacity of the sea vessel, has realized the communication between ship-ship, ship-bank, ship-satellite and satellite-ground, and because of the new proposed protocol standard, in the communication between satellite and vessel, reserve the sufficient frequency spectrum resource, have laid the foundation for the expansion of more businesses in the future. With the rapid development of modern information communication technology and radio technology, intellectualization, fusion and digitization are the development directions of the current water radio communication. If the current overwater communication channel is adjusted according to a VDES protocol, the pressure of AIS data transmission in the existing communication face is greatly reduced, the utilization rate and the communication capacity of a frequency band can be improved, the ship navigation safety is guaranteed to a greater extent, the future application can be combined with a Beidou satellite navigation system, the electronic chart display and information system can be applied to intelligent ships or unmanned ships, real-time transmission and updating can be carried out on the electronic chart display and information system, and the power is provided for ship traffic service, e-navigation strategies and the like.

At present, south Africa Stone Tree company develops VDES terminal products, and performs land performance actual measurement of VDE-TER and compatibility test with AIS in combination with Canada; the company CML Microsystems, england, developed a VDES development kit VDES1000 based on software radio; research and development of VDES ship-borne prototype machines are carried out by Japan Wireless corporation (JRC), and point-to-point experiments and broadcast experiments are completed; the Beijing Kadun environmental corporation completes the development of a VDES base station hardware test platform and tests on the sea; the Shanghai assist zhen science and technology Co., Ltd develops a VDES base station test platform and performs reception performance tests in water. Overall, the international standards of VDES are basically dominated by foreign teams, and domestic related institutions and colleges have no significant gap in VDES technology development and commercialization, but most products are still in the stage of development and testing.

The key technology of the VDE-TER system as a communication system is the research of related technologies such as signal modulation and demodulation, signal synchronization and the like. In 2015, Zhu wenlong studied the modulation and demodulation technology of 16QAM in VDE-TER in "the modulation and demodulation algorithm and implementation research of VDES", and implemented based on FPGA, and proposed the possibility of using OFDM system in VDE-TER; in 2018, Huangjian Lin proposes a carrier synchronization technology suitable for a VDE-TER system in VDE-TER carrier synchronization technology research, and adopts a method of combining frequency coarse synchronization and fine synchronization. In 2020, the OFDM modulation system is applied to a VDES system in "OFDM synchronization technology research based on training sequences in VDES" by ruxue, and relevant simulation and research are performed on the synchronization technology; in 2021, hujie proposed a method for implementing 16QAM transceiving and processing in VDE-TER based on software radio technology in "research on VDES modulation and demodulation for vessels based on software radio"; van Jiahui in VDES intermediate frequency offset estimation and phase tracking algorithm research provides a key algorithm for frequency offset estimation and phase tracking when 16QAM receives signals in VDE-TER.

The existing VDE-TER communication system is still in a research, development and test stage, and professional VDES technology development boards are few, such as VDES1000, but the VDE-TER communication system is expensive; most of VDE-TER products in other research and development tests only realize a single modulation mode and a single data rate required in a VDE-TER standard protocol, and cannot switch the modulation mode and the communication bandwidth under different channel environments; the products of multi-rate and multi-modulation mode have the problems of more hardware resource occupation, large processing delay and the like; the developed products are generally base stations or terminals, system research and development is not carried out on the base stations and the terminals, the performance of a developed communication system is not compared with various performances required by a VDE-TER standard protocol, and whether the performance required by the protocol is met is unclear.

Therefore, a communication system capable of adapting to the VDE-TER standard protocol is currently lacking.

Disclosure of Invention

In view of the above, the present invention provides a digital diversity communication system based on VDE-TER, which is used for implementing ship-shore communication according to the VDEs G1139 protocol.

In order to achieve the purpose, the technical scheme of the invention is as follows: a VDE-TER based digital diversity communication system comprises a transmitter and a receiver; and a set of digital diversity communication system is respectively arranged on the terminal and the base station.

The transmitter consists of a transmitter link layer, a transmitter physical layer and transmitter hardware equipment; the transmitter link layer is used for sending data by an upper computer; the physical layer of the transmitter comprises a RAM data buffer module, an 1/2Turbo coding module, a 3/4Turbo coding module, a 19.2ksps data framing module, a 76.8ksps data framing module, a first time base control module, a second time base control module, a modulation module, an interpolation module and an up-conversion module; the transmitter hardware equipment comprises a DAC, a power amplifier and an antenna which are connected in sequence.

After a transmitter link layer issues data, the issued data enters an RAM data cache module, the RAM data cache module outputs two paths of data to be respectively accessed into an 1/2Turbo coding module and a 3/4Turbo coding module, the 1/2Turbo coding module outputs to be respectively accessed into a 19.2ksps data framing module and a 76.8ksps data framing module, the 19.2ksps data framing module outputs to be connected with a first time base control module, the 76.8ksps data framing module outputs to be accessed into a second time base control module, the first time base control module and the second time base control module are both accessed into a modulation module, and the output end of the modulation module is sequentially connected with an interpolation module and an up-conversion module.

The receiver consists of a receiver link layer, a receiver physical layer and receiver hardware equipment; the hardware equipment of the receiver consists of a double receiving antenna, a low noise amplifier, a numerical control attenuator and an ADC which are connected in sequence; the physical layer of the receiver is composed of a JESD204b interface, a first receiving channel, a second receiving channel, a pi/4-QPSK demodulation module, a 16QAM demodulation module, a 1/2Turbo decoding module and a 3/4Turbo decoding module.

The receiver receives signals through the double receiving antennas, and the conversion of analog-digital information is realized through the double-channel ADC through the double-channel low-noise amplifier and the hardware equipment of the digital control attenuator; after passing through a JESD204b interface communicated with an ADC, a received signal is divided into two paths, the two paths of signals respectively enter a first receiving channel and a second receiving channel, the two paths of signals are superposed after being processed by corresponding signals, and the superposed signals respectively enter a pi/4-QPSK demodulation module and a 16QAM demodulation module for demodulation operation, wherein the output of the pi/4-QPSK demodulation module is accessed to a 1/2Turbo decoding module, and the output of the 16QAM demodulation module is accessed to a 3/4Turbo decoding module; 1/2Turbo decoding module and 3/4Turbo decoding module input into receiver link layer as upper computer reading data.

Further, the 1/2Turbo coding module is composed of a first CRC calculation module, a first Turbo coding module, and a first scrambling module, which are connected in sequence, and performs CRC calculation, Turbo coding, and scrambling operations on the transmitted data, respectively.

1/4 the Turbo coding module uses the second CRC calculation module, the second Turbo coding module and the second scrambling module to perform CRC calculation, Turbo coding and scrambling operation on the transmitted data respectively.

Further, both the 19.2ksps data framing module and the 76.8ksps data framing module are framing modules.

The framing module is used for forming a complete frame by the issued data and other parts of the frame structure, namely the rising and falling protection time, the training sequence, the Link ID and the protection time specified by the VDES protocol according to the frame structure given by the VDES, and transmitting the data of the complete frame obtained by framing to the next module.

According to different data rates and different frame lengths, the framing module is divided into two paths to be respectively realized, namely a 19.2ksps data framing module and a 76.8ksps data framing module; the two data framing modules have consistent structures and respectively comprise a double-port RAM and two ROMs, the length of each RAM is twice that of the corresponding frame, each RAM and each ROM realize framing of one modulation mode, the RAM realizes the function of ping-pong RAM cache, issued data are alternately stored according to one frame and one frame, the purpose is to continuously send the data to a next-level data processing module, the ROM stores synchronous sequences and data used for judging information such as modulation modes and the like by a receiving end, and after the data are read from the ROM, the data read from the ping-pong RAM and the data are well grouped according to the frame structure and sent to the next module.

Furthermore, the first time base control module and the second time base control module are both time base control modules, the time base control module gives the current time slot number and the current symbol position in a frame in the transmitting process according to the relationship between the symbol rates and the rate of the clock and the time slot counting mode specified by the VDES protocol, and the symbol position controls the address of the ping-pong RAM to read out the data according to the correct rate, thereby facilitating the processing and control of the relevant parts of the frame and the time slot by the modulation module; the time base control module arranged on the terminal needs to keep the time slot synchronous with the base station, so the time slot number and the counter are counted according to the receiving and capturing condition of the broadcast packet, and the counting of the current time slot is continuously adjusted due to the frequency difference and the Doppler frequency shift of the carrier waves between the equipment, thereby realizing the synchronization of the time slot of the terminal and the base station.

Furthermore, the outputs of the first time base control module and the second time base control module both enter a modulation module, after the data stream enters the modulation module, the modulation module performs different control on the data according to the current modulation mode and data rate, and performs two-bit mapping pi/4-QPSK or four-bit mapping 16QAM on the bit stream data according to a constellation diagram specified by a protocol to obtain signals of two paths I and Q.

Before the interpolation module, the I path and Q path rate is 19.2ksps or 76.8ksps, when the interpolation operation is carried out, the FIR filter and the polyphase filter are used for design, and the interpolation method is as follows: the 19.2ksps data rate mode shares FIR filters with interpolation multiples of 16, 5, and 4 with the 76.8ksps data rate mode, except that the 19.2ksps data rate mode has one more stage of a 4-fold interpolated FIR filter.

Further, in the receiver, the receiving channel includes a first receiving channel and a second receiving channel.

The receiving channel comprises two processing links, namely a 19.2ksps data processing link and a 75.8ksps data processing link, and the two processing links are respectively suitable for processing 19.2ksps data and 76.8ksps data and have consistent processing modes.

The processing modes of the 19.2ksps data processing link and the 75.8ksps data processing link are as follows:

the signal is subjected to a digital down-conversion module, the down-converted signal is subjected to signal extraction through an extraction module, on one hand, power statistics is carried out on the extracted signal, and the real-time adjustment of the power of the signal is realized through the attenuation value of the numerical control attenuator corresponding to the current power value; and on the other hand, the extracted signal is subjected to frequency offset correction, phase offset correction and bit synchronization, and pi/4-QPSK modulation or 16QAM modulation is performed after the processing to obtain the output of the receiving channel.

Has the advantages that:

1. the invention provides a VDE-TER digital diversity communication system based on a VDES communication protocol standard, which is realized based on an FPGA and comprises a base station and terminal equipment. The communication system is used for realizing ship-shore communication according to a VDES G1139 protocol. The transceivers of the communication system all provide various modulation modes (pi/4-QPSK and 16QAM), provide various communication bandwidths (100KHz and 25KHz), the transmission rate can reach 307.2kbps and 76.8kbps theoretically, and the communication modes can be switched at any time through an upper computer interface in the using process, and the performance of the receiver is improved by adopting the diversity reception technology so as to adapt to the communication requirements under different scenes.

2. The invention carries out the design of the communication system based on the VDES protocol requirement, has the advantages of multiple modulation modes, selectable communication bandwidth, good performance index of the transceiver and the like, reduces the resource occupation by the FPGA design, and can bear the requirement of the communication service between the VDES offshore ship and the shore.

3. According to the VDES standard protocol, the VDE-TER uses a VHF frequency band to transmit in three bandwidths of 25KHz, 50KHz and 100KHz, the modulation modes to be adopted are pi/4-QPSK, 16QAM, 8PSK and the like, the optional modes of the VDE-TER are a pi/4-QPSK modulation mode with 25KHz bandwidth, a 16QAM modulation mode with 100KHz bandwidth and a pi/4-QPSK modulation mode with 100KHz bandwidth, and the other modes are optional modes. The invention provides three VDE-TER optional modes, 16QAM is more easily influenced by noise compared with pi/4QPSK, but the bandwidth occupancy rate is very small, the frequency spectrum utilization rate is very high, the throughput of a channel can be ensured under the condition of better channel condition, and the bandwidth and the modulation mode are selected according to the channel environment, thereby realizing the data communication function between ships and between ships.

4. In order to improve the performance of a receiver of a communication system and reduce noise interference, the digital diversity communication system based on the VDE-TER standard protocol adopts a diversity receiving technology, realizes dual-channel processing of a receiver signal under limited hardware resources, provides a frequency deviation correction and a phase deviation correction algorithm which are simultaneously suitable for pi/4-QPSK and 16QAM, and reduces the requirement on the hardware resources.

Drawings

FIG. 1 is a flow chart of physical layer data framing;

FIG. 2 is a block diagram of a VDE-TER transmitter design and implementation;

FIG. 3 is a schematic diagram of an interpolation module;

FIG. 4 is a block diagram of a VDE-TER receiver design and implementation;

FIG. 5(a) is a block diagram of a 19.2ksps link design and implementation for a receive channel in a VDE-TER receiver;

FIG. 5(b) is a block diagram of a link design and implementation of a receive channel 76.8ksps link in a VDE-TER receiver;

FIG. 6 is a schematic diagram of a phase-locked loop tracking frequency offset correction algorithm for pi/4-QPSK modulation;

fig. 7 is a schematic diagram of a sliding window fine frequency offset correction algorithm suitable for 16QAM modulation.

Detailed Description

The invention is described in detail below by way of example with reference to the accompanying drawings.

The invention is used as a set of digital communication system, mainly provides the functions of the physical layer in the VDES system, such as signal modulation and demodulation, signal coding and decoding, and the like, and completes the data exchange with the link layer, the digital communication system is realized based on the FPGA design, the functions comprise a transmitter and a receiver, the design of the transmitter and the receiver is different for the base station and the terminal equipment, and the design and the realization method of the transmitter and the receiver are respectively introduced.

According to the requirements of VDE-TER standard protocol, the physical layer part of the transmitter is realized according to the physical layer data framing flow chart shown in figure 1, after the data is issued by the link layer, the data is filled with 0 firstly, after CRC calculation, Turbo coding, scrambling and modulation, the data is subjected to other processing and then is transmitted by hardware equipment such as an amplifier, an antenna and the like, and according to the flow chart shown in figure 1, the transmitter is designed and realized as shown in figure 2 for realizing the pi/4-QPSK modulation mode with the bandwidth of 25KHz, the 16QAM modulation mode with the bandwidth of 100KHz and the pi/4-QPSK modulation mode with the bandwidth of 100KHz at the same time.

As shown in fig. 2, the function of the physical layer is implemented based on the FPGA, the data to be transmitted is sent to the physical layer by the upper computer according to the interface protocol, and finally, an end mark indicating that one frame of data is written is given, and control words required by the FPGA (such as the modulation mode and the data rate of this transmission) and the hardware chip (such as the a/D, D/a chip) are sent at the same time.

The FPGA part firstly caches the data with one frame length by using a dual-port RAM, controls the length of the data read from the RAM according to a control word of a mark modulation mode and a data rate, and sends the data to a coding module.

If the modulation mode is pi/4-QPSK modulation, the data is sent to 1/2Turbo coding module, because two data rates can be selected under pi/4-QPSK modulation mode, and further the data length of a frame is different, the length of 1/2Turbo coding is adjusted by the coding module according to the flag modulation mode issued by the upper layer and the control word of the data rate, so that the common coding module with different data rates is realized to save FPGA resources; if the modulation is 16QAM, the data is sent to 3/4Turbo coding module. In addition to the coding including Turbo coding, the coding module also implements CRC check and scrambling on data before and after Turbo coding according to the flowchart in fig. 1. The information stream then enters the framing module.

The framing module has the main functions of forming a complete frame by the transmitted data and other parts of the frame structure, namely the rising and falling protection time, the training sequence, the Link ID and the protection time (specified by a VDES protocol) according to the frame structure given by the VDES, and transmitting the data of the complete frame to the next module (a time base control module for time slot control). Because different data rates and different frame lengths, the framing module is divided into two paths to be respectively realized. The 19.2ksps data framing module comprises a double-port RAM and two ROMs, wherein the length of each RAM is twice as long as that of each ROM, each RAM and each ROM realize framing of a modulation mode, the RAM realizes the function of ping-pong RAM cache, issued data are stored alternately according to one frame and one frame, the purpose is to continuously send the data to a next-stage data processing module, the ROMs store synchronous sequences and data used for a receiving end to judge information such as the modulation mode and the like, and after the data are read from the ROMs, the data read from the ping-pong RAMs and the data are sent to the next module according to a frame structure.

In order to control the data rate, a time base control module is designed and realized, which gives the current time slot number and the current symbol position in a frame in the transmission process according to the relation between the symbol rates and the clock rate and the time slot counting mode specified by the VDES protocol, and the symbol position controls the address of the ping-pong RAM to read out the data according to the correct rate, thereby facilitating other modules (such as a modulation module) to process and control the relevant parts of the frame and the time slot. The design and implementation of the time base control modules of the base station and the terminal are not completely the same, the terminal needs to keep the time slot synchronous with the base station, so the time slot number and the counter can be set according to the receiving and capturing condition of the broadcast packet, and the counting of the current time slot can be continuously adjusted due to the frequency difference of the carriers between the devices, the Doppler frequency shift and other factors, so the time slot synchronization of the terminal and the base station is realized.

After the data stream enters the modulation module, the modulation module controls the data differently according to the current modulation mode and the data rate, and performs two-bit mapping (pi/4-QPSK) or four-bit mapping (16QAM) on the bit stream data according to a constellation diagram specified by a protocol to obtain signals of two paths of an I path and a Q path.

The I and Q way rates are 19.2ksps or 76.8ksps before the interpolation block, and the sampling rate of the D/A used on the hardware platform is 983.04 MSa/s. To achieve rate matching, the digital signal needs to be interpolated before the DAC processes the digital signal. When the interpolation operation is performed, the FIR filter and the polyphase filter can be used for design, and the purposes of shaping filtering, interpolation and anti-image filtering are realized. Interpolation method as shown in fig. 3, the 19.2ksps data rate mode and the 76.8ksps data rate mode share FIR filters with interpolation multiples of 16, 5, and 4 to save FPGA resources, except that the 19.2ksps data rate mode requires one more stage of FIR filter with 4 times interpolation.

After a series of interpolation is carried out on data, because the data rate is the same as the FPGA main clock rate, 8 times of interpolation is carried out in a multi-phase up-conversion mode to obtain data matched with the DAC rate, in order to realize digital up-conversion, the DDS performs complex multiplication with signals according to frequency control words and phase accumulation words configured on an upper layer, sinusoidal signals are obtained and then are subjected to complex multiplication through a complex multiplier, the real parts of the signals are input to the DAC, the signals are amplified through a power amplifier, and the signals are transmitted through an antenna.

The receiver designed and realized by the invention is shown in figure 4, realizes the receiving of three modes (a pi/4-QPSK modulation mode with 25KHz bandwidth, a 16QAM modulation mode with 100KHz bandwidth and a pi/4-QPSK modulation mode with 100KHz bandwidth) signals in a VDE-TER system through dual-channel diversity reception, and can adjust the signal mode according to the power of the current signal to realize rate self-adaptation.

Firstly, a receiver receives signals through double antennas, and conversion of analog-digital information is realized through a double-channel ADC (analog-to-digital converter) through a double-channel low-noise amplifier and hardware equipment of a digital control attenuator. After passing through a JESD204b interface communicated with an ADC, received data is divided into two paths, namely a receiving path 1 and a receiving path 2, and the two paths of signals are superposed after being processed by corresponding signals, wherein the diversity is adopted because the amplitude is superposed when the two paths of signals are the same in phase, the power value can be enlarged by 4 times, and the noise is only enlarged by 2 times through power superposition, so that the 3dB signal-to-noise ratio gain is obtained, and the multi-path fading can be resisted due to the adoption of double-antenna receiving.

In the dual-channel reception, the signals of the dual channels are multiple copies of the same signal, and the processing modes are basically consistent, so in design and implementation, the signal processing part of the receiver of the invention is mainly divided into two modules, namely a receiving channel 1 and a receiving channel 2. Since the signal of the VDE-TER system is bursty and the rate of the signal is unknown when the signal is received, in order to adapt to the 19.2ksps and 76.8ksps signals, each channel is divided into two different data processing links according to the rate, and the data processing manner between each link is basically consistent, so the main part of the data processing is described by taking the 76.8ksps data processing link in the receiving channel 1 as an example. FIG. 4 is a block diagram of a VDE-TER receiver design and implementation, and FIG. 5(a) is a block diagram of a 19.2ksps link of a receiving channel in the VDE-TER receiver; FIG. 5(b) is a block diagram of a link design and implementation of a receive channel 76.8ksps in a VDE-TER receiver.

In order to process the signal, firstly, the signal is subjected to digital down-conversion to remove the carrier wave, the DDS is used for generating a carrier frequency signal, and the real part and the imaginary part of the carrier frequency signal are respectively subjected to complex multiplication with the received signal, so that the real part and the imaginary part of the signal can be obtained. In order to realize the automatic gain control of the system, the power statistics is carried out on the signals at the same time, and the real-time adjustment of the power of the signals is realized through the attenuation value of the numerical control attenuator corresponding to the current power value. In order to facilitate signal processing, the extraction module reduces the signal rate (the extraction multiples of FIR filters passed by processing links with different data rates are different), each symbol has 16 sampling points after the signal in each data processing link is extracted, and the signal still has frequency offset due to the frequency difference of the carrier and the influence of doppler frequency shift, and then the signal is subjected to frequency offset correction, phase offset correction and bit synchronization.

According to the standard protocol of VDE-TER, although the modulation modes of load data in different modes are different, the LINK ID of the synchronous sequence and the information of the identification frame are both pi/4-QPSK modulation modes, so in order to save FPGA resources, when each LINK processes pi/4-QPSK modulation or 16QAM, part of a data caching module, a coarse frequency offset estimation module, a synchronous sequence frequency offset compensation module, a bit synchronization module and the like can be shared, and a fine frequency offset estimation module is respectively designed and realized.

Because the modulation mode of the training sequence is pi/4-QPSK modulation, and the signal information of the modulation mode is related by the phase of the signal and is not influenced by the amplitude, amplitude normalization processing is firstly carried out on the data. When the coarse frequency offset estimation is carried out on the signal, the data of 27 training sequences are taken at the same time for calculation and estimation, but the data is in a streaming type, and a new data comes every 100 clocks, so that the data is cached by using a dual-port RAM (random access memory), and the subsequent data taking calculation is convenient.

According to the principle that an optimal sampling point is selected for each symbol, 27 received data are read out from a buffer RAM, and because a synchronization sequence is a double-Barker code sequence, a large amount of simulation and actual tests are carried out, and a low-complexity universal frequency offset estimation algorithm based on the double-Barker code is adopted by a coarse frequency offset estimation module. The specific method is as follows. Now, assume that timing synchronization is completed and the receiving end has extracted the training sequence. According to the modulation rule of pi/4-QPSK, the synchronization sequence is denoted as t, t (i) ± 1, and the training sequence after local modulation is expressed as

The training sequence received by the receiver is represented as:

where r denotes the received training sequence, f _d Which represents the frequency offset, is,

the phase offset introduced for the channel, T denotes the symbol period, and n (j) is the channel noise.

In VDE-TER communication, pi/4-QPSK is alternately mapped between star and square constellations. The constellation of each bit mapping of the 13-bit barker code and its inverse is different. To simplify the calculation, the training sequence is uniformly converted into a star constellation before being operated. The method of conversion is simple, as follows:

the traditional double-barker code frequency offset estimation algorithm needs to utilize the special data characteristics and good autocorrelation of the mutual inverse code of double barker codes to obtain the phase difference of 13 points apart and then average to obtain the frequency offset estimation value, so as to simplify the calculation, save the FPGA resource and make the method have good universality, the invention provides and realizes the low-complexity universal frequency offset estimation algorithm based on the double barker codes, the specific method is to abandon the last 3 groups of 13 groups of barker codes, and average the phase difference of two groups of data of 2 nd to 11 th symbols and 18 th to 27 th symbols in 27 training sequences, because the local modulation phases of the two groups of symbols are inconsistent, the phase rotation is firstly carried out on the symbols with inconsistent phases in one group to form new two groups of double barker codes, as shown below:

r _bark1 (k)＝r _new (k)k＝17,18,...,26

the phase difference separated by 16 points is

Averaging the phase differences 16 points apart to obtain an estimated coarse frequency offset value,

in FPGA implementation, division by taking 16 as divisor can be directly realized by shifting, and two rotation phase operations can be combined into one completion, so that resources and computational complexity are saved to a great extent compared with a double-Barker code frequency offset estimation algorithm.

After obtaining the coarse frequency offset estimation value, performing coarse frequency offset correction on 27 symbol points received in a cache RAM, and caching a plurality of coarse frequency offset values by using the RAM because the signals are not subjected to bit synchronization at the moment and the starting position points and the optimal sampling points of the signals are unknown.

In the bit synchronization module, in order to determine the starting position point and the optimal sampling point of a signal, the received signal is continuously correlated with a local sequence, if a synchronization sequence is received, a peak value area appears in a correlation value, when the correlation value is higher than a set threshold value, data is cached, the value with the maximum correlation result in the data higher than the threshold value is selected as the optimal sampling point, a rule of extracting one point according to each symbol is adopted, data is obtained from a cache RAM, and then a next complete packet of data is obtained. Such an algorithm achieves bit synchronization of VDES such burst communication. In order to obtain the initial phase offset introduced by the channel, the phase angle can be directly obtained by calculating the cross-correlation result value, the result is the same as the coarse frequency offset value, a plurality of values are cached in the RAM, and after the optimal sampling point and the signal starting position point are determined, the two parameter values can be provided for the fine frequency offset estimation module to carry out further signal correction.

After the received signal is subjected to coarse frequency compensation and initial phase offset compensation, a small frequency offset usually remains due to the influence of the coarse frequency compensation precision, and the frequency offset can gradually rotate a constellation diagram, so that the error rate of signal judgment is reduced. Therefore, the invention adopts a phase-locked loop tracking frequency offset correction algorithm aiming at pi/4-QPSK modulation and adopts a sliding window frequency offset correction algorithm aiming at 16QAM modulation to perform fine frequency offset/phase offset compensation on signals.

First, a phase-locked loop tracking frequency offset correction algorithm applied to pi/4-QPSK modulation is introduced, as shown in fig. 6, and the algorithm is improved based on a DD phase offset estimation algorithm.

Reading parameters from a coarse frequency offset cache RAM and an initial frequency offset cache RAM by a first signal value after bit synchronization to perform coarse frequency offset and phase offset correction, then demodulating and judging the point to obtain a standard position point on a constellation diagram, solving a phase angle deviation between a received signal value and the standard position value, wherein the phase angle deviation phase _ adj is caused by residual frequency offset, and performing phase-locked loop tracking on the phase _ adj through a second-order loop filter, as shown in the following formula,

phase_temp(n)＝phase_temp(n-1)·exp(-j·C2·phase_adj(n))

phase_acc(n)＝phase_temp(n)·exp(-1j·C1·phase_adj(n))

and feeding back the phase _ acc obtained each time for the frequency offset correction of the next signal point, thereby realizing the frequency offset and phase offset correction of the pi/4-QPSK modulation signal.

After the LINK ID after the training sequence is recovered, the modulation mode and the signal rate of the current signal can be determined, each LINK gives the recovery result of the LINK ID to an upper computer, and whether the LINK continues to perform subsequent signal processing, such as demodulation and decoding, is determined. If the modulation is pi/4-QPSK modulation, the load data is recovered by continuously adopting a phase-locked loop tracking frequency offset correction algorithm, and if the modulation is 16QAM, the signal is recovered by adopting a sliding window frequency offset correction algorithm.

Next, a sliding window fine frequency offset correction algorithm suitable for 16QAM modulation is described. Assuming that the signals after coarse and initial phase offset corrections are expressed as follows:

wherein, Δ f _d 'is a small residual frequency offset, and Δ φ' is a small residual phase offset, and the effect of the residual frequency offset on demodulation can be considered as the effect of the residual phase offset on demodulation, so the residual phase offset can be expressed as

Δφ”＝2πΔf _d 'mT+Δφ'

Further comprises

r(m)＝b(m)·e ^jΔφ″ +n(m)

Now, the residual delta phi' is subjected to phase deviation removing processing, and fine frequency deviation correction is also realized.

A sliding window fine frequency offset correction algorithm suitable for 16QAM modulation is shown in fig. 4, after bit synchronization is completed, the position where an effective signal starts is determined, when a first symbol after a training sequence is received, a sliding window fine frequency offset correction algorithm is performed, for the received first symbol, coarse frequency offset and residual phase offset are compensated and demodulated and mapped, a demodulation mapping value and 27 local training sequence groups are local packet data, a window width is set to 28, the received signal also takes 27 received training sequences and the first symbol group as a received signal packet, residual phase offset is solved according to a method for solving initial phase offset, specifically, data normalization is performed to reduce the influence of amplitude value on calculation, then two packet data are cross-correlated and phase angle is solved to obtain residual phase offset, coarse frequency offset and residual phase offset compensation are performed on a second received symbol, and then demodulation mapping is performed, and outputting the data to the next module, feeding back the data to the front road for the local data packet of the sliding window group, and so on. Similar to making a window with the width of 28 symbols on the whole frame of data, sliding from the initial position of the synchronous sequence to the end of the data one by one, using the demodulation signal as the local sequence in the window, making correlation between the received signal and the local sequence to realize the phase deviation removal processing of the data, and keeping the tracking state of the phase to achieve the effect of fine frequency deviation correction. It should be noted that when the received signal is LINK ID, the demodulation mapping should be performed according to pi/4-QPSK, and after the LINK ID is determined, if the payload data is modulated by 16QAM, the payload data is demodulated and mapped according to 16 QAM.

FIG. 7 is a sliding window fine frequency offset correction algorithm suitable for 16QAM modulation

At this time, each data link completes the recovery of all data of one frame, and carries the basic information of the frame data, such as modulation mode and data rate, and needs to complete the combination of two paths of data received by diversity before demodulating the data. The power statistic value of the signal is needed to be counted by a power statistic module, and the statistic basis of the module is that the sum of the square of the amplitude of the I path signal and the square of the amplitude of the Q path signal is in direct proportion to the signal power. The algorithm for combining the two-channel data is to use the signal power value as the weight, obtain a combined I-channel signal value by the superposition of the two-channel I-channel signals, obtain a combined Q-channel signal value by the superposition of the two-channel Q-channel signals, use the new I, Q signal value to complete the mapping and demodulation of the constellation diagram, further complete the decoding which is inverse to the transmission link, and recover the original bit data.

When the decoding is finished, the upper computer reads the current modulation mode and the data rate, reads data according to the specified frame length, determines the information mode applicable to the current channel condition according to the current power statistic value, and feeds back the information to the transmitting party for mode adjustment if adjustment is needed, so as to realize the self-adaptation of the information rate.

In summary, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A digital diversity communication system based on VDE-TER, comprising a transmitter and a receiver; a set of digital diversity communication system is respectively arranged on the terminal and the base station;

the transmitter consists of a transmitter link layer, a transmitter physical layer and transmitter hardware equipment; the transmitter link layer is used for sending data by an upper computer; the physical layer of the transmitter comprises a RAM data buffer module, an 1/2Turbo coding module, a 3/4Turbo coding module, a 19.2ksps data framing module, a 76.8ksps data framing module, a first time base control module, a second time base control module, a modulation module, an interpolation module and an up-conversion module; the transmitter hardware equipment comprises a DAC, a power amplifier and an antenna which are connected in sequence;

the receiver consists of a receiver link layer, a receiver physical layer and receiver hardware equipment; the receiver hardware equipment consists of a double receiving antenna, a low noise amplifier, a numerical control attenuator and an ADC which are connected in sequence; the physical layer of the receiver is composed of a JESD204b interface, a first receiving channel, a second receiving channel, a pi/4-QPSK demodulation module, a 16QAM demodulation module, a 1/2Turbo decoding module and a 3/4Turbo decoding module.

2. The digital diversity communication system of claim 1, wherein after the transmitter link layer transmits data, the transmitted data enters a RAM data buffer module, the RAM data buffer module outputs two paths of data to access 1/2Turbo coding module and 3/4Turbo coding module respectively, the 1/2Turbo coding module outputs access 19.2ksps data framing module and 76.8ksps data framing module respectively, the 19.2ksps data framing module outputs connect a first time base control module, the 76.8ksps data framing module outputs access a second time base control module, the first time base control module and the second time base control module both access a modulation module, the modulation module output end connects an interpolation module and an up-conversion module in sequence;

3. The digital diversity communication system according to claim 1 or 2, wherein the 1/2Turbo coding module is composed of a first CRC calculation module, a first Turbo coding module and a first scrambling module connected in sequence, and performs CRC calculation, Turbo coding and scrambling operations on the transmitted data respectively;

the 3/4Turbo coding module is composed of a second CRC calculation module, a second Turbo coding module and a second scrambling module, and is used for performing CRC calculation, Turbo coding and scrambling operation on the transmitted data respectively.

4. The digital diversity communication system of claim 1 or 2, wherein the 19.2ksps data framing module and the 76.8ksps data framing module are both framing modules;

the framing module is used for forming a complete frame by the issued data and other parts of the frame structure, namely the rising and falling protection time, the training sequence, the LinkID and the protection time specified by the VDES protocol according to the frame structure given by the VDES, and transmitting the data of the complete frame obtained by framing to the next module;

5. The digital diversity communication system according to claim 4, wherein the first time base control module and the second time base control module are time base control modules, the time base control module gives the number of the current time slot and the symbol position in the current frame during the transmission process according to the relationship between the symbol rates and the rate of the clock and the time slot counting mode specified by the VDES protocol, the symbol position controls the address of the ping-pong RAM to read out the data at the correct rate, which facilitates the modulation module to process and control the frame and the time slot related part; the time base control module arranged on the terminal needs to keep the time slot synchronous with the base station, so the time slot number and the counter are counted according to the receiving and capturing condition of the broadcast packet, and the counting of the current time slot is continuously adjusted due to the frequency difference and the Doppler frequency shift of the carrier waves between the equipment, thereby realizing the synchronization of the time slot of the terminal and the base station.

6. The digital diversity communication system according to claim 1, 2 or 5, wherein the outputs of the first time base control module and the second time base control module enter the modulation module, after the data stream enters the modulation module, the modulation module performs different control on the data according to the current modulation mode and the data rate, and performs two-bit mapping pi/4-QPSK or four-bit mapping 16QAM on the bit stream data according to a constellation diagram specified by a protocol to obtain two-path signals of an I path and a Q path;

7. A digital diversity communication system according to claim 1 or 2, wherein in the receiver, the reception path comprises a first reception path and a second reception path;

the receiving channel comprises two processing links, namely a 19.2ksps data processing link and a 75.8ksps data processing link, and the two processing links are respectively suitable for processing 19.2ksps data and 76.8ksps data and have consistent processing modes;