CN115079807A - Communication device, memory access method of communication device and electronic equipment - Google Patents

Communication device, memory access method of communication device and electronic equipment Download PDF

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CN115079807A
CN115079807A CN202210519978.3A CN202210519978A CN115079807A CN 115079807 A CN115079807 A CN 115079807A CN 202210519978 A CN202210519978 A CN 202210519978A CN 115079807 A CN115079807 A CN 115079807A
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processor
transmission
interrupt
memory
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CN115079807B (en
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朱忠武
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Spreadtrum Technology Hangzhou Co ltd
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Spreadtrum Technology Hangzhou Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5022—Mechanisms to release resources

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  • General Engineering & Computer Science (AREA)
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  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Abstract

The application discloses communication device, this communication device includes: the storage is used for storing the firmware and the file system of the first processor and the second processor; the first processor comprises a first processor, a hardware lock unit, a transmission control unit, an interrupt transmission unit and a first transmission unit, wherein the hardware lock unit transmits a target command to the interrupt transmission unit, the transmission control unit generates an interrupt instruction according to information transmitted by the memory, the first processing unit receives the interrupt instruction and processes the interrupt instruction, or the first transmission unit transmits the interrupt instruction to the second processor; the second processor comprises a second processing unit and a second transmission unit, the second transmission unit transmits the interrupt instruction to the second processing unit, and the second processing unit processes according to the interrupt instruction. The application also discloses a memory access method of the communication device and an electronic device with the communication device.

Description

Communication device, memory access method of communication device and electronic equipment
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a communication device, a memory access method for the communication device, and an electronic apparatus having the communication device.
Background
An Embedded System (Embedded System) is a device capable of operating independently, and integrates modules such as a Central Processing Unit (CPU), a memory, a communication module, an input/output module, and the like into one chip, so that the Embedded System meets the requirements of small volume, low power consumption, and specialized use scenarios, and is widely applied to intelligent devices such as consumer electronics and mobile communication. An embedded system generally includes an Application Processor (AP), a Communication Processor (CP), and the like.
Currently, because of the area and cost constraints, an Embedded system usually has only one Embedded multimedia Card (EMMC), which is used to store the firmware and file system of the AP and CP. When the CP side is started, the AP needs to assist to load its firmware into a Double Data Rate (DDR) of the CP side, and the AP must be started first to start the CP. However, when only the CP is required to access the required file system, software on the AP side also operates simultaneously, resulting in an increase in power consumption of the entire system.
Disclosure of Invention
The application provides a communication device, a memory access method of the communication device and an electronic device with the communication device, which solve the problem that the power consumption of the whole system is increased due to the fact that an AP must be started in a system before a CP can be started, and voltage division is generated.
In a first aspect, the present application provides a communication device comprising: the storage device comprises a memory, a first processor and a second processor, wherein the first processor is electrically connected with the memory and the second processor, and the memory is used for storing firmware and file systems of the first processor and the second processor; the first processor comprises a hardware lock unit, a transmission control unit, an interrupt transmission unit and a first transmission unit, wherein the hardware lock unit is electrically connected with the interrupt transmission unit and is used for transmitting a target command to the interrupt transmission unit, the transmission control unit is electrically connected with the memory and the interrupt transmission unit and is used for generating an interrupt instruction according to information transmitted by the memory and transmitting the interrupt instruction to the interrupt transmission unit, the interrupt transmission unit is electrically connected with the first transmission unit and is used for selectively transmitting the interrupt instruction transmitted by the transmission control unit to the first processing unit or the first transmission unit according to the target command transmitted by the hardware lock unit, and the first processing unit is used for receiving the interrupt instruction transmitted by the interrupt transmission unit, processing the interrupt instruction, or transmitting the interrupt instruction transmitted by the interrupt transmission unit to the second processor by the first transmission unit; the second processor comprises a second processing unit and a second transmission unit, wherein the second transmission unit is electrically connected with the first transmission unit and is used for transmitting the interrupt instruction transmitted by the first transmission unit to the second processing unit, and the second processing unit is used for processing according to the interrupt instruction transmitted by the second transmission unit; the second processing unit is further configured to transmit an access instruction to the second transmission unit, and the second transmission unit is further configured to transmit the access command to the memory through the first transmission unit and the transmission control unit.
To sum up, in the communication device of the present application, under the condition that the first processing unit in the first processor is asleep, the second processor transmits the access command to the transmission control unit through the first transmission unit and the second transmission unit, and the transmission control unit transmits the access command to the memory again, so as to access the memory, thereby reducing the power consumption of the communication device. In addition, the communication device of the application makes full use of the existing hardware resources, and solves the problem of how the second processor shares the EMMC storage of the first processor under the condition that the EMMC in the system is unique.
In a possible implementation manner, the second processor further includes a storage unit, wherein the storage unit is electrically connected to the second processing unit and the second transmission unit, and is configured to transmit data to the second transmission unit.
In a possible implementation manner, the first processor further includes a first bus, the first bus is electrically connected to the hardware lock unit, the first processing unit, the transmission control unit, the interrupt transmission unit, and the first bus is configured to transmit data, a data address, and a control command received or sent by the first processor; the second processor further includes a second bus electrically connected to the second processing unit, the second transmission unit, and the storage unit, and configured to transmit the interrupt instruction transmitted by the second transmission unit or the access command transmitted by the second processing unit.
In one possible implementation, the memory is an embedded multimedia card, the first processor is an application processor, and the second processor is a communication processor.
In one possible implementation, the memory unit is a double rate synchronous dynamic random access memory.
In a possible implementation manner, the hardware lock unit is a spin lock, the first processing unit and the second processing unit are both central processing units, the transmission control unit is a secure digital input/output interface, the interrupt transmission unit is a doorbell transaction module, and the first transmission unit and the second transmission unit are both high-speed serial computer expansion buses.
In a second aspect, the present application further provides a memory access method of a communication device, for accessing a memory by the communication device, where the memory access method includes: the transmission control unit generates an interrupt instruction and transmits the interrupt instruction to a second processing unit of a second processor through a corresponding interrupt transmission path; the second processing unit outputs an access command to a memory; and the second processing unit carries out data transmission with the memory according to the access command.
In summary, in the memory access method of the communication device of the present application, when the first processing unit in the first processor is in a sleep state, the second processor transmits an access command to the transmission control unit through the first transmission unit and the second transmission unit, and the transmission control unit transmits the access command to the memory, so as to access the memory, thereby reducing the power consumption of the communication device. In addition, the communication device of the application makes full use of the existing hardware resources, and solves the problem of how the second processor shares the EMMC storage of the first processor under the condition that the EMMC in the system is unique.
In one possible implementation manner, the generating, by the transmission control unit, an interrupt instruction and transmitting the interrupt instruction to the second processing unit of the second processor through a corresponding interrupt transmission path includes: the interrupt transmission unit transmits the interrupt instruction transmitted by the transmission control unit to the second processing unit through the first transmission unit and the second transmission unit, and the second processing unit processes the interrupt instruction transmitted by the second transmission unit; the interrupt transmission unit transmits the interrupt instruction transmitted by the transmission control unit to a first processing unit of a first processor, and the first processing unit processes according to the interrupt instruction transmitted by the interrupt transmission unit.
In a possible implementation, the second processing unit outputs the access command to the transfer control unit, the base address used is a mapping of the transfer control unit address on the second processor, and the mapping is performed by the second transfer unit.
In a possible implementation, the second processing unit transfers data with the memory, the source address used is a mapping of memory unit addresses in the first processor, and the mapping is performed by the second transfer unit.
In one possible implementation, the memory access method of the communication device further includes: the memory receives an access command sent by the first processor or the second processor; the first processor or the second processor acquires a hardware lock unit; the memory reads the access command sent by the first processor or the second processor; the first processor or the second processor drives the memory to access; the first processor or the second processor completing the access to the memory; the first processor or the second processor releases the hardware lock unit.
In a third aspect, the present application further provides an electronic device, which includes a user design module and the communication apparatus described above.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a communication device according to an embodiment of the present application;
FIG. 2 is a schematic flow chart of a method of memory access of the communication device of FIG. 1;
fig. 3 is a schematic structural diagram corresponding to step S10 in the memory access method of the communication device shown in fig. 2;
fig. 4 is a schematic structural diagram corresponding to step S20 in the memory access method of the communication device shown in fig. 2;
fig. 5 is a schematic address mapping diagram of access commands of a first processor and a second processor in a communication device according to an embodiment of the present application;
fig. 6 is a schematic structural diagram corresponding to step S30 in the memory access method of the communication device shown in fig. 2;
fig. 7 is a schematic diagram of address mapping of data of a first processor and a second processor in a communication device according to an embodiment of the present application;
FIG. 8 is a schematic diagram of the operation of a hardware lock unit of the communication device of FIG. 1;
fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the following embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used in the specification of the present application and the appended claims, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the listed items.
It should be noted that the terms "first," "second," "third," and the like in the description and claims of the present application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in other sequences than described or illustrated herein. Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or server that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Because the Embedded System (Embedded System) integrates modules such as a Central Processing Unit (CPU), a memory, a communication module, an input/output module and the like into one chip, the Embedded System meets the requirements of small volume, low power consumption and specialized use scenes, and is widely applied to intelligent devices such as consumer electronics and mobile communication. An embedded system generally includes an Application Processor (AP), a Communication Processor (CP), and the like. Currently, because of the area and cost constraints, an Embedded system usually has only one Embedded multimedia Card (EMMC), which is used to store the firmware and file system of the AP and CP. When the CP side is started, the AP needs to assist in loading its firmware into a Double Data Rate (DDR) of the CP side, and the CP must be started first. However, when only the CP side is required to access the required file system, software that also starts the AP side is also simultaneously operated, resulting in an increase in power consumption of the entire system.
Therefore, finding a solution to the problem in the prior art that the power consumption of the whole system is increased due to the voltage division generated when the AP must be started in the system to start the CP first becomes a technical problem that needs to be solved by those skilled in the art.
Based on this, the present application is intended to provide a solution to the above technical problem, which can solve the problem of increased power consumption of the whole system due to the voltage division generated by the CP that must be started by the AP in the system, and the details of which will be described in the following embodiments. The detailed description of the scheme of the application includes a communication device, a memory access method of the communication device and an electronic device with the communication device.
Please refer to fig. 1, which is a schematic structural diagram of a communication device according to an embodiment of the present application. As shown in fig. 1, the communication apparatus 100 provided herein is applicable to a specific embedded device, which may include at least a memory 110, a first processor 120, and a second processor 130. The memory 110 is electrically connected to the first processor 120, and the first processor 120 is electrically connected to the second processor 130, that is, the first processor 120 is electrically connected to both the memory 110 and the second processor 130.
In the embodiment of the present application, the memory 110 is used for storing the firmware and the file system of the first processor 120 and the second processor 130, and the second processor 130 transmits an access command to the memory 110 through the first processor 120, so as to implement data transmission between the second processor 130 and the memory 110.
In the embodiment of the present application, the memory 110 may be an Embedded multimedia Card (EMMC), which mainly aims at the Embedded memory standard specification of products such as mobile phones and tablet computers, and a multimedia Card interface, a flash memory device, a main controller and other devices are packaged in the memory. The first Processor 120 may be an Application Processor (AP), and the second Processor 130 may be a Communication Processor (CP).
In the embodiment of the present application, the first processor 120 includes a hardware lock unit 121, a first processing unit 122, a first bus 123, a transmission control unit 124, an interrupt transmission unit 125, and a first transmission unit 126, wherein the hardware lock unit 121 is electrically connected to the first bus 123 and the interrupt transmission unit 125, and is configured to transmit a target command to the interrupt transmission unit 125. The first processing unit 122 is electrically connected to the first bus 123, and configured to receive the interrupt instruction transmitted by the interrupt transmission unit 125 through the first bus 123 and process the interrupt instruction. The first bus 123 is electrically connected to the hardware lock unit 121, the first processing unit 122, the transmission control unit 124, the interrupt transmission unit 125, and the first transmission unit 126, and is configured to transmit data, data addresses, and control commands received or sent by the first processor 120.
In the embodiment of the present application, the transmission control unit 124 is electrically connected to the memory 110, the first bus 123 and the interrupt transmission unit 125, and is configured to generate an interrupt command according to the information transmitted by the memory 110 and transmit the interrupt command to the interrupt transmission unit 125. The interrupt transmission unit 125 is electrically connected to the hardware lock unit 121, the first bus 123, the transmission control unit 124 and the first transmission unit 126, and is configured to transmit an interrupt instruction transmitted by the transmission control unit 124 to the first processing unit 122 or the first transmission unit 126 according to a target command transmitted by the hardware lock unit 121. The first transmission unit 126 is electrically connected to the first bus 123, the interrupt transmission unit 125 and the second processor 130, and is configured to transmit the interrupt instruction transmitted by the interrupt transmission unit 125 to the second processor 130.
In the embodiment of the present application, the hardware lock Unit 121 may be a spin lock (Spinlock), the first Processing Unit 122 may be a Central Processing Unit (CPU), the transmission control Unit 124 may be a Secure Digital Input and Output (SDIO) interface, and the interrupt transmission Unit 125 may be a Doorbell (Doorbell Gen, DG) transaction module, which is a port-based lightweight transaction, may be used for in-band (in-band) interrupts, and may be used for sending inter-processor interrupt instructions.
In the embodiment of the present application, the first transmission unit 126 may be a Peripheral Component Interconnect Express (PCIE).
In this embodiment, the second processor 130 includes a second processing unit 131, a second bus 132, a second transmission unit 133 and a storage unit 134, wherein the second transmission unit 133 is electrically connected to the first transmission unit 126 and electrically connected to the second processing unit 131 through the second bus 132, and the second transmission unit 133 is configured to transmit the interrupt instruction transmitted by the first transmission unit 126 to the second processing unit 131 through the second bus 132. The second transmission unit 133 is further configured to transmit the access command transmitted by the second processing unit 131 to the first transmission unit 126.
In this embodiment, the second processing unit 131 is electrically connected to the second bus 132, and is configured to process according to the interrupt instruction transmitted by the second transmitting unit 133. The second processing unit 131 is further configured to transmit an access command to the memory 110 through the second bus 132, the second transmission unit 133, the first transmission unit 126, the first bus 123, and the transmission control unit 124.
In this embodiment, the second bus 132 is electrically connected to the second processing unit 131, the second transmission unit 133 and the storage unit 134, and is configured to transmit the interrupt instruction transmitted by the second transmission unit 133 or the access command transmitted by the second processing unit 131. The storage unit 134 is electrically connected to the second transmission unit 133 through the second bus 132, and is configured to transmit data to the second transmission unit 133.
In the embodiment of the present invention, the second Processing Unit 131 may be a Central Processing Unit (CPU), the second transmission Unit 133 may be a Peripheral Component Interconnect Express (PCIE), and the storage Unit 134 may be a Double Data Rate (DDR).
To sum up, in the communication device 100 of the present application, when the first processing unit 122 in the first processor 120 is in sleep, the second processor 130 transmits an access command to the transmission control unit 124 through the first transmission unit 126 and the second transmission unit 133, and the transmission control unit 124 transmits the access command to the memory 110, so as to access the memory 110, thereby reducing the power consumption of the communication device 100. In addition, the communication device 100 of the present application makes full use of the existing hardware resources, and solves the problem of how the second processor 130 shares the EMMC storage of the first processor 120 when the EMMC is unique in the system.
Please refer to fig. 2, which is a flowchart illustrating a memory access method of the communication apparatus shown in fig. 1. This workflow is used to reduce the power consumption of the communication apparatus 100 in the embodiment shown in fig. 1 described above. As shown in fig. 2, the workflow of the memory access method of the communication apparatus includes at least the following steps.
S10, the transmission control unit 124 generates an interrupt instruction, and transmits the interrupt instruction to the second processing unit 131 of the second processor 130 through the corresponding interrupt transmission path.
Specifically, referring to fig. 3, in the embodiment of the present application, the transmission control unit 124 generates an interrupt instruction according to the information transmitted by the memory 110, and transmits the interrupt instruction to the interrupt transmission unit 125, and at the same time, the hardware lock unit 121 transmits a target command to the interrupt transmission unit 125, so that the interrupt transmission unit 125 determines whether to transmit the interrupt instruction transmitted by the transmission control unit 124 to the first processing unit 122 or the second processing unit 131 according to the target command transmitted by the hardware lock unit 121, and generates two different interrupt transmission paths, namely, a first interrupt transmission path and a second interrupt transmission path. For example, if the interrupt transmission unit 125 determines, according to the target command transmitted by the hardware lock unit 121, that the interrupt instruction transmitted by the transmission control unit 124 is transmitted to the second processing unit 131, that is, when the interrupt transaction is transmitted through the second interrupt transmission path, the interrupt transmission unit 125 transmits the interrupt instruction transmitted by the transmission control unit 124 to the first transmission unit 126, the first transmission unit 126 transmits the transmitted interrupt instruction to the second transmission unit 133, the second transmission unit 133 transmits the interrupt instruction transmitted by the first transmission unit 126 to the second processing unit 131 through the second bus 132, and the second processing unit 131 processes according to the interrupt instruction transmitted by the second transmission unit 133; if the interrupt transmission unit 125 determines to transmit the interrupt instruction transmitted by the transmission control unit 124 to the first processing unit 122 according to the target command transmitted by the hardware lock unit 121, the interrupt transmission unit 125 transmits the interrupt instruction transmitted by the transmission control unit 124 to the first processing unit 122 through the first bus 123, and the first processing unit 122 is electrically connected to the first bus 123 and configured to process according to the interrupt instruction transmitted by the interrupt transmission unit 125 through the first bus 123.
S20, the second processing unit 131 outputs an access command to the memory 110.
Specifically, referring to fig. 4, in the embodiment of the present application, the second processing unit 131 generates an access command and transmits the access command to the second transmitting unit 133 through the second bus 132, the second transmitting unit 133 transmits the access command to the first transmitting unit 126, the first transmitting unit 126 transmits the access command to the transmission control unit 124 through the first bus 123, and the transmission control unit 124 transmits the access command to the memory 110.
In the embodiment of the present application, in the access command transmission phase, the second processing unit 131 outputs the access command to the transmission control unit 124, and the used base address is the mapping of the address of the transmission control unit 124 in the second processor 130, and this mapping is completed by the second transmission unit 133. In the embodiment of the present application, for convenience of describing the mapping relationship, the following description is given with reference to fig. 5 as an example. Please refer to fig. 5, which is a schematic diagram illustrating address mapping of access commands of a first processor and a second processor in a communication device according to an embodiment of the present disclosure. Taking the starting address of the transmission control unit 124 in the first processor 120 as 0x71400000 as an example, the mapped address of the second transmission unit 133 in the second processor 130 is 0x271400000, that is, when the second processor 130 accesses the mapped address 0x271400000, the transmission control unit 124 in the first processor 120 can be actually accessed.
S30, the second processing unit 131 performs data transmission with the memory 110 according to the access command.
Specifically, referring to fig. 6, in an embodiment of the present application, the transmission control unit 124 in the first processor 120 starts data transmission, where the transmission control unit 124 includes a built-in Direct Memory Access (DMA). When a read operation is performed, only the destination address of the DMA needs to be set, where the destination address is a mapping of a certain address in the memory unit 134 of the second processor 130 to the first processor 120. When a write operation is performed, only the source address of the DMA needs to be set, where the source address is a mapping of a certain address in the storage unit 134 of the second processor 130 to the first processor 120.
In this embodiment, in the data transmission phase, the second processing unit 131 transmits data with the memory 110, and the source address used is the mapping of the address of the storage unit 134 in the first processor 120, and this mapping is performed by the second transmission unit 133. In the embodiment of the present application, for convenience of describing the mapping relationship, the following description is given with reference to fig. 7 as an example. Please refer to fig. 7, which is a schematic diagram illustrating address mapping of data of a first processor and a second processor in a communication device according to an embodiment of the present disclosure. Taking the example that the destination address of the data read from the memory 110 and saved to the DMA is 0x80000000 of the second processor 130, the first transfer unit 126 in the first processor 120 may map this address to 0x280000000, that is, the mapped address is 0x280000000, and then the start address of the DMA written in the transfer control unit 124 by the second processor 130 is 0x 280000000. The transmission control unit 124 includes a built-in Direct Memory Access (DMA). When a read operation is performed, only the destination address of the DMA needs to be set.
In summary, in the memory access method of the communication device of the present application, when the first processing unit 122 in the first processor 120 is in sleep, the second processor 130 transmits an access command to the transmission control unit 124 through the first transmission unit 126 and the second transmission unit 133, and the transmission control unit 124 transmits the access command to the memory 110, so as to access the memory 110, thereby reducing the power consumption of the communication device 100. In addition, the communication device 100 of the present application makes full use of the existing hardware resources, and solves the problem of how the second processor 130 shares the EMMC storage of the first processor 120 when the EMMC is unique in the system.
Please refer to fig. 8, which is a flowchart illustrating a work flow of the hardware lock unit of the communication device shown in fig. 1. As shown in fig. 8, the workflow of the hardware lock unit of the communication device includes at least the following steps.
S100, the memory 110 receives an access command sent by the first processor 120 or the second processor 130.
S200, the first processor 120 or the second processor 130 obtains the hardware lock unit 121.
S300, the memory 110 reads the access command sent by the first processor 120 or the second processor 130.
S400, the first processor 120 or the second processor 130 drives the memory 110 to access.
S500, the first processor 120 or the second processor 130 completes the access to the memory 110.
S600, the first processor 120 or the second processor 130 releases the hardware lock unit 121.
As shown in fig. 9, fig. 9 is an electronic device further provided in the embodiments of the present application. In the embodiment of the present application, the electronic device 20 includes the communication apparatus 100 and the user design module 200. Electronic equipment 20 can be used to thing networking usage scenarios such as intelligent wearing, intelligent house, sharing bicycle. For details, the communication device 100 refers to the description of the embodiment shown in fig. 1, and is not described herein again. The user design module 200 is used for controlling the communication device 100 to implement preset functions.
Each device and product described in the above embodiments includes modules/units, which may be software modules/units, or hardware modules/units, or may be partly software modules/units and partly hardware modules/units. For example, for each device and product of an application or integrated chip, each module/unit included in the application or integrated chip may all be implemented in a hardware manner such as a circuit, or at least a part of the modules/units may be implemented in a software program, which runs on an integrated processor inside the chip, and the remaining part of the modules/units may be implemented in a hardware manner such as a circuit; for each device and product corresponding to or integrating the chip module, each module/unit included in the device and product can be implemented by adopting hardware such as a circuit, different modules/units can be positioned in the same piece (such as a chip, a circuit module and the like) or different components of the chip module, at least part of/unit can be implemented by adopting a software program, and the software program runs in the chip module, and the rest of the modules/units of the integrated processor can be implemented by adopting hardware such as a circuit; for each device or product corresponding to or integrating the terminal, the modules/units included in the device or product may all be implemented by using hardware such as circuits, different modules/units may be located in the same component (e.g., chip, circuit module, etc.) or different components in the terminal, or at least some of the modules/units may be implemented by using a software program, the program runs on a processor integrated in the terminal, and the remaining sub-modules/units may be implemented by using hardware such as circuits.
It is noted that, for simplicity of explanation, the foregoing method embodiments are described as a series of acts or combination of acts, but those skilled in the art will appreciate that the present application is not limited by the order of acts, as some acts may, in accordance with the present application, occur in other orders and/or concurrently. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required in this application.
The descriptions of the embodiments provided in the present application may be referred to each other, and the descriptions of the embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments. For convenience and simplicity of description, for example, the functions and operations performed by each device and apparatus provided in the embodiments of the present application may refer to the relevant description of the method embodiments of the present application, and may also be referred to, combined with or incorporated into each other among the method embodiments and the device embodiments.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims (12)

1. A communications apparatus, comprising: the storage device comprises a memory, a first processor and a second processor, wherein the first processor is electrically connected with the memory and the second processor, and the memory is used for storing firmware and file systems of the first processor and the second processor;
the first processor comprises a hardware lock unit, a transmission control unit, an interrupt transmission unit and a first transmission unit, wherein the hardware lock unit is electrically connected with the interrupt transmission unit and is used for transmitting a target command to the interrupt transmission unit, the transmission control unit is electrically connected with the memory and the interrupt transmission unit and is used for generating an interrupt instruction according to information transmitted by the memory and transmitting the interrupt instruction to the interrupt transmission unit, the interrupt transmission unit is electrically connected with the first transmission unit and is used for selectively transmitting the interrupt instruction transmitted by the transmission control unit to the first processing unit or the first transmission unit according to the target command transmitted by the hardware lock unit, and the first processing unit is used for receiving the interrupt instruction transmitted by the interrupt transmission unit, processing the interrupt instruction, or transmitting the interrupt instruction transmitted by the interrupt transmission unit to the second processor by the first transmission unit;
the second processor comprises a second processing unit and a second transmission unit, wherein the second transmission unit is electrically connected with the first transmission unit and is used for transmitting the interrupt instruction transmitted by the first transmission unit to the second processing unit, and the second processing unit is used for processing according to the interrupt instruction transmitted by the second transmission unit;
the second processing unit is further configured to transmit an access instruction to the second transmission unit, and the second transmission unit is further configured to transmit the access command to the memory through the first transmission unit and the transmission control unit.
2. The communication device according to claim 1, wherein the second processor further comprises a storage unit, wherein the storage unit is electrically connected to the second processing unit and the second transmission unit, and is configured to transmit data to the second transmission unit.
3. The communication device according to claim 2, wherein the first processor further comprises a first bus, the first bus is electrically connected to the hardware lock unit, the first processing unit, the transmission control unit, the interrupt transmission unit, and the first bus is configured to transmit data, data addresses, and control commands received or sent by the first processor;
the second processor further includes a second bus electrically connected to the second processing unit, the second transmission unit, and the storage unit, and configured to transmit the interrupt instruction transmitted by the second transmission unit or the access command transmitted by the second processing unit.
4. The communication device of claim 1, wherein the memory is an embedded multimedia card, the first processor is an application processor, and the second processor is a communication processor.
5. The communication device of claim 2, wherein the memory unit is a double rate synchronous dynamic random access memory.
6. The communication device according to any one of claims 1 to 5, wherein the hardware lock unit is a spin lock, the first processing unit and the second processing unit are both central processing units, the transmission control unit is a secure digital input output interface, the interrupt transmission unit is a doorbell transaction module, and the first transmission unit and the second transmission unit are both high-speed serial computer expansion buses.
7. A memory access method of a communication apparatus for accessing a memory by the communication apparatus according to any one of claims 1 to 6, the memory access method comprising:
the transmission control unit generates an interrupt instruction and transmits the interrupt instruction to a second processing unit of a second processor through a corresponding interrupt transmission path;
the second processing unit outputs an access command to a memory;
and the second processing unit carries out data transmission with the memory according to the access command.
8. The memory access method of a communication device according to claim 7, wherein the transmission control unit generates an interrupt instruction and transmits the interrupt instruction to a second processing unit of a second processor through a corresponding interrupt transmission path, comprising:
the interrupt transmission unit transmits the interrupt instruction transmitted by the transmission control unit to the second processing unit through the first transmission unit and the second transmission unit, and the second processing unit processes the interrupt instruction transmitted by the second transmission unit;
the interrupt transmission unit transmits the interrupt instruction transmitted by the transmission control unit to a first processing unit of a first processor, and the first processing unit processes according to the interrupt instruction transmitted by the interrupt transmission unit.
9. The memory access method of the communication apparatus according to claim 8, wherein the second processing unit outputs the access command to the transfer control unit, the base address used is a mapping of the transfer control unit address on the second processor, and the mapping is performed by the second transfer unit.
10. The memory access method of the communication device as claimed in claim 9, wherein the second processing unit transfers data with the memory using a source address which is a mapping of memory unit addresses in the first processor, the mapping being performed by the second transfer unit.
11. The memory access method of a communication apparatus according to claim 10, further comprising:
the memory receives an access command sent by the first processor or the second processor;
the first processor or the second processor acquires a hardware lock unit;
the memory reads the access command sent by the first processor or the second processor;
the first processor or the second processor drives the memory to access;
the first processor or the second processor completing the access to the memory;
the first processor or the second processor releases the hardware lock unit.
12. An electronic device, characterized in that it comprises a user design module and a communication apparatus according to any of claims 1-6.
CN202210519978.3A 2022-05-13 Communication device, memory access method of communication device and electronic equipment Active CN115079807B (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0944442A (en) * 1995-07-26 1997-02-14 Denso Corp Data transfer device for microcomputer
JP2014063510A (en) * 2013-11-19 2014-04-10 Renesas Electronics Corp Data processing apparatus
CN104424033A (en) * 2013-09-02 2015-03-18 联想(北京)有限公司 Electronic device and data processing method
CN105302489A (en) * 2015-10-30 2016-02-03 致象尔微电子科技（上海）有限公司 Heterogeneous multi-core remote embedded memory system and method
US20160162201A1 (en) * 2014-12-08 2016-06-09 Symbol Technologies, Inc. Emmc functionality expander

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0944442A (en) * 1995-07-26 1997-02-14 Denso Corp Data transfer device for microcomputer
CN104424033A (en) * 2013-09-02 2015-03-18 联想(北京)有限公司 Electronic device and data processing method
JP2014063510A (en) * 2013-11-19 2014-04-10 Renesas Electronics Corp Data processing apparatus
US20160162201A1 (en) * 2014-12-08 2016-06-09 Symbol Technologies, Inc. Emmc functionality expander
CN105302489A (en) * 2015-10-30 2016-02-03 致象尔微电子科技（上海）有限公司 Heterogeneous multi-core remote embedded memory system and method

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