CN115079765A - Linear voltage regulator and integrated circuit device including the same - Google Patents
Linear voltage regulator and integrated circuit device including the same Download PDFInfo
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- CN115079765A CN115079765A CN202211009432.XA CN202211009432A CN115079765A CN 115079765 A CN115079765 A CN 115079765A CN 202211009432 A CN202211009432 A CN 202211009432A CN 115079765 A CN115079765 A CN 115079765A
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- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
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- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract
The application relates to a linear voltage regulator and an integrated circuit device comprising the same, wherein the linear voltage regulator comprises an amplifier, a driving stage circuit and an output stage circuit, wherein: the first input end of the amplifier is connected with a reference voltage, the second input end of the amplifier is connected with an output voltage provided by the output stage circuit, and the output end of the amplifier is connected with the driving stage circuit; the driving stage circuit includes: a current source; the source electrode of the first field effect tube is connected to the current source, the grid electrode of the first field effect tube is connected to the output end of the amplifier, and the drain electrode of the first field effect tube is grounded; the output stage circuit includes: and the grid electrode of the second field effect transistor is connected to the source electrode and the source electrode of the first field effect transistor to lead out the output voltage.
Description
Technical Field
The present application relates to the field of power supplies for integrated circuits, and more particularly, to linear voltage regulators and integrated circuit devices including the same.
Background
A linear regulator is a basic module commonly used in integrated circuits and is commonly used to provide a customized power supply for a particular module on a chip. The linear regulator generates less power supply noise and ripple compared to a switching power supply. More importantly, the linear voltage regulator can suppress noise and ripples from an external power supply, so that the quality of the power supply obtained by an internal circuit is higher. This characteristic is referred to as the Power Supply Rejection of the linear regulator and can be measured in terms of Power Supply Rejection (PSR).
The PSR characteristic of a linear regulator is frequency dependent. In a low speed system, the PSR characteristic of the linear regulator at low frequency is usually only of interest, but in a high speed, noise sensitive system, the PSR characteristic of the full frequency band of the linear regulator needs to be of interest to avoid excessive power supply noise at a certain frequency from entering the system.
For this reason, there is a need to design an improved linear regulator.
Disclosure of Invention
Embodiments of the present application provide a linear regulator and an integrated circuit device including the same for providing a high quality power supply with less noise and ripple for the integrated circuit device.
According to an aspect of the present application, a linear regulator is provided. The linear voltage regulator comprises an amplifier, a driving stage circuit and an output stage circuit, wherein: the first input end of the amplifier is connected with a reference voltage, the second input end of the amplifier is connected with an output voltage provided by the output stage circuit, and the output end of the amplifier is connected with the driving stage circuit; the driving stage circuit includes: a current source; the source electrode of the first field effect tube is connected to the current source, the grid electrode of the first field effect tube is connected to the output end of the amplifier, and the drain electrode of the first field effect tube is grounded; the output stage circuit includes: and the grid electrode of the second field effect transistor is connected to the source electrode and the source electrode of the first field effect transistor to lead out the output voltage.
In some embodiments of the present application, optionally, the first fet is a P-channel fet, and the second fet is an N-channel fet.
In some embodiments of the present application, optionally, a drain of the second field effect transistor is connected to a first power supply, the amplifier is driven by a second power supply, and a voltage of the second power supply is higher than a voltage of the first power supply.
In some embodiments of the present application, optionally, the current source is driven by the second power supply.
According to another aspect of the present application, a linear regulator is provided. The linear voltage regulator comprises an amplifier, a driving stage circuit, a feedback circuit and one or more output stage circuits, wherein: the first input end of the amplifier is connected with a reference voltage, the second input end of the amplifier is connected with the feedback circuit, and the output end of the amplifier is connected with the driving stage circuit; the driving stage circuit includes: a current source; the source electrode of the first field effect tube is connected to the current source, the grid electrode of the first field effect tube is connected to the output end of the amplifier, and the drain electrode of the first field effect tube is grounded; the feedback circuit includes: the grid electrode of the second field effect transistor is connected to the source electrode of the first field effect transistor, and the source electrode of the second field effect transistor is connected to the second input end; and a load resistor connected between the source of the second FET and a system ground; the output stage circuit includes: and the grid electrode of the third field effect transistor is connected to the source electrode and the source electrode of the first field effect transistor to lead out the output voltage.
In some embodiments of the present application, optionally, the first fet is a P-channel fet, and the second fet and the third fet are N-channel fets.
In some embodiments of the application, optionally, the output stage circuit supplies power to a second load resistor at the output voltage, and a resistance value of the load resistor is configured such that a ratio of sizes of the second fet and the third fet is equal to a ratio of resistance values of the second load resistor and the load resistor.
In some embodiments of the present application, optionally, a drain of the second field effect transistor and a drain of the third field effect transistor are connected to a first power supply, the amplifier is driven by a second power supply, and a voltage of the second power supply is higher than a voltage of the first power supply.
In some embodiments of the present application, optionally, the current source is driven by the second power supply.
According to another aspect of the present application, there is provided an integrated circuit device comprising any one of the linear voltage regulators as described above.
Drawings
The above and other objects and advantages of the present application will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which like or similar elements are designated by like reference numerals.
FIG. 1 illustrates a linear regulator according to one embodiment of the present application;
FIG. 2 illustrates a linear regulator according to one embodiment of the present application;
FIG. 3 shows a PSR characteristic circuit model of a linear regulator according to one embodiment of the present application;
fig. 4 to 7 show a circuit model according to a conventional linear regulator and its PSR characteristic.
Detailed Description
For the purposes of brevity and explanation, the principles of the present application are described herein with reference primarily to exemplary embodiments thereof. However, those skilled in the art will readily recognize that the same principles are equally applicable to all types of linear regulators and integrated circuit devices that include the same, and that these same or similar principles may be implemented therein, with any such variations not departing from the true spirit and scope of the present application. In this context, N-channel field effect transistors (P-channel field effect transistors), NMOS (PMOS), and NMOS transistors (PMOS) will be used in combination.
Fig. 4 to 7 show a circuit model according to a conventional linear regulator and its PSR characteristic. FIG. 4 shows a typical PMOS linear regulator structure, which includes a high gain amplifier Amp, a PMOS transistor M1 (powered by a power supply Vdd 1), and a load resistor R load And a capacitor C connected in parallel therewith load . In the loop of the linear regulator, a high gain amplifier Amp (the working voltage of which can also be provided by a power supply Vdd 1) adjusts the dc point of the output voltage by adjusting the voltage at the point a to minimize the difference between the reference voltage Vref and the output voltage Vout.
Assuming that the reference voltage Vref is an ideal reference without noise, the PSR characteristic of its full band will be considered below. At low frequencies, the supply noise seen by the noise at the output (where the output voltage Vout is drawn) is suppressed by the loop, thereby improving the PSR at low frequencies. At high frequencies, the noise at the output will be C load Low impedance to ground inhibits, so at high frequencies,the design can also obtain better PSR characteristics. But at intermediate frequencies, where the loop gain has been reduced to less than 1, and C load The impedance of the linear regulator is still large, and the PSR of the linear regulator is formed by the output resistor R of the PMOS tube M1 out And a load resistance R load The partial pressure of (c) to determine:
therefore, the full-band PSR of the PMOS linear regulator with the common structure is close to 1, which is difficult to meet the requirements of a noise sensitive system.
Fig. 5 shows an NMOS linear regulator design with an improved full-band PSR based on fig. 4. Compared with the PMOS linear regulator shown in fig. 4, the NMOS transistor M2 replaces the PMOS transistor M1, and the rest remains unchanged. The NMOS linear regulator has an output node with low output impedance, which reduces the transfer of noise from the power supply to the output point. The PSR resulting from the resistive voltage division can be calculated as:
wherein R is out2 Represents the output resistance, g, of the NMOS transistor M2 m2 Represents transconductance, R, of the NMOS transistor M2 load Representing the load resistance in the circuit. In general, g m2 R out2 Is significantly larger than the other terms in equation (2), which makes the PSR characteristic of the intermediate frequency of the NMOS linear regulator mainly depend on the self-gain of the regulating tube M2, and the PSR characteristic of the NMOS linear regulator is significantly better than that of the PMOS linear regulator.
The effect of the capacitance PSR of the NMOS linear regulator of fig. 5 is shown in fig. 6, where Ramp represents the output resistance of the amplifier Amp, C int Capacitance to ground representing point B connection, C gd Representing the parasitic capacitance between the gate and the drain of the NMOS transistor M2. At intermediate frequencies, the NMOS linear regulator has a gate capacitance to pass power supply noise through, in addition to the resistive path from Vdd1 through the output resistor of NMOS transistor M2 to the output voltage VoutThe capacitive path of (a). Due to the follow characteristic of the output stage, it can be considered that the output voltage Vout will follow the change of the point B at the intermediate frequency. Therefore, the noise transferred from the power supply to the point B will be completely transferred to the output voltage Vout point. Since the Ramp is large and can be ignored in calculation, the PSR characteristic ultimately caused by capacitance can be expressed as:
finally, the overall PSR characteristic resulting from two factors is:
in the overall PSR characteristic, the resistance and capacitance-induced PSR characteristics have the same weight, and both are required to have better characteristics if the overall PSR is to be optimized. As shown in the formula (3), C needs to be increased to optimize the capacitance PSR int The size of (2). Therefore, the NMOS linear regulator requires additional on-chip area to place a capacitor to achieve the effect of optimizing PSR.
Fig. 7 shows a dual power NMOS linear regulator modified from the NMOS linear regulator shown in fig. 5. Compared with the NMOS linear regulator shown in fig. 5, the dual-power NMOS linear regulator uses two operating voltages, Vdd1 and Vdd2, to respectively power the NMOS transistor M3 and the high-gain amplifier Amp, wherein the voltage of Vdd2 is higher than the voltage of Vdd 1. Thus, the voltage at point C is limited to the voltage of Vdd2, but can be higher than the voltage of Vdd 1. The voltage drop of the NMOS transistor M3 is not limited by the threshold voltage, so that the efficiency of the NMOS linear regulator is much higher than that of the typical NMOS linear regulator.
To address one or more of the above-described shortcomings in prior art linear regulators, the underlying principles of the application will be described below in connection with specific embodiments.
According to an aspect of the present application, there is provided a linear regulator. As shown in FIG. 1, the linear regulator 10 includes an amplifier 101, a driver stage circuit 102, and an output stage circuitAnd a way 103. For clarity of illustration of the principles of the present application, a load resistor R connected to the output stage circuit 103 is also shown in fig. 1 load And a capacitor C load The load resistor R is load And a capacitor C load May be an abstraction of the various loads actually connected to the linear regulator 10 (specifically the output stage circuit 103). That is, the load resistance R load And a capacitor C load The comprehensive resistive and capacitive characterization of the actual load can be realized respectively.
The amplifier 101 has a first input terminal (shown as the "+" pole) connected to the reference voltage Vref, a second input terminal (shown as the "-" pole) connected to the output voltage Vout provided by the output stage circuit 103, and an output terminal connected to the driver stage circuit 102. In other examples, the input signals of the first and second inputs of the amplifier 101 may be interchanged. The reference voltage Vref functions to limit the output voltage Vout provided from the output stage circuit 103, and specifically, the feedback and adjustment of the output voltage Vout can be realized by a loop formed by the amplifier 101, the driver stage circuit 102 and the output stage circuit 103 shown in the figure.
The driving stage circuit 102 includes a current source and a first fet M4, the source of the first fet M4 is connected to the current source, the gate is connected to the output terminal of the amplifier 101, and the drain is grounded. The output stage circuit 103 comprises a second field effect transistor M5, and the gate of the second field effect transistor M5 is connected to the source of the first field effect transistor M4, and the source thereof draws the output voltage Vout. Parallel load resistance R load And a capacitor C load Is connected between the source of the second fet M5 of the output stage circuit 103 and the system ground.
The amplifier 101 can utilize the characteristic of high gain to change the voltage at the point D with the difference between Vref and Vout, and under the action of the loop, the difference between Vout and Vref in the dc state can be made small, thereby realizing the adjustment of the output voltage Vout. The design requirements of amplifier 101 are generally met by using a differential input amplifier with a higher gain. The amplifier 101 may have a high output resistance such that its output point D is a low frequency pole in the loop, thereby ensuring the stability of the loop. In addition, some capacitance can be added at point D to further improve the stability of the loop without affecting the PSR characteristics of interest in the present invention.
The first fet M4 and the upper current source form a driver stage circuit 102, which functions to convert the gate E of the second fet M5 into a low impedance node. In the dc state, the source E point of the first fet M4 follows the change of the gate D point, so the driver stage circuit 102 is close to short circuit at the dc point and does not change the gain of the loop. In the ac state, due to the characteristics of the first fet M4, the resistance to ground at point E becomes:
where gm4 denotes the transconductance of the first FET M4, R out,I Representing the output resistance of the current source. By reasonably adjusting the current magnitude of the current source, 1/gm4 can be much smaller than R out,I And the output resistance of amplifier 101. Therefore, the driver stage circuit 102 greatly reduces the impedance to ground at point E compared to the case where D, E is directly short-circuited.
The second fet M5 in the output stage circuit 103 can control the magnitude of the output voltage Vout by the voltage value at point E.
In some embodiments of the present application, the first fet M4 is a P-channel fet and the second fet M5 is an N-channel fet. The N-channel fet has an output node with a low output impedance, which reduces the transfer of noise from the power supply to the output point. Therefore, constructing the output stage circuit 103 with an N-channel fet will make the PSR characteristic of the linear regulator 10 superior to constructing the output stage circuit 103 with a P-channel fet.
In some embodiments of the present application, the drain of the second fet M5 is connected to the first power supply Vdd1, the amplifier 101 is driven by the second power supply Vdd2, and the voltage of the second power supply Vdd2 is higher than the voltage of the first power supply Vdd 1. The dual-power linear regulator 10 uses two voltages, Vdd1 and Vdd2, to respectively supply the NMOS transistor M5 and the amplifier 101, wherein the voltage of Vdd2 is higher than the voltage of Vdd 1. Thus, the voltage at point D is limited to the voltage of Vdd2, but can be higher than the voltage of Vdd 1. The voltage drop of the NMOS transistor M5 is not limited by the threshold voltage, so that the efficiency of the NMOS linear regulator is much higher than that of the typical NMOS linear regulator. In addition, the current source in the driver stage circuit 102 may also be driven by the second power supply Vdd 2.
Fig. 3 shows a PSR characteristic circuit model of the linear regulator corresponding to fig. 1. Analyzing the PSR of the technical scheme in FIG. 1 at the worst frequency, the total PSR can be expressed in the form of formula (4), wherein the PSR caused by the resistance characteristic R See formula (2) for details. And PSR caused by capacitance due to the addition of the driving stage circuit 102 C The circuit model is shown in fig. 3, which is different from the above. Compared with the traditional NMOS linear voltage regulator, the resistor R connected with the point E in parallel buf Is a small resistor and therefore cannot be ignored in the calculation of the intermediate frequency. At this time, the capacitance-induced PSR characteristic can be expressed as:
wherein R is buf Representing the output resistance of driver stage circuit 102, i.e., 1/gm 4. s is used to represent the frequency of the calculated point. R in the formula (6) buf Is small, therefore PSR C Has a very high frequency. By adjusting R buf Can easily adjust the PSR C Is placed at a higher frequency than the pole of the output stage circuit 103. Thus, in PSR C Before that, the PSR of the entire linear regulator 10 has been dominated by the PSR capability of the pole of the output stage circuit 103. Thus, the circuitPSR no longer interacts with PSR C A strong correlation.
In summary, the driving stage circuit 102 with low output resistance improves the PSR characteristic due to the capacitor, thereby improving the overall PSR characteristic. Moreover, the PSR of the NMOS linear voltage stabilizer is not connected with the gate-to-ground capacitor C of the adjusting tube any more int Strong correlation, so that C is required for realization int The size of the capacitor is reduced, thereby reducing the cost of implementation of the linear voltage regulator.
According to another aspect of the present application, a linear regulator is provided. As shown in fig. 2, the linear regulator 20 includes an amplifier 201, a driving stage circuit 202, a feedback circuit 203, and one or more output stage circuits 204. Only one output stage circuit 204 is shown for illustrative purposes, but those skilled in the art may extend the multiple output stage circuit 204 from the illustrated output stage circuit 204. Likewise, for clarity of illustrating the principles of the present application, a load resistor R coupled into the output stage circuit 204 is also shown in FIG. 2 load2 (hereinafter referred to as a second load resistor for distinction) and a capacitor C load And in the case of including multiple output stage circuits, each output stage circuit can be connected with a corresponding load resistor and capacitor.
The amplifier 201 has a first input (shown as the "+" pole) connected to the reference voltage Vref, a second input (shown as the "-" pole) connected to the feedback circuit 203, and an output connected to the driver stage circuit 202. In other examples, the input signals of the first and second inputs of the amplifier 201 may be interchanged. The reference voltage Vref functions to limit the output voltage Vout provided by the output stage circuit 204, and specifically, the feedback and adjustment of the output voltage Vout can be realized by a loop formed by the amplifier 201, the driving stage circuit 202 and the feedback circuit 203 shown in the figure.
The driving stage circuit 202 includes a current source and a first fet M4, the source of the first fet M4 is connected to the current source, the gate is connected to the output terminal of the amplifier 201, and the drain is grounded. The feedback circuit 203 comprises a second FET M7, the gate of the second FET M7 is connected to the source of the first FET M4, the source is connected to the amplifier 201, to the second input terminal. The feedback circuit 203 further includes a load resistor R connected between the source of the second fet M7 and the system ground load1 . The output stage circuit 204 includes a third fet M8, and the gate of the third fet M8 is connected to the source of the first fet M4, and the source of the third fet is connected to the output voltage Vout. Parallel load resistor R load2 And a capacitor C load Is connected between the source of the third fet M8 of the output stage circuit 204 and the system ground.
The operation principle of linear regulator 20 shown in fig. 2 is substantially the same as that of linear regulator 10 shown in fig. 1, except that the control of voltage Voutr is implemented by a loop formed by amplifier 201, driver stage circuit 202 and feedback circuit 203 in linear regulator 20, and output stage circuit 204 is only used for providing output voltage Vout to the outside. The operation of the linear regulator 10 is incorporated herein by reference for the sake of brevity and will not be described in detail herein.
In some embodiments of the present application, the first fet M4 is a P-channel fet, and the second fet M7 and the third fet M8 are N-channel fets. The N-channel fet has an output node with a low output impedance, which reduces the transfer of noise from the power supply to the output point. Therefore, the feedback circuit 203 and the output stage circuit 204 are constructed by N-channel fets, which makes the PSR characteristic of the linear regulator 20 better than that of the feedback circuit and the output stage circuit constructed by P-channel fets.
In some embodiments of the present application, a ratio of the sizes of the second fet M7 and the third fet M8 is equal to a ratio of the second load resistance to the resistance of the load resistance. For example, as shown in FIG. 2, the functionality of linear regulator 20 may be implemented using a replica tube design. The second FET M7 is a replica of the third FET M8, and has a load resistor R load1 Is the second load resistor R load2 The replicated load of (c). Second field effect transistor M7, R load1 In the loop, while the third fet M8 is not in the loop, only the gate voltage is shared with the second fet M7. If it is ensured that the ratio of the sizes of the second FET M7 and the third FET M8 is equal to the second load resistance R load2 And a load resistance R load1 By comparison, Vout can be considered equal to Voutr, and thus control of voltage Voutr will also effect regulation of dc voltage Vout. The dimensional relationships that need to be satisfied are as follows:
W/L represents the width-to-length ratio of the channel sizes of the second field effect transistor M7 and the third field effect transistor M8, respectively. In this way, the PSR characteristic of linear regulator 20 at the output voltage Vout point and the PSR characteristic of linear regulator 10 at the output voltage Vout point are kept consistent.
In some embodiments of the present application, the drain of the second fet M7 and the drain of the third fet M8 are connected to the first power supply Vdd1, and the amplifier 201 is driven by the second power supply Vdd 2. The dual-power linear regulator 20 uses two voltages, Vdd1 and Vdd2, to respectively supply power to the NMOS transistor M7, M8 and the amplifier 201, wherein the voltage of Vdd2 is higher than the voltage of Vdd 1. Thus, the voltage at point D is limited to the voltage of Vdd2, but can be higher than the voltage of Vdd 1. The voltage drop of the NMOS transistors M7 and M8 is not limited by the threshold voltage, so that the efficiency of the NMOS linear regulator is much higher than that of the typical NMOS linear regulator. In addition, the current source in the driver stage circuit 202 may also be driven by the second power supply Vdd 2.
Another aspect of the present application also provides an integrated circuit device comprising any one of the linear voltage regulators described above.
In summary, some embodiments of the present application use an NMOS transistor to construct a linear regulator, which can have a better PSR; in some embodiments, the MOS transistor and the amplifier are respectively supplied with power by two power domains, so that the efficiency of the linear voltage regulator can be improved. In addition, the gate of the adjusting tube is changed into a low-resistance node through the low-resistance output driving stage in some embodiments, so that the PSR can be improved, the area can be saved, and the cost can be reduced.
The above are merely specific embodiments of the present application, but the scope of the present application is not limited thereto. Other possible variations or substitutions may occur to those skilled in the art based on the teachings herein, and are intended to be covered by the present disclosure. The embodiments and features of the embodiments of the present application may be combined with each other without conflict. The scope of protection of the present application is subject to the description of the claims.
Claims (10)
1. A linear regulator, comprising an amplifier, a driver stage circuit, and an output stage circuit, wherein:
the first input end of the amplifier is connected with a reference voltage, the second input end of the amplifier is connected with an output voltage provided by the output stage circuit, and the output end of the amplifier is connected with the driving stage circuit;
the driving stage circuit includes:
a current source; and
the source electrode of the first field effect tube is connected to the current source, the grid electrode of the first field effect tube is connected to the output end of the amplifier, and the drain electrode of the first field effect tube is grounded;
the output stage circuit includes:
and the grid electrode of the second field effect transistor is connected to the source electrode and the source electrode of the first field effect transistor to lead out the output voltage.
2. The linear regulator of claim 1, wherein the first fet is a P-channel fet and the second fet is an N-channel fet.
3. The linear regulator according to claim 2, wherein a drain of the second field effect transistor is connected to a first power supply, the amplifier is driven by a second power supply, and a voltage of the second power supply is higher than a voltage of the first power supply.
4. The linear regulator of claim 3, wherein the current source is driven by the second power supply.
5. A linear regulator, comprising an amplifier, a driver stage circuit, a feedback circuit, and one or more output stage circuits, wherein:
the first input end of the amplifier is connected with a reference voltage, the second input end of the amplifier is connected with the feedback circuit, and the output end of the amplifier is connected with the driving stage circuit;
the driving stage circuit includes:
a current source; and
the source electrode of the first field effect tube is connected to the current source, the grid electrode of the first field effect tube is connected to the output end of the amplifier, and the drain electrode of the first field effect tube is grounded;
the feedback circuit includes:
the grid electrode of the second field effect transistor is connected to the source electrode of the first field effect transistor, and the source electrode of the second field effect transistor is connected to the second input end; and
a load resistor connected between the source of the second FET and a system ground;
the output stage circuit includes:
and the grid electrode of the third field effect tube is connected to the source electrode and the source electrode of the first field effect tube to lead out the output voltage.
6. The linear regulator of claim 5, wherein the first FET is a P-channel FET, and the second and third FETs are N-channel FETs.
7. The linear regulator according to claim 6, wherein the output stage circuit supplies power to a second load resistor at the output voltage, and a resistance value of the load resistor is configurable such that a ratio of sizes of the second field effect transistor and the third field effect transistor is equal to a ratio of the second load resistor and the resistance value of the load resistor.
8. The linear regulator of claim 6, wherein the drain of the second FET and the drain of the third FET are connected to a first power supply, the amplifier is driven by a second power supply, and the second power supply has a voltage higher than the first power supply.
9. The linear regulator of claim 8, wherein the current source is driven by the second power supply.
10. An integrated circuit device, characterized in that the device comprises a linear regulator according to any of claims 1-9.
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