CN115064135A - Driving circuit and driving method of display panel and display device - Google Patents

Driving circuit and driving method of display panel and display device Download PDF

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Publication number
CN115064135A
CN115064135A CN202210806765.9A CN202210806765A CN115064135A CN 115064135 A CN115064135 A CN 115064135A CN 202210806765 A CN202210806765 A CN 202210806765A CN 115064135 A CN115064135 A CN 115064135A
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China
Prior art keywords
gate
polarity
gate line
lines
grid
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Chinese (zh)
Inventor
魏旃
王世君
王洋
丁腾飞
梁海瑶
吕广爽
张盛丰
陈公达
彭洲
王继国
刘屹
台玉可
杨心澜
齐胜美
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to CN202210806765.9A priority Critical patent/CN115064135A/en
Publication of CN115064135A publication Critical patent/CN115064135A/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The invention discloses a driving circuit, a driving method and a display device of a display panel, wherein in the driving circuit, aiming at each GOA unit group, any row of pixel points defined as the most positive polarity and the most negative polarity is taken as a reference, N GOA units are respectively connected with a grid line of pixel points defined as the first polarity and a grid line of pixel points defined as the second polarity according to the driving sequence, so that the driving sequences of the pixel points with the same defined polarity are adjacent, the first polarity and the second polarity are any one of the positive polarity and the negative polarity, and the first polarity and the second polarity are different polarities; when the N GOA units output the grid driving signals in sequence, the data lines are configured to output data signals with the polarities matched with the grid driving signals, so that the charging sequences of the pixel points with the defined polarities are adjacent. The invention can reduce the whole power consumption of the display panel.

Description

Driving circuit and driving method of display panel and display device
Technical Field
The invention relates to the technical field of display, in particular to a driving circuit and a driving method of a display panel and a display device.
Background
The Dual Gate product can reduce the number of data lines, thereby reducing the number of source driving chips, greatly reducing the cost and improving the product competitiveness. However, according to the existing Dual Gate pixel driving method, it is difficult to further reduce power consumption during driving.
Disclosure of Invention
In view of the above problems, the present invention provides a driving circuit, a driving method and a display device for a display panel, which can reduce the overall power consumption of the display panel.
In a first aspect, the present application provides the following technical solutions through an embodiment:
a driving circuit of a display panel, comprising: the GOA unit groups comprise N GOA units which are sequentially arranged, N is the number of clock signals, N is the number of clock signal lines, and N is an even number which is more than or equal to 6;
for each GOA unit group, taking any row of pixel points defined as the pixel points with the maximum total number of positive polarity and negative polarity as a reference, respectively connecting the N GOA units with the gate lines of the pixel points defined as the first polarity and the gate lines of the pixel points defined as the second polarity according to the driving sequence, so that the pixel points with the same defined polarity are adjacent in the driving sequence, wherein the first polarity and the second polarity are any one of the positive polarity and the negative polarity, and the first polarity and the second polarity are different polarities;
when the N GOA units sequentially output gate driving signals, the data lines are configured to output data signals with the polarity matched with the gate driving signals and the polarity matched with the gate driving signals, so that the charging sequence of pixel points with the same defined polarity is adjacent.
Optionally, the polarity inversion mode of the display panel is 2-pixel inversion;
the N GOA units correspond to N grid lines which are sequentially arranged, and the N grid lines comprise a first grid line group, a second grid line group, a third grid line group and a fourth grid line group; the first grid line group comprises 4 xK 1+1 of the N grid lines, the second grid line group comprises 4 xK 2+2 of the N grid lines, the third grid line group comprises 4 xK 3+3 of the N grid lines, and the fourth grid line group comprises 4K 4+4 of the N grid lines, wherein K1, K2, K3 and K4 are natural numbers, and 4 xK 1+1, 4 xK 2+2, 4 xK 3+3 and 4 xK +4 are not more than N, and K1, K2, K3 and K4 are sequentially changed from small value to large value;
the N GOA units are sequentially connected to each gate line in the first gate line group, each gate line in the second gate line group, each gate line in the third gate line group, and each gate line in the fourth gate line group.
Optionally, when the value of N is 8, the connection sequence of the N GOA units and the N gate lines is:
the 1 st GOA unit is connected with the 1 st gate line, the 2 nd GOA unit is connected with the 5 th gate line, the 3 rd GOA unit is connected with the 2 nd gate line, the 4 th GOA unit is connected with the 6 th gate line, the 5 th GOA unit is connected with the 3 rd gate line, the 6 th GOA unit is connected with the 7 th gate line, the 7 th GOA unit is connected with the 4 th gate line, and the 8 th GOA unit is connected with the 8 th gate line.
In a second aspect, based on the same inventive concept, the present application provides the following technical solutions through an embodiment:
a driving method of a display panel is used for driving the display panel; the display panel comprises a plurality of groups of gate lines and a plurality of data lines, wherein each group of gate lines comprises N gate lines which are sequentially arranged, N is the number of clock signals, N is the number of clock signal lines, and N is an even number which is more than or equal to 6;
for each group of gate lines, based on any column of pixel points defined as positive polarity and defined as negative polarity with the maximum total number, the driving method comprises the following steps:
outputting a gate drive signal to the N gate lines to sequentially drive pixels of the row defined as a first polarity, and after the driving of the pixels of the first polarity is completed, sequentially driving pixels of the row defined as a second polarity; the first and second polarities are either positive or negative, the first and second polarities being different polarities;
and outputting a data signal with the polarity matched with the gate driving signal and the polarity matched with the gate driving signal to the data line based on the gate driving signal for each gate line, so that the charging sequence of the pixel points with the same defined polarity is adjacent.
Optionally, the polarity inversion mode of the display panel is 2-pixel inversion; the N grid lines comprise a first grid line group, a second grid line group, a third grid line group and a fourth grid line group; the first grid line group comprises 4 xK 1+1 of the N grid lines, the second grid line group comprises 4 xK 2+2 of the N grid lines, the third grid line group comprises 4 xK 3+3 of the N grid lines, and the fourth grid line group comprises 4K 4+4 of the N grid lines, wherein K1, K2, K3 and K4 are natural numbers, and 4 xK 1+1, 4 xK 2+2, 4 xK 3+3 and 4 xK +4 are not more than N, and K1, K2, K3 and K4 are sequentially changed from small value to large value;
the outputting gate driving signals to the N gate lines includes:
outputting the gate driving signals to the N gate lines according to the sequence of the first gate line group, the second gate line group, the third gate line group and the fourth gate line group.
Optionally, when the value of N is 8, the outputting gate driving signals to the N gate lines includes:
and outputting the gate driving signal to 8 gate lines according to the sequence of the 1 st gate line, the 5 th gate line, the 2 nd gate line, the 6 th gate line, the 3 rd gate line, the 7 th gate line, the 4 th gate line and the 8 th gate line.
Optionally, when the value of N is 6, the outputting gate driving signals to the N gate lines includes:
outputting the gate driving signal to the 6 gate lines in the order of the 1 st gate line, the 5 th gate line, the 2 nd gate line, the 6 th gate line, the 3 rd gate line and the 4 th gate line.
Optionally, when the value of N is 16, the outputting gate driving signals to the N gate lines includes:
outputting the gate driving signal to 16 gate lines in the order of 1 st gate line, 5 th gate line, 9 th gate line, 13 th gate line, 2 nd gate line, 6 th gate line, 10 th gate line, 14 th gate line, 3 rd gate line, 7 th gate line, 11 th gate line, 15 th gate line, 4 th gate line, 8 th gate line, 12 th gate line, and 16 th gate line.
In a third aspect, based on the same inventive concept, the present application provides the following technical solutions through an embodiment:
a driving circuit of a display panel comprises a time sequence controller, a source electrode driver and a grid electrode driver, wherein the source electrode driver and the grid electrode driver are connected with the time sequence controller; the display panel comprises a plurality of groups of gate lines and a plurality of data lines, wherein each group of gate lines comprises N gate lines which are sequentially arranged, N is the number of clock signals, N is the number of clock signal lines, and N is an even number which is more than or equal to 6;
regarding each group of gate lines, taking any column of pixel points defined as positive polarity and defined as negative polarity with the maximum total number as reference:
the time sequence controller is used for controlling the grid driver to output grid driving signals to the N grid lines so as to sequentially drive the pixels defined as a first polarity in the row of pixels and sequentially drive the pixels defined as a second polarity in the row of pixels after the pixels of the first polarity are driven; the first and second polarities are either positive or negative, the first and second polarities being different polarities;
and for each gate line, the time sequence controller is used for controlling the source driver to output a data signal with the polarity matched with the gate driving signal and a data signal with the polarity matched with the gate driving signal to the data line based on the gate driving signal, so that the charging sequence of pixel points with the same defined polarity is adjacent.
In a fourth aspect, based on the same inventive concept, the present application provides the following technical solutions through an embodiment:
a display device comprising the driving circuit of the display panel according to any one of the first and third aspects.
In the driving circuit of the display panel in the embodiment of the invention, after the GOA units are connected with the gate lines, the plurality of data lines are configured to output the data signals matched with the gate driving signals when the N GOA units sequentially output the gate driving signals, so that the charging sequence of the pixel points with the same defined polarity is adjacent; therefore, the starting sequence of the pixel points with the same polarity is adjacent, the pixel points with the other polarity can be started after the pixel points with the one polarity are completely started, in the process, the reversing times of the polarity of the data signals are greatly reduced, and the power consumption of a display panel using the driving circuit can be remarkably reduced.
The above description is only an overview of the technical solutions of the present invention, and the present invention can be implemented in accordance with the content of the description so as to make the technical means of the present invention more clearly understood, and the above and other objects, features, and advantages of the present invention will be more clearly understood.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts. In the drawings:
fig. 1 is a schematic structural diagram showing a driving circuit of a first display panel in an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating the layout of GOA cells and gate lines of the display panel according to the embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating a comparison of polarity change timings of data signals between the present scheme and the existing scheme under a white/gray scale frame of a first pixel architecture according to an embodiment of the present invention;
FIG. 4 is a schematic diagram showing a comparison between polarity change timings of data signals in the present and existing schemes under a YCM color-mixed picture of a first pixel architecture according to an embodiment of the invention;
FIG. 5 is a schematic diagram illustrating a comparison between polarity change timings of data signals in the present and existing schemes under an RGB monochrome image with a first pixel architecture according to an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating the principle that the sequential turn-on of adjacent gate lines affects the voltages of the pixels according to the embodiment of the present invention;
FIG. 7 is a timing diagram illustrating pulse signals corresponding to some gate lines under the 8CLK clock signal in the embodiment of the present invention;
fig. 8 is a schematic diagram illustrating a comparison between the charging effects of the present solution and the charging effects of the prior solutions in the embodiment of the present invention;
FIG. 9 is a schematic diagram showing a comparison of polarity change timings of data signals in the present and existing schemes under a white/gray scale frame of a second pixel architecture according to an embodiment of the present invention;
FIG. 10 is a schematic diagram showing a comparison of polarity change timings of data signals in the present and existing schemes under a YCM color-mixed picture of a second pixel architecture according to an embodiment of the invention;
fig. 11 is a schematic diagram illustrating a comparison of polarity change timings of data signals in the present and existing schemes under an RGB monochrome picture of a second pixel architecture according to an embodiment of the present invention;
fig. 12 is a flowchart showing a driving method of a display panel in the embodiment of the present invention;
fig. 13 is a schematic diagram showing a structure of a driving circuit of a second display panel according to an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Referring to fig. 1, in an embodiment of the invention, a driving circuit 100 of a display panel is provided for driving a display panel 200. The driving circuit 100 includes: the Array substrate includes a plurality of data lines 111 and a plurality of Gate Driver on Array (GOA) unit groups, each of the GOA unit groups includes N GOA units arranged in sequence, N is the number of clock signal lines, and N is an even number greater than or equal to 6. The plurality of data lines 111 are used for transmitting data signals, which can be generated by a source driver; the plurality of GOA cell sets 121 can be used to generate gate driving signals to turn on or off the pixels in the corresponding row. Each row of pixels with the same color may be connected by the same gate line 122, and the pixels may be turned on or off by a gate driving signal transmitted through the gate line 122.
In this embodiment, the pixel point of the display panel is the light emitting point of the minimum unit. For example, a Pixel (Pixel) is composed of three single color light emitting units of red (R), green (G) and blue (B), and the Pixel is composed of the single color light emitting units of red, green and blue. When the display panel displays a picture, each pixel point has corresponding polarity, and the polarity of the pixel points is defined by the type of the display panel or the pre-designed specification. For example, in a 2dot inversion display panel, the defined polarity repetition mode of a certain column of pixels may be: ++ - - ++ - -.
Furthermore, the N GOA units may be configured to receive N clock signals, respectively, and the plurality of GOA unit groups may sequentially transmit gate driving signals to corresponding gate lines under the control of a scanning start Signal (STV) due to a cascade relationship among the plurality of GOA unit groups; it can be understood that after one GOA unit group completes scanning, the next GOA unit group starts scanning, and so on; of course, this is merely an example and may not be limited thereto.
For any group of GOA units, the pulse sequence of the gate driving signals output by the N GOA units may be arranged sequentially; that is, the pulse timing sequence of the 1 st GOA unit to the nth GOA unit sequentially starts from first to last. In the embodiment, no matter which frame of image the display panel refreshes, the image composition thereof is composed of a white/gray scale picture, a YCM (yellow, cyan, magenta) color-mixed picture and an RGB monochrome picture, so in the present embodiment, the GOA unit and the gate line are connected based on the characteristic of the polarity distribution of the pixel points. Specifically, based on any row of pixels defined as having the maximum total number of positive and negative polarities (which may be any frame of picture), the N GOA units are respectively connected to the gate lines of the pixels defined as the first polarity and the gate lines of the pixels defined as the second polarity according to the driving sequence, so that the driving sequences of the pixels defined as the same polarity are adjacent to each other. Wherein the first polarity and the second polarity are either positive polarity or negative polarity, and the first polarity and the second polarity are different polarities. For example, in fig. 2, a row of pixels defined as the row with the largest total number of positive and negative polarities is the pixel corresponding to any one of the rows of data lines S1, S2, S4, S5, the total number of the defined positive and negative polarities of each row is 4, and the pixel corresponding to the defined positive and negative polarities of the data line S3 and the data line S6 is 0.
The connection mode can ensure that when the N GOA units output the grid driving signals in sequence, the data lines are configured to output the data signals matched with the grid driving signals, so that the charging sequences of the pixel points with the same defined polarity are adjacent. That is to say, since the turn-on sequence of the pixels with the same polarity is adjacent, the pixel with the other polarity is turned on after the pixel with the one polarity is completely turned on, and in this process, the polarity of the data signal only needs to be inverted once. Therefore, the connection structure can greatly reduce the polarity jump times of the data signals and can obviously reduce the power consumption of the display panel applying the driving circuit.
In some display panels with 2dot inversion (two-dot liquid crystal inversion), N GOA cells in a GOA cell group are associated with N gate lines. The N grid lines comprise a first grid line group, a second grid line group, a third grid line group and a fourth grid line group. The first grid line group comprises 4 xK 1+1 of N grid lines, the second grid line group comprises 4 xK 2+2 of the N grid lines, the third grid line group comprises 4 xK 3+3 of the N grid lines, and the fourth grid line group comprises 4 xK 4+4 of the N grid lines, wherein K1, K2, K3 and K4 are natural numbers, and 4 xK 1+1, 4 xK 2+2, 4K 3+3 and 4 xK +4 are not more than N, and K1, K2, K3 and K4 take values from small to large in sequence; that is, the gate lines in each gate line group are arranged according to the sequence numbers from small to large. In order to ensure that the driving sequence of the pixels with the same defined polarity can be adjacent when a GOA group is scanned, the N GOA units are sequentially connected with each gate line in the first gate line group, each gate line in the second gate line group, each gate line in the third gate line group and each gate line in the fourth gate line group.
It is understood that the connection manner can be adjusted correspondingly in other types of display panels with inversion, for example, in a 4dot inversion display panel, N gate lines are divided into 8 groups; the first group of grid line groups is the 8 th xK 1+1 of the N grid lines, the second group of grid line groups comprises the 8 th xK 2+2 of the N grid lines, the third group of grid line groups comprises the 8 th xK 3+3 of the N grid lines, and the like; the eighth grid line group comprises 8K 8+8 of N grid lines, wherein K1, K2, K3, K4,. cndot.. cndot.and K8 are natural numbers, 4K 1+1, 4K 2+2, 4K 3+3, 4K +4,. cndot.. cndot.8 and K8+8 are not more than N, and K1, K2, K3,. cndot.. cndot.and K8 are sequentially increased from small to large.
In some implementations, when N is 8, the GOA architecture drives the display panel to have a clock signal of 8 CLK. Referring to fig. 2, taking the Dual Gate sum (a Dual Gate driving architecture) as an example, in the pixel architecture, in the first row of pixels, the sequence of the red pixels connected to the Gate line is: g1, G2, G1 and G2 which are sequentially circulated; the green pixel points are connected with the grid lines in sequence as follows: g2, G1, G2 and G1 which are sequentially circulated; the connection of the blue pixel point and the grid line is as follows in sequence: g1, G2, G1, G2, as shown in fig. 2. The connection sequence of the N GOA cells and the N gate lines at this time is as follows:
the 1 st GOA cell (GOA1) is connected to the 1 st gate line (G1), the 2 nd GOA cell (GOA2) is connected to the 5 th gate line (G5), the 3 rd GOA cell (GOA3) is connected to the 2 nd gate line (G2), the 4 th GOA cell (GOA4) is connected to the 6 th gate line (G6), the 5 th GOA cell (GOA5) is connected to the 3 rd gate line (G3), the 6 th GOA cell (GOA6) is connected to the 7 th gate line (G7), the 7 th GOA cell (GOA7) is connected to the 4 th gate line (G4), and the 8 th GOA cell (GOA8) is connected to the 8 th gate line (G8), as shown in fig. 2.
When driving, the turn-on sequence of 8 GOA units is from 1 to 8 GOA units, i.e. the GOAs 1 to 8 shown in fig. 2 are sequentially turned on; at this time, the opening sequence of the corresponding gate lines is as follows: the 1 st gate line, the 5 th gate line, the 2 nd gate line, the 6 th gate line, the 3 rd gate line, the 7 th gate line, the 4 th gate line, and the 8 th gate line, that is, G1, G5, G2, G6, G3, G7, G4, and G8 shown in fig. 2 are sequentially turned on; therefore, the driving sequence of the pixel points with the same defined polarity is adjacent, and the polarity change times of the data signals transmitted by the data lines can be reduced.
For easy understanding, the following description will be made by taking different display screen examples to illustrate the beneficial effects of the solution of the present embodiment:
referring to fig. 3(a), when the display panel displays a white/gray level image, the display panel is driven according to the conventional circuit structure, since the GOA1 is connected to the G1, the GOA2 is connected to the G2, the GOA3 is connected to the G3, the GOA4 is connected to the G4, the GOA5 is connected to the G5, the GOA6 is connected to the G6, the GOA7 is connected to the G7, and the GOA8 is connected to the G8; when the GOA units are sequentially turned on, first, the GOA1 and the GOA2 are sequentially turned on, and since the polarity of the defined pixel is positive, the data line S1 is a positive data signal; then, the GOA3 and the GOA4 are sequentially turned on, and since the polarity of the defined pixel is negative, the data line S1 is a negative data signal; the data signal of the data line S1 needs to be inverted once when the data signal is changed from positive polarity to negative polarity; by analogy, when the GOAs 5 and 6 are turned on, the polarity of the data signal of the data line S1 is inverted once again to become positive; when GOA7 and GOA8 are turned on, the polarity of the data signal on the data line S1 is inverted once again to become negative. That is, during driving, the polarity timing variation of the data signal of the data line S1 can be expressed as: + + - -; the polarity timing variation of the data signal of the data line S2 can be expressed as: - +++ - ++, as shown in FIG. 3 (c).
When the driving circuit of the display panel according to the present embodiment is used for driving, when the GOA units are turned on in turn, the gate lines connected thereto are G1, G5, G2, and G6 when the GOA1, the GOA2, the GOA3, and the GOA4 are turned on in turn; the pixel points corresponding to the 4 gate lines and the data line S1 are all defined as positive polarity; therefore, when GOA1, GOA2, GOA3 and GOA4 are turned on, the data signal of the data line S1 does not need to be inverted; similarly, when GOA5, GOA6, GOA7 and GOA8 are turned on, the gate lines connected to the GOA5, GOA6, GOA7 and GOA8 are G3, G7, G4 andg8, the pixel points corresponding to the 4 gate lines and the data line S1 are all defined as negative polarity, and the data signal of the data line S1 does not need to be inverted; during the time that these 8 GOA cells are turned on, polarity reversal will only occur between the last GOA cell of the previous group and the GOA1 of the current group, and between GOA4 and GOA 5. The polarity timing variation of the data signal of the data line S1 can be expressed as: + + + + + - - - - -; the polarity timing variation of the data signal of the data line S2 can be expressed as: - - - +++, as shown in FIG. 3 (b). That is, during driving, the polarity inversion effect of the data signals of the data lines S1 and S2 is equivalent to 4dot inversion, and the inversion frequency is reduced by 50% compared to 2dot inversion of the data signals of the prior art. Power formula ═ sigma based on Power consumption n f source *C*(V H ―V L ) 2 It can be determined that the Power consumption of the source driver can be greatly reduced by 50%, where Power is the Power consumption of the source driver, and f source Is the polarity inversion frequency of the data signal, C is the storage capacitance of the pixel, V H Is a voltage with positive polarity of data signal, V L Is a voltage with negative polarity of the data signal.
Referring to fig. 4(a), when the color mixing picture of the display panel YCM is displayed, the driving is performed according to the conventional circuit structure, and when the GOAs 1-8 are sequentially turned on, that is, the pixels corresponding to G1, G2, G3, G4, G5, G6, G7, and G8 are sequentially turned on. For the data line S1, the timing variation of the polarity of the data signal can be expressed as: + + - -; for the data line S2, the timing variation of the polarity of the data signal can be expressed as: 0-0+0-0 +; for the data line S3, the timing variation of the polarity of the data signal can be expressed as: +0-0+0-0, as shown in FIG. 4 (c).
If the driving circuit in this embodiment is used for driving, when the GOAs 1-8 are sequentially turned on, that is, the pixels corresponding to G1, G5, G2, G6, G3, G7, G4, and G8 are sequentially turned on. For the data line S1, the timing variation of the polarity of the data signal can be expressed as: + + + + + - - - - -; for the data line S2, the timing variation of the polarity of the data signal can be expressed as: 00-00 + +; for the data line S3, the timing variation of the polarity of the data signal can be tabulatedShown as follows: , + 00-00, as shown in FIG. 4 (b). Therefore, after the circuit structure in the embodiment is adopted to realize driving, the polarity inversion frequency of the data signal transmitted by the data line is also obviously reduced, and the Power consumption formula Power ═ Σ is based on n f source *C*(V H ―V L ) 2 By calculation, it can be determined that the power consumption of the source driver can also be greatly reduced by 50%.
Referring to fig. 5(a), when RGB monochromatic images are displayed, the conventional circuit structure is used to drive, and when the GOAs 1-8 are sequentially turned on, that is, the corresponding pixels G1, G2, G3, G4, G5, G6, G7, and G8 are sequentially turned on. For the data line S1, the timing variation of the polarity of the data signal can be expressed as: +0-0+ 0-0; for the data line S2, the timing variation of the polarity of the data signal can be expressed as: 0-0+0-0 +; for the data line S3, the timing variation of the polarity of the data signal can be expressed as: 00000000, as shown in fig. 5 (c).
If the circuit structure in this embodiment is used for driving, when the GOAs 1 to 8 are sequentially turned on, that is, the pixels corresponding to G1, G5, G2, G6, G3, G7, G4, and G8 are sequentially turned on. For the data line S1, the timing variation of the polarity of the data signal can be expressed as: + 00-00; for the data line S2, the timing variation of the polarity of the data signal can be expressed as: 00-00 + +; for the data line S3, the timing variation of the polarity of the data signal can be expressed as: 00000000, as shown in fig. 5 (b). Therefore, after the circuit structure in the embodiment is adopted to realize driving, the polarity inversion frequency of the data signal transmitted by the data line is also obviously reduced, and the Power consumption formula Power ═ Σ is based on n f source *C*(V H ―V L ) 2 By calculation, it can be determined that the power consumption of the source driver can also be reduced by as much as 33%.
Moreover, the driving order in a group of gate lines after the circuit configuration is adjusted is G1, G5, G2, G6, G3, G7, G4, G8 under the RGB monochrome picture; so that the gate lines will not be turned on sequentially, thereby avoiding the occurrence of parasitic capacitance (C) on part of the pixels in the conventional structure gp ) The different coupling results in poor image quality, such as vertical stripes on the screen.
Referring to fig. 6, when the conventional methods G1-G8 are sequentially driven, taking the pixel R1 corresponding to G1S1 as an example, G1 is turned off after the charging of the pixel R1 is finished, because a parasitic capacitor C exists between G1 and the pixel R1 during the charging process gp 1, the electrode of the pixel R1 is pulled by coupling to generate the first voltage deviation Δ Vp. When G2 is turned off after 1H time (duration of scanning one line), a parasitic capacitor C exists between G2 and the pixel R1 gp 2, the voltage deviation Δ Vp is again affected. For the pixel point R2 corresponding to G1S2, since G1 is turned before and G2 is turned after, the pixel point R2 is only subjected to the parasitic capacitance C when G2 is turned off gp 2, and the resulting voltage deviation Δ Vp, as shown in fig. 6. In other words, the charging process of the pixel S1 is affected by the turn-on of G1 and G2, but the charging process of the pixel S2 is affected by the turn-on of G2 (C corresponding to the data line S2) gp 1) and the influence of the pixel point R1 and the pixel point R2 is different, resulting in a difference in charging voltage. That is to say, the two rows of red pixels corresponding to the data line S1 and the data line S2 respectively generate a brightness difference, so that the red image shows vertical stripes. Similarly, it can be known that the same problem exists for both the green pixel and the blue pixel, and therefore, the vertical stripe defect can be generated when the green picture or the red picture is displayed.
In the present embodiment, the driving sequence is G1, G5, G2, G6, G3, G7, G4, and G8, as shown in fig. 7. When the G1 is turned on, only the pixel point R1 is charged, and when the G1 is turned off, the pixel point R1 is pulled, so that the primary voltage deviation Δ Vp is generated. When G5 is turned on for pre-charging, the turning on and off of G5 does not have any influence on the charging process of the pixel point R1 because G2, G3 and G4 are spaced between G5 and G1. When G2 is turned on, pixel R1 has completed the charging process, and G1 has been turned off, and is not affected by G1. That is, the pixel R2 is pulled only when G2 is turned off to generate the sequential voltage deviation Δ Vp. Therefore, the influence quantity of the gate lines on the pixel point R1 and the pixel point R2 is the same, the charging difference is avoided, the picture quality can be better improved, and the bad vertical stripes are inhibited.
Furthermore, the driving circuit in this embodiment greatly reduces the number of inversion times of the data signal due to the influence of the charging sequence, and the gate lines are turned on alternately, so as to improve the pre-charging time and charging rate of some pixels, reduce the charging difference between adjacent columns of the YCM color-mixed picture, and improve the picture quality. Referring to fig. 8(a), O is good, Δ is middle of charging, X is bad, X ↓ represents bad charging and is influenced by parasitic capacitance to a low level. Parasitic capacitance C caused by driving sequence when charging is carried out by adopting the existing scheme gp And the influence of polarity inversion, which causes that the red pixel point of the first column has charging difference with the standard voltage to be reached, and is also influenced by a parasitic capacitor C gp Low in the influence of (c); similarly, the green pixel points in the fifth column have charging differences with the standard voltage to be reached, and are also influenced by the parasitic capacitance to be low, when the driving circuit is adopted, the inversion frequency of the data signal is reduced, the charging rate can be obviously improved, and adverse effects caused by the parasitic capacitance are avoided; as shown in fig. 8(b), the adverse effect by the parasitic capacitance is eliminated while the relative reduction in the state of charge in the pixels of the first column and the fifth column is reduced by half.
Referring to fig. 9, taking a display panel with Dual Gate sum 2 (a Dual Gate driving structure) structure as an example, in the pixel structure, in the first row of pixels, the red pixels are connected to G1 when they are connected to the Gate line; the green pixel points are connected with the G2 ring when being connected with the gate lines; the connection of the blue pixel point and the grid line is as follows in sequence: g2, G1, G2, G1, as shown in fig. 9. At this time, the connection sequence of the N GOA units and the N Gate lines is the same as that of the display panel with the Dual Gate column architecture, and is not described again. Similarly, a description will be given of different display screens as follows:
referring to fig. 9, when the display panel displays a white/gray level image, the polarity sequence of the data signals of the data lines S1 when the display panel is driven according to the conventional circuit structure and the GOAs 1-8 are turned on sequentially can be expressed as: + + - -; the polarity timing variation of the data signal of the data line S2 can be expressed as: - - ++ - - ++. When performed according to the driving circuit of the display panel in the present embodimentWhen driving, the polarity timing variation of the data signal of the data line S1 can be expressed as: + + ++ - - - -; the polarity timing variation of the data signal of the data line S2 can be expressed as: - - - - ++++. Power formula ═ sigma based on Power consumption n f source *C*(V H ―V L ) 2 It can be determined that the power consumption of the source driver can be greatly reduced by 50%.
Referring to fig. 10, when the display panel YCM color-mixed picture is driven according to the conventional circuit structure and the GOAs 1-8 are sequentially turned on, the timing variation of the polarity of the data signal for the data line S1 can be represented as: + + - -; for the data line S2, the timing variation of the polarity of the data signal can be expressed as: -0+0-0+ 0; for the data line S3, the timing variation of the polarity of the data signal can be expressed as: 0+0-0+0-. When the driving circuit in the present embodiment is used for driving, the timing variation of the polarity of the data signal for the data line S1 can be expressed as: + + + + + - - - - -; for the data line S2, the timing variation of the polarity of the data signal can be expressed as: -00+ + 00; for the data line S3, the timing variation of the polarity of the data signal can be expressed as: 00++00- -. Therefore, after the circuit structure in the embodiment is adopted to realize driving, the polarity inversion frequency of the data signal transmitted by the data line is also obviously reduced, and the Power consumption formula Power ═ Σ is based on n f source *C*(V H ―V L ) 2 By calculation, it can be determined that the power consumption of the source driver can also be reduced by as much as 50%.
Referring to fig. 11, when the RGB monochromatic images are displayed and driven according to the conventional circuit structure, and the GOAs 1-8 are sequentially turned on, the timing variation of the polarity of the data signal for the data line S1 can be represented as: +0-0+ 0-0; for the data line S2, the timing variation of the polarity of the data signal can be expressed as: -0+0-0+ 0; for the data line S3, the timing variation of the polarity of the data signal can be expressed as: 00000000. when the circuit structure in this embodiment is used for driving, the timing change of the polarity of the data signal for the data line S1 can be expressed as: + 00-00; for the data line S2, the timing variation of the polarity of the data signal can be expressed as: -00+ + 00; for theFor the data line S3, the timing variation of the polarity of the data signal can be expressed as: 00000000. power-consumption-formula-based Power ═ sigma n f source *C*(V H ―V L ) 2 By calculation, it can be determined that the power consumption of the source driver can also be reduced by as much as 33%.
Similarly, in the Dual Gate gum 2 configuration, the charging rate can be improved while suppressing the moire defect due to the parasitic capacitance by the driving circuit. The related principle can be referred to the explanation in the aforementioned Dual Gate gum architecture example, and is not described here again.
In some implementations, when N is 16, that is, the GOA architecture drives the display panel with a clock signal of 16 CLK. Under this architecture, the connection order of the N GOA cells and the N gate lines is as follows:
the 1 st GOA unit is connected with the 1 st gate line, the 2 nd GOA unit is connected with the 5 th gate line, the 3 rd GOA unit is connected with the 9 th gate line, the 4 th GOA unit is connected with the 13 th gate line, the 5 th GOA unit is connected with the 2 nd gate line, the 6 th GOA unit is connected with the 6 th gate line, the 7 th GOA unit is connected with the 10 th gate line, the 8 th GOA unit is connected with the 14 th gate line, the 9 th GOA unit is connected with the 3 rd gate line, the 10 th GOA unit is connected with the 7 th gate line, the 11 th GOA unit is connected with the 11 th gate line, the 12 th GOA unit is connected with the 15 th gate line, the 13 th GOA unit is connected with the 4 th gate line, the 14 th GOA unit is connected with the 8 th gate line, the 15 th GOA unit is connected with the 12 th gate line, and the 16 th GOA unit is connected with the 16 th gate line.
Through the connection mode, in the display panel with 2dot inversion, when the source driver generates a data signal, the effect of 8dot inversion can be realized. For example, in a white/gray-scale screen, when driving with the conventional scheme, the timing change of the polarity of the data signal of the data line S1 can be expressed as: + + - - -; when the driving circuit of the present embodiment is used, the timing variation of the polarity of the data signal of the data line S1 can be expressed as: ++++++++ - - - - - - - -. So that the display panel with the 16CLK clock signal can further reduce the power consumption by 50% compared with the display panel with the 8CLK in the foregoing embodiment.
Similarly, in the 16CLK GOA architecture, the drive circuit can improve the charging rate while suppressing the mura defect due to the parasitic capacitance. The related principle can be referred to the explanation in the foregoing example of the 8CLK GOA architecture, and is not described here again.
It should be noted that, when the driving circuit of the display panel in this embodiment is implemented in some implementations, only the wiring between the GOA unit and the gate line may need to be adjusted, which hardly increases the manufacturing cost.
In summary, in the driving circuit of the display panel provided in this embodiment, the connection structure of the GOA unit and the gate lines is changed, so that the charging sequences of the pixels with the same defined polarity are adjacent to each other, and when the data lines transmit the data signals matched with the corresponding gate lines, the inversion times of the data signals can be reduced, thereby effectively reducing the power consumption of the display panel.
Of course, in some embodiments, the same driving result as the driving circuit of the previous embodiment can also be achieved by controlling the order of outputting the gate driving signals to the gate lines. In view of the above, the present invention provides a method for driving a display panel in another embodiment of the present invention.
Referring to fig. 12, the driving method of the display panel provided in the present embodiment can be used for driving the display panel; furthermore, the method can be applied to a driving circuit of a display panel. The display panel comprises a plurality of groups of gate lines and a plurality of data lines, wherein each group of gate lines comprises N gate lines which are sequentially arranged, N is the number of clock signal lines, and N is an even number which is more than or equal to 6.
Aiming at each group of gate lines, taking any column of pixel points defined as positive polarity and defined as negative polarity with the maximum total number as a reference, the driving method comprises the following steps:
step S10: outputting a gate drive signal to the N gate lines to sequentially drive pixels of the row defined as a first polarity, and after the driving of the pixels of the first polarity is completed, sequentially driving pixels of the row defined as a second polarity; the first and second polarities are either positive or negative, the first and second polarities being different polarities;
step S20: and for each gate line, outputting a data signal with the polarity matched with the gate driving signal to the data line based on the gate driving signal, so that the charging sequence of the pixel points with the same defined polarity is adjacent.
It should be noted that the execution of step S10 and step S20 are not in order of priority. Step S10 and step S20 are coordinated in execution. It is understood that the N gate lines output the gate driving signal according to a certain timing, and the gate driving signal may be a pulse. After any one of the gate lines outputs a driving signal, a data signal having a polarity matching the gate driving signal is also output to the data line accordingly. That is, the step S10 executes the gate driving signal output for one gate line, and the step S20 executes the data signal output corresponding to the gate driving signal output, so as to finally ensure that the charging sequences of the pixels with the same defined polarity are adjacent. Therefore, the inversion times of the data signals are reduced, and the power consumption of the display panel is reduced.
In some optional embodiments, the polarity inversion manner of the display panel may be 2-pixel inversion; the N grid lines comprise a first grid line group, a second grid line group, a third grid line group and a fourth grid line group; the first grid line group comprises 4 xK 1+1 of N grid lines, the second grid line group comprises 4 xK 2+2 of the N grid lines, the third grid line group comprises 4 xK 3+3 of the N grid lines, and the fourth grid line group comprises 4 xK 4+4 of the N grid lines, wherein K1, K2, K3 and K4 are natural numbers, and 4 xK 1+1, 4 xK 2+2, 4K 3+3 and 4 xK +4 are not more than N, and K1, K2, K3 and K4 take values from small to large in sequence.
In this case, step S10 may specifically include:
and outputting gate driving signals to the N gate lines according to the sequence of the first gate line group, the second gate line group, the third gate line group and the fourth gate line group.
In some optional embodiments, when the value of N is 8, that is, when N corresponds to a GOA architecture of 8CLK, step S10 may specifically include:
gate drive signals are output to the 8 gate lines in the order of the 1 st, 5 th, 2 nd, 6 th, 3 rd, 7 th, 4 th, and 8 th gate lines.
In some optional embodiments, when N is 6, that is, corresponding to a GOA architecture of 6CLK, step S10 may specifically include:
gate driving signals are output to the 6 gate lines in the order of the 1 st gate line, the 5 th gate line, the 2 nd gate line, the 6 th gate line, the 3 rd gate line, and the 4 th gate line.
In some optional embodiments, when the value of N is 16, that is, when the value of N corresponds to a GOA architecture of 16CLK, step S10 specifically includes:
gate driving signals are output to the 16 gate lines in the order of 1 st, 5 th, 9 th, 13 th, 2 nd, 6 th, 10 th, 14 th, 3 rd, 7 th, 11 th, 15 th, 4 th, 8 th, 12 th, and 16 th gate lines.
It should be noted that, the difference between the present embodiment and the foregoing driving circuit embodiment is that the driving method in the present embodiment adjusts the timing of outputting pulses to the gate lines, so as to change the gate line on timing, thereby achieving the purpose of reducing the number of data signal inversion times of the data lines. The manner of adjusting the timing of outputting the pulse to the gate line is not limited, and the connection manner between the GOA unit and the gate line can be changed, such as the driving circuit structure in the foregoing embodiments. The timing of outputting pulses to the gate lines may also be adjusted by changing the pulse timing of the clock signal by a Timing Controller (TCON).
In addition, the beneficial effects and related principles of the driving method of the display panel in this embodiment can be seen in the driving circuit of the display panel in the foregoing embodiment, which is not described herein again.
Referring to fig. 13, based on the same inventive concept, in another embodiment of the present invention, a driving circuit 300 for a display panel is further provided, which can be used for driving a display panel 500, the driving circuit includes a timing controller 310, a source driver 320 and a gate driver 330, and the source driver 320 and the gate driver 330 are both connected to the timing controller 310; the display panel includes a plurality of groups of gate lines 331 and a plurality of data lines 321, each group of gate lines 331 includes N gate lines 331 arranged in sequence, N is the number of clock signal lines, and N is an even number greater than or equal to 6; for each group of gate lines 331, based on any row of pixel points defined as positive polarity and defined as negative polarity with the most total number:
the timing controller 310 is configured to control the gate driver 330 to output a gate driving signal to the N gate lines 331 so as to sequentially drive the pixels of the row defined as a first polarity, and sequentially drive the pixels of the row defined as a second polarity after the pixels of the first polarity are driven; the first polarity and the second polarity are either positive polarity or negative polarity, and the first polarity and the second polarity are different polarities; for each gate line 331, the timing controller 310 is configured to control the source driver 320 to output a data signal having a polarity matching the gate driving signal to the data line 321 based on the gate driving signal, so that the charging sequence of the pixel points having the same defined polarity is adjacent.
It should be noted that, in the driving circuit 300 of a display panel according to an embodiment of the present invention, the timing controller 310, the gate driver 330 and the source driver 320 control the operation of turning on or off the gate lines 331 and the operation of controlling the data signals transmitted by the data lines 321 are the same as the driving circuit 100 in the previous embodiment. In addition, the technical effects produced are also the same as those of the foregoing embodiment of the driving circuit 100, and for the sake of brief description, reference may be made to corresponding contents in the foregoing embodiment of the driving circuit 100 where no part is mentioned in this embodiment.
Based on the same inventive concept, in another embodiment of the present invention, there is provided a display device including the driving circuit of the display panel described in any one of the foregoing embodiments. The display device in this embodiment may be a display panel, or may be a notebook computer, a television, a vehicle-mounted display screen, or the like, to which the display panel is applied. The display device in this embodiment includes the driving circuit in the foregoing embodiment, and for the advantages of the driving circuit in the foregoing embodiment, for brief description, and for parts of the embodiment that are not mentioned, reference may be made to corresponding contents in the foregoing method embodiment.
The term "and/or" appearing herein is merely one type of associative relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship; the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (10)

1. A driving circuit of a display panel, comprising: the GOA unit groups comprise N GOA units which are sequentially arranged, N is the number of clock signal lines, and N is an even number which is more than or equal to 6;
for each GOA unit group, taking any column of pixel points defined as the most positive polarity and the most negative polarity as a reference, respectively connecting the N GOA units with a gate line of the pixel points defined as the first polarity and a gate line of the pixel points defined as the second polarity according to a driving sequence, so that the pixel points with the same defined polarity are adjacent in the driving sequence, wherein the first polarity and the second polarity are either the positive polarity or the negative polarity, and the first polarity and the second polarity are different polarities;
when the N GOA units sequentially output gate driving signals, the data lines are configured to output data signals with polarities matched with the gate driving signals, so that pixel points with the same defined polarity are adjacent in charging sequence.
2. The driving circuit according to claim 1, wherein the polarity inversion scheme of the display panel is 2-pixel inversion;
the N GOA units correspond to N grid lines which are sequentially arranged, and the N grid lines comprise a first grid line group, a second grid line group, a third grid line group and a fourth grid line group; the first grid line group comprises 4 xK 1+1 of the N grid lines, the second grid line group comprises 4 xK 2+2 of the N grid lines, the third grid line group comprises 4 xK 3+3 of the N grid lines, and the fourth grid line group comprises 4K 4+4 of the N grid lines, wherein K1, K2, K3 and K4 are natural numbers, and 4 xK 1+1, 4 xK 2+2, 4 xK 3+3 and 4 xK +4 are not more than N, and K1, K2, K3 and K4 are sequentially changed from small value to large value;
the N GOA units are sequentially connected to each gate line in the first gate line group, each gate line in the second gate line group, each gate line in the third gate line group, and each gate line in the fourth gate line group.
3. The driving circuit according to claim 2, wherein when the value of N is 8, the connection sequence of the N GOA units and the N gate lines is:
the 1 st GOA unit is connected with the 1 st gate line, the 2 nd GOA unit is connected with the 5 th gate line, the 3 rd GOA unit is connected with the 2 nd gate line, the 4 th GOA unit is connected with the 6 th gate line, the 5 th GOA unit is connected with the 3 rd gate line, the 6 th GOA unit is connected with the 7 th gate line, the 7 th GOA unit is connected with the 4 th gate line, and the 8 th GOA unit is connected with the 8 th gate line.
4. A driving method of a display panel is characterized in that the method is used for driving the display panel; the display panel comprises a plurality of groups of gate lines and a plurality of data lines, each group of gate lines comprises N gate lines which are sequentially arranged, N is the number of clock signal lines, and N is an even number which is more than or equal to 6;
for each group of gate lines, based on any column of pixel points defined as positive polarity and defined as negative polarity with the maximum total number, the driving method comprises the following steps:
outputting a gate drive signal to the N gate lines to sequentially drive pixels of the row defined as a first polarity, and after the driving of the pixels of the first polarity is completed, sequentially driving pixels of the row defined as a second polarity; the first and second polarities are either positive or negative, the first and second polarities being different polarities;
and outputting a data signal with the polarity matched with the gate driving signal to the data line based on the gate driving signal aiming at each gate line so as to enable the charging sequence of the pixel points with the same defined polarity to be adjacent.
5. The driving method according to claim 4, wherein the polarity inversion scheme of the display panel is 2-pixel inversion; the N grid lines comprise a first grid line group, a second grid line group, a third grid line group and a fourth grid line group; the first grid line group comprises 4 xK 1+1 of the N grid lines, the second grid line group comprises 4 xK 2+2 of the N grid lines, the third grid line group comprises 4 xK 3+3 of the N grid lines, and the fourth grid line group comprises 4K 4+4 of the N grid lines, wherein K1, K2, K3 and K4 are natural numbers, and 4 xK 1+1, 4 xK 2+2, 4 xK 3+3 and 4 xK +4 are not more than N, and K1, K2, K3 and K4 are sequentially changed from small value to large value;
the outputting gate driving signals to the N gate lines includes:
outputting the gate driving signals to the N gate lines according to the sequence of the first gate line group, the second gate line group, the third gate line group and the fourth gate line group.
6. The driving method according to claim 5, wherein when the value of N is 8, the outputting gate driving signals to the N gate lines includes:
and outputting the gate driving signals to the 8 gate lines according to the sequence of the 1 st gate line, the 5 th gate line, the 2 nd gate line, the 6 th gate line, the 3 rd gate line, the 7 th gate line, the 4 th gate line and the 8 th gate line.
7. The driving method according to claim 5, wherein when the value of N is 6, the outputting gate driving signals to the N gate lines includes:
outputting the gate driving signal to the 6 gate lines in the order of the 1 st gate line, the 5 th gate line, the 2 nd gate line, the 6 th gate line, the 3 rd gate line and the 4 th gate line.
8. The driving method according to claim 5, wherein when the value of N is 16, the outputting gate driving signals to the N gate lines includes:
outputting the gate driving signal to 16 gate lines in the order of 1 st gate line, 5 th gate line, 9 th gate line, 13 th gate line, 2 nd gate line, 6 th gate line, 10 th gate line, 14 th gate line, 3 rd gate line, 7 th gate line, 11 th gate line, 15 th gate line, 4 th gate line, 8 th gate line, 12 th gate line, and 16 th gate line.
9. The driving circuit of the display panel is characterized by comprising a time sequence controller, a source driver and a grid driver, wherein the source driver and the grid driver are connected with the time sequence controller; the display panel comprises a plurality of groups of gate lines and a plurality of data lines, each group of gate lines comprises N gate lines which are sequentially arranged, N is the number of clock signal lines, and N is an even number which is more than or equal to 6;
regarding each group of gate lines, taking any column of pixel points defined as positive polarity and defined as negative polarity with the maximum total number as reference:
the time schedule controller is used for controlling the grid driver to output grid driving signals to the N grid lines so as to sequentially drive the pixels defined as a first polarity in the row of pixels and sequentially drive the pixels defined as a second polarity in the row of pixels after the pixels with the first polarity are driven; the first and second polarities are either positive or negative, the first and second polarities being different polarities;
and for each gate line, the time sequence controller is used for controlling the source driver to output a data signal with the polarity matched with the gate driving signal to the data line based on the gate driving signal so as to enable the charging sequence of the pixel points with the same defined polarity to be adjacent.
10. A display device comprising the display panel driving circuit according to any one of claims 1 to 3 and claim 9.
CN202210806765.9A 2022-07-08 2022-07-08 Driving circuit and driving method of display panel and display device Pending CN115064135A (en)

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