CN115061091A

CN115061091A - Radar data processing method and system and electronic equipment

Info

Publication number: CN115061091A
Application number: CN202210592153.4A
Authority: CN
Inventors: 孙旭旭; 轩阳; 王震
Original assignee: China Automotive Innovation Corp
Current assignee: China Automotive Innovation Corp
Priority date: 2022-05-27
Filing date: 2022-05-27
Publication date: 2022-09-16

Abstract

The present application relates to the field of data processing technologies, and in particular, to a radar data processing method and system, and an electronic device. The method comprises the following steps: the processing system receives a first data processing completion signal aiming at the current subframe, responds to the first data processing completion signal when not performing second data processing, performs second data processing on intermediate data of the current subframe to obtain target data of the current subframe, and simultaneously sends a first data processing signal aiming at the next subframe to the programmable logic device; the programmable logic device responds to a first data processing signal aiming at a next subframe, radar detection data of the next subframe are obtained, first data processing is carried out on the radar detection data of the next subframe, and second data processing of a current subframe and first data processing of the next subframe by the programmable logic device are processed in parallel. The processing speed of the imaging radar data can be improved, and the real-time performance and feasibility of the output target data are guaranteed.

Description

Radar data processing method and system and electronic equipment

Technical Field

The present disclosure relates to the field of data processing technologies, and in particular, to a radar data processing method, a radar data processing system, and an electronic device.

Background

An FPGA (field programmable gate array device) is a product of further development based on programmable devices such as programmable array logic, general array logic, and the like. The circuit is a semi-custom circuit in the field of application-specific integrated circuits, not only overcomes the defects of the custom circuit, but also overcomes the defect that the number of gate circuits of the original programmable device is limited.

Conventionally, 4D imaging radar data is processed using an FPGA Chip based on a System On Chip (SOC) model such as Zynq, where a part of the PL that is not related to the PL is referred to as a Processing System (PS) and a part of the PL is referred to as a Programmable Logic (PL). For an FPGA device, the PL portion and the PS portion are two relatively independent portions, and the two portions interact with each other through an AXI (Advanced eXtensible Interface) bus, an interrupt, a GPIO (General Purpose Input/Output), a shared DDR, and the like. The 4D imaging radar data is subjected to data processing by a PL portion and a PS portion, for example, the data processing of the PL portion includes FFT (fast Fourier transform) processing and NCI (Non-coherent integration) processing, and the data processing of the PS portion includes CFAR (Constant False Alarm Rate) processing and DOA (Direction of Arrival) processing.

In the data processing flow of the PL part and the PS part, imaging radar data must be processed by the PL part and the PS part in sequence to obtain target data, namely the processing processes of the PL part and the PS part are sequentially executed, after NCI of the PL part is finished, CFAR of the PS side starts to operate, and after DOA operation of the PS side is finished, a wave-transmitting signal is generated to start the next round of operation of the PL part. In the existing signal processing flow, a PL part and a PS part are tightly coupled, and the work of each part of the PL and the PS is strongly related to the other part, so that the functional module which can independently work has a waiting condition, which causes resource waste, causes the processing speed of imaging radar data to be slower, further causes the speed of outputting target data to be slower, has poorer real-time performance, and further causes the feasibility of the target data to be reduced.

Therefore, it is desirable to provide a radar data processing method, a radar data processing system, and an electronic device, which can improve the processing speed of imaging radar data and ensure the real-time performance and feasibility of output target data.

Disclosure of Invention

The embodiment of the application provides a radar data processing method, a radar data processing system and electronic equipment, which can improve the processing speed of imaging radar data and ensure the real-time performance and feasibility of output target data.

In a first aspect, an embodiment of the present application provides a radar data processing method, which is applied to an electronic device, where the electronic device includes a programmable logic device (i.e., the above PL part) and a processing system (i.e., the above PS part), and the method includes:

the processing system receives the first data processing completion signal aiming at the current subframe, responds to the first data processing completion signal when not performing second data processing, performs second data processing on intermediate data of the current subframe to obtain target data of the current subframe, and simultaneously sends a first data processing signal aiming at the next subframe to the programmable logic device; the first processing completion signal is generated after first data processing of the programmable logic device is completed, and the intermediate data of the current subframe is obtained by performing first data processing on radar detection data of the current subframe by the programmable logic device;

the programmable logic device responds to a first data processing signal which is sent by a processing system and aims at a next subframe, obtains radar detection data of the next subframe, carries out first data processing on the radar detection data of the next subframe to obtain intermediate data corresponding to the next subframe, and sends a first data processing completion signal aiming at the next subframe to the processing system;

and the processing system processes the second data of the current sub-frame in parallel with the first data of the next sub-frame processed by the programmable logic device.

In some optional embodiments, the method further comprises:

and the processing system controls the radar to detect when the second data processing is not carried out.

In some optional embodiments, the method further comprises:

and when the processing system does not receive the first data processing completion signal and does not perform second data processing, the processing system sends the first data processing signal to the programmable logic device.

In some optional embodiments, the programmable logic device is provided with a state machine, an initial state, a first state, a ping state, and a pong state, and the method further comprises:

before the programmable logic device receives the first data processing signal corresponding to the first subframe, the state machine is in the initial state;

when the programmable logic device receives the first data processing signal corresponding to a first subframe, the state machine jumps from the initial state to the first state;

when the programmable logic device generates the first data processing completion signal corresponding to the first subframe, the state machine jumps from the first state to the pong state;

and when the programmable logic device receives the first data processing signal corresponding to the non-first subframe and the adjacent next subframe, the state machine jumps between the ping state and the pong state.

In some optional embodiments, the method further comprises:

the intermediate data obtained by the programmable logic device in the pong state and the intermediate data obtained in the ping state are respectively stored in a first storage unit and a second storage unit by adopting ping-pong storage operation;

or,

after the programmable logic device performs the first data processing, storing the intermediate data obtained in the first state and the ping state in a first storage unit; and storing the intermediate data obtained in the ping state in a second storage unit.

In some optional embodiments, the method further comprises:

the processing system alternately retrieves the intermediate data from the first storage unit and the second storage unit before performing the second data processing.

In some optional embodiments, the first data processing comprises distance measurement and/or velocity measurement based on a fast fourier transform implementation.

In some optional embodiments, the second data processing comprises data screening and/or angle processing; the data screening is realized based on the constant false alarm rate detection of the processing system; the angle processing is implemented based on angle-of-arrival calculations of the processing system.

In a second aspect, an embodiment of the present application provides a radar data processing system, where the system includes: a programmable logic device and a processing system;

the processing system is used for receiving the first data processing completion signal aiming at the current subframe, responding to the first data processing completion signal when the second data processing is not carried out, carrying out the second data processing on the intermediate data of the current subframe to obtain the target data of the current subframe, and simultaneously sending a first data processing signal aiming at the next subframe to the programmable logic device; the first processing completion signal is generated after first data processing of the programmable logic device is completed, and the intermediate data of the current subframe is obtained by performing first data processing on radar detection data of the current subframe by the programmable logic device;

the programmable logic device is used for responding to a first data processing signal which is sent by a processing system and aims at a next subframe, acquiring radar detection data of the next subframe, performing first data processing on the radar detection data of the next subframe to obtain intermediate data corresponding to the next subframe, and sending a first data processing completion signal aiming at the next subframe to the processing system;

In a third aspect, an embodiment of the present application provides an electronic device, where the electronic device includes a processor and a memory, where the memory stores at least one instruction or at least one program, and the at least one instruction or the at least one program is loaded by the processor and executes the radar data processing method.

Receiving the first data processing completion signal aiming at the current subframe through a processing system, responding to the first data processing completion signal when the second data processing is not performed, performing the second data processing on the intermediate data of the current subframe to obtain the target data of the current subframe, and simultaneously sending a first data processing signal aiming at the next subframe to a programmable logic device; the method comprises the steps that a programmable logic device responds to a first data processing signal which is sent by a processing system and aims at a next subframe, obtains radar detection data of the next subframe, carries out first data processing on the radar detection data of the next subframe to obtain intermediate data corresponding to the next subframe, and sends a first data processing completion signal aiming at the next subframe to the processing system; and the processing system processes the second data of the current sub-frame in parallel with the first data of the next sub-frame processed by the programmable logic device. Therefore, the programmable logic device is controlled to perform first data processing on the radar data of the next subframe while the processing system is controlled to perform second data processing on the intermediate data of the current subframe so as to obtain the intermediate data of the next subframe, the waiting time of the programmable logic device and the processing system can be reduced, the processing speed of the radar data is improved, and the real-time performance and the feasibility of the output target data are ensured.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of radar data processing in the prior art;

fig. 2 is a schematic flowchart of a radar data processing method according to an embodiment of the present application;

FIG. 3 is a schematic diagram of another radar data processing provided by an embodiment of the present application;

FIG. 4 is a schematic flow chart diagram of another radar data processing method provided in the embodiments of the present application;

FIG. 5A is a schematic diagram of a state of a programmable logic device in radar data processing according to an embodiment of the present disclosure;

FIG. 5B is a schematic diagram of a state jump of a programmable logic device according to an embodiment of the present application;

FIG. 6 is a schematic flow chart of radar data processing at the processing system side according to an embodiment of the present disclosure;

FIG. 7 is a schematic structural diagram of a radar data processing system according to an embodiment of the present disclosure;

fig. 8 is a hardware block diagram of an electronic device for implementing a radar data processing method according to an embodiment of the present application.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the invention. In describing the present invention, it is to be understood that the terms "first," "second," "third," and "fourth," etc. in the description and claims of the present invention and the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

Referring to fig. 1, fig. 1 is a schematic diagram of radar data processing in the prior art. In the radar data processing process, first data processing (including distance dimension FFT and velocity dimension FFT) of a programmable logic device (PL part) and second data processing (including CFAR and DOA) of a processing system (PS part) are required. For example, for each subframe radar data, the processing process of the PS part generates a chirp _ start signal to the PL part, the PL part performs first data processing on each subframe radar data after receiving the chirp _ start signal to obtain intermediate data, generates nci _ done signal to the PS part after the completion of the processing, the processing time of the PL part is T1, then the PS part performs second data processing on the intermediate data after receiving nci _ done signal to obtain target data, generates doa _ done signal to the PL part after the completion of the processing, the processing time of the PS part is T2, and T2 is greater than T1, and the PS part controls radar wave transmission after obtaining the target data to obtain radar data of a next subframe and process the next subframe. The sum of the processing time of one sub-frame in the PL portion plus the processing time in the PS portion is the minimum frame period of one frame rate, and the processing time T of radar data of each sub-frame is T1+ T2. For example, suppose that the PL portion is 33ms in time, the PS portion is 67ms in time, and the corresponding frame rate is 100 ms. If 500 points are generated in one sub-frame, 5000 points are generated in 1 second.

As described above, since the programmable logic device and the processing system perform serial data processing to tightly couple the programmable logic device and the processing system, the programmable logic device and the processing system have a waiting condition, which causes waste of resources and time, and causes a slow data processing speed of radar data, and further causes a slow speed of outputting target data, a poor real-time performance, and further a reduced feasibility of the target data. The frame rate is reduced due to the fact that the time of the single subframe frame rate (time T shown in figure 1) is too long, and further the number of point clouds in unit time is reduced, and the performance index of the whole radar is affected.

In order to solve the above problem, the present application provides a radar data processing method, specifically, in which a programmable logic device responds to a first data processing signal, which is sent by a processing system and is directed to a current subframe, to obtain radar detection data of the current subframe, performs first data processing on the radar detection data of the current subframe to obtain intermediate data corresponding to the current subframe, and sends a first data processing completion signal, which is directed to the current subframe, to the processing system; the processing system receives the first data processing completion signal, and when second data processing is not performed, responds to the first data processing completion signal, performs the second data processing on the intermediate data of the current subframe, and simultaneously sends the first data processing signal for a next subframe to the programmable logic device, so that when the processing system performs the second data processing on the intermediate data of the current subframe, the programmable logic device responds to the first data processing signal for the next subframe sent by the processing system, acquires radar detection data of the next subframe, performs the first data processing on the radar detection data of the next subframe to obtain the intermediate data corresponding to the next subframe, and sends the first data processing completion signal for the next subframe to the processing system. Therefore, the data are processed in parallel through the programmable logic device and the processing system, the processing speed of the imaging radar data is improved, and the real-time performance and the feasibility of the output target data are ensured.

A specific embodiment of a radar data processing method according to the present application is described below, and fig. 2 is a schematic flow chart of a radar data processing method according to the present application. The specification provides the method steps as in the examples or flowcharts, but may include more or fewer steps based on conventional or non-inventive labor. The order of steps recited in the embodiments is merely one manner of performing the steps in a multitude of orders and does not represent the only order of execution. In practice, the system or server product may be implemented in a sequential or parallel manner (e.g., parallel processor or multi-threaded environment) according to the embodiments or methods shown in the figures. As shown in fig. 2, the method is applied to an electronic device, where the electronic device includes a programmable logic device and a processing system, and the method may include:

s202: the programmable logic device responds to a first data processing signal which is sent by a processing system and aims at a current subframe, acquires radar detection data of the current subframe, performs first data processing on the radar detection data of the current subframe to obtain intermediate data corresponding to the current subframe, and sends a first data processing completion signal aiming at the current subframe to the processing system.

In some optional embodiments, the first data processing comprises distance measurement and/or velocity measurement based on a fast fourier transform implementation. For example, the distance and the speed between each target of the radar are resolved through first data processing; and the intermediate data is 2D-FTT data including distance and velocity information.

In some optional embodiments, the current subframe may refer to a first subframe at a starting time when radar subframe data starts to be processed, or may refer to a subframe at any time after the starting time, where a next subframe refers to a subframe at a next time adjacent to the current subframe, and a previous subframe refers to a subframe at a previous time adjacent to the current subframe.

In some optional embodiments, before the radar data processing is started, neither the programmable logic device nor the processing system starts the data processing process, and at an initial time of starting the radar data processing, the processing system first sends a first data processing signal for a current subframe to the programmable logic device to instruct the programmable logic device to start the first data processing process and perform the first data processing on the current subframe. This current subframe may be understood as the first subframe of radar data.

S204: the processing system receives a first data processing completion signal aiming at the current subframe, responds to the first data processing completion signal when not performing second data processing, performs second data processing on intermediate data of the current subframe to obtain target data of the current subframe, and simultaneously sends a first data processing signal aiming at the next subframe to the programmable logic device;

In some optional embodiments, the second data processing comprises data screening and/or angle processing.

In some optional embodiments, the data screening is implemented based on Constant False Alarm Rate (CFAR) of the processing system; the angle processing is implemented based on the angle of Arrival (i.e., DOA) calculation of the processing system. And performing second data processing on the intermediate data to obtain target data of the frame.

In some alternative embodiments, the first data processing time T1 is less than the second data processing time T2, and a case where the second data processing of the current sub-frame by the processing system is processed in parallel with the first data processing of the next sub-frame by the programmable logic device means that the first data processing of the programmable logic device is started and completed within the processing time of the second data processing by the processing system, which is the second data processing time T2. It is to be understood that the present application is not limited to the time relationship between the first data processing and the second data processing, i.e., the first data processing time T1 may be greater than, less than or equal to the second data processing time T2.

In some alternative embodiments, the content of step 204 is continuously cycled, during the first T2 time period, the processing system processes the second data of the current sub-frame in parallel with the first data of the next sub-frame processed by the programmable logic device, during the second T2 time period, the processing system processes the second data of the next sub-frame in parallel with the first data of the next sub-frame processed by the programmable logic device, and so on, until the radar data of the last sub-frame is processed.

In some alternative embodiments, the processing time of the first data processing time T1 is included in the second data processing time T2, so that the single subframe processing time T is reduced from the previous T1+ T2 to T2.

In the above embodiment, the processing system receives the first data processing completion signal for the current subframe, and when the second data processing is not performed, the processing system performs the second data processing on the intermediate data of the current subframe in response to the first data processing completion signal to obtain the target data of the current subframe, and sends the first data processing signal for the next subframe to the programmable logic device; the programmable logic device responds to a first data processing signal which is sent by a processing system and aims at a next subframe, obtains radar detection data of the next subframe, carries out first data processing on the radar detection data of the next subframe to obtain intermediate data corresponding to the next subframe, and sends a first data processing completion signal aiming at the next subframe to the processing system; and the processing system processes the second data of the current sub-frame in parallel with the first data of the next sub-frame processed by the programmable logic device. And controlling the programmable logic device to perform first data processing on the radar data of the next subframe while performing second data processing on the intermediate data of the current subframe through the control processing system so as to obtain the intermediate data of the next subframe. The method has the advantages of reducing the waiting time of a processing system and a programmable logic device, improving the processing speed of radar data, improving the frame rate and ensuring the real-time performance and feasibility of output target data.

The radar data processing method according to the embodiment of the present application is further described below with reference to fig. 3. As shown in fig. 3, in some embodiments, at an initial time, the processing system first transmits (i.e., PS TO PL) a first data processing signal chirp _ start for a first subframe TO the programmable logic device;

after receiving the signal chirp _ start, the programmable logic device starts to perform first data processing on the first subframe to obtain intermediate data of the first subframe, and after the first data processing is completed, the programmable logic device sends (namely PLTO PS) a first data processing completion signal Nci _ done for the first subframe to a processing system;

the processing system receives the signal Nci _ done, determines that the received first signal Nci _ done is the first signal Nci _ done, and generates a first data processing signal chirp _ start for the second subframe again, so that the programmable logic device starts to perform first data processing on the second subframe after receiving the signal chirp _ start to obtain intermediate data of the second subframe, and after the first data processing is completed, the programmable logic device sends (namely PLTO PS) a first data processing completion signal Nci _ done for the second subframe to the processing system;

and simultaneously, starting to perform second data processing on the intermediate data of the first subframe in response to the first signal Nci _ done, obtaining target data of the first subframe after the second data processing is completed, and generating a second data processing completion signal doa _ done of the first subframe. At this point, the data processing process of the first sub-frame is completed. Since the PS processing time is generally longer than the PL processing time, the nci _ done signal for the second subframe is generally generated earlier than the first subframe doa _ done signal, which is the case shown in the figure;

when receiving a first processing completion signal Nci _ done sent by the programmable logic device for a second subframe by the processing system, and when obtaining a second processing completion signal doa _ done for a first subframe, generating a chirp _ start signal for a third subframe again, so that after receiving the chirp _ start signal, the programmable logic device starts to perform first data processing on the third subframe to obtain intermediate data of the third subframe, and after completing the first data processing, the programmable logic device sends (i.e., PLTO PS) the first data processing completion signal Nci _ done for the third subframe to the processing system;

and simultaneously, starting to perform second data processing on the intermediate data of the second subframe in response to the second signal Nci _ done, obtaining target data of the second subframe after the second data processing is completed, and generating a second data processing completion signal doa _ done of the second subframe. And finishing the data processing process of the second sub-frame.

The subsequent circulation carries out the independent ping-pong pipeline operation of the PL and the PS, the PL and the PS are not closely coupled like the serial connection before, and waiting is not carried out.

In summary, by decoupling and adjusting the PL and PS serial close coupling modes, under a new interaction mechanism, the latency of each module is reduced, and the frame rate of radar signal processing can be improved. For example, the PL side time is 33ms, the PS side time is 67ms, the original serial frame rate is 100ms, and the frame rate can be reduced to 67ms after the scheme of the present application is adopted.

Fig. 4 is a schematic flowchart of another radar data processing method provided in the embodiment of the present application, and as shown in fig. 4, the method includes steps shown in fig. 2, i.e., steps S202 to S204, which are not repeated herein for the contents of the steps in fig. 2. The method comprises the following specific steps:

before the programmable logic device receives the first data processing signal in step S202, step S201 is performed, and the processing system sends the first data processing signal.

S201: and when the processing system does not receive the first data processing completion signal and does not perform the second data processing, the processing system sends a first data processing signal to the programmable logic device.

After the processing system processes the second data in step S204, the process proceeds to step S206, and the processing system controls the radar to perform detection.

S206: and the processing system controls the radar to detect when the second data processing is not carried out.

Through the embodiment, the processing system controls the programmable logic device according to the control condition of the first data processing signal, the processing system and the programmable logic device can simultaneously process data, the waiting time is reduced, and the data processing speed is improved.

Referring to fig. 3, before the processing system controls the radar to transmit waves for the first time, the processing system does not receive the first data processing completion signal, and does not perform the second data processing, and then the processing system controls the radar to perform detection. And after the radar receives the control information, initializing, calibrating and sending waves.

Referring to fig. 3, when the processing system receives the first data processing completion signal, the processing system starts the second data processing, sends the first data processing signal to the programmable logic device, and controls the radar to detect. And after the radar receives the control information, initializing, calibrating and sending the wave again. And when the processing system processes second data processing corresponding to the first data processing completion signal, the programmable logic device responds to the first data processing signal and starts to receive detection data of the radar and perform first data processing.

As shown in fig. 3, when the processing system receives the second first data processing completion signal (i.e., generates the intermediate data corresponding to the third subframe), after the second data processing corresponding to the first data processing completion signal is completed (i.e., the second data processing is completed for the intermediate data corresponding to the second subframe), the processing system sends the third first data processing signal to the programmable logic device, controls the editable logic device to perform the first data processing on the radar data of the third subframe, and simultaneously performs the second data processing on the intermediate data corresponding to the second subframe (i.e., performs the parallel first data processing on the radar data of the second subframe and the parallel second data processing on the intermediate data of the third subframe), and controls the radar to detect.

The radar data processing method is further described below with reference to fig. 5A, 5B, and 6.

In some optional embodiments, the programmable logic device is provided with a state machine, an initial state, a first state, a ping state, and a pong state;

before the programmable logic device receives the target signal corresponding to the first subframe, the state machine is in the initial state;

when the programmable logic device receives the target signal corresponding to a first subframe, the state machine jumps from the initial state to the first state;

and when the programmable logic device generates the first data processing completion signal corresponding to the first subframe, the state machine jumps from the first state to the pong state.

And when the programmable logic device receives the target signal corresponding to the non-first subframe and the adjacent next subframe, the state machine jumps between the ping state and the pong state.

In some optional embodiments, the state machine transitions between the ping state and the pong state when the programmable logic device receives the first data processing signal corresponding to a current subframe and an adjacent next subframe.

For example, fig. 5B is a schematic diagram of state jump of the programmable logic device provided in the embodiment of the present application, where the initial state is the IDEL state shown in the diagram; the first state is the state Master _ one shown in the figure; the ping state is the state Master _ ping shown in the figure; state Master _ pang shown in the pong state diagram. The first data processing signal is the signal chirp _ start in the figure.

For example, fig. 5A is a state diagram of a programmable logic device in radar data processing according to an embodiment of the present application, where the programmable logic device (i.e., PL) receives the first signal chirp _ start shown in fig. 3, the programmable logic device enters the state Master _ one from the initial state, the programmable logic device jumps from the state Master _ one to the state Master _ pang when the first signal nci _ done is generated, the programmable logic device jumps from the state Master _ pang to the state Master _ ping when the second signal chirp _ start is received, the programmable logic device jumps from the state Master _ pang to the state Master _ pang when the third signal chirp _ start is received, and so on, jumps between the state Master _ ping and the state Master _ pang.

In the embodiment, the state transition of the programmable logic device is further facilitated by setting the state machine, the state jump condition is designed, the waiting time of each module is reduced, and the radar data processing frame rate is improved.

In some optional embodiments, the intermediate data obtained by the programmable logic device in the pong state and the intermediate data obtained in the ping state are respectively stored in the first storage unit and the second storage unit by using a ping-pong storage operation.

For example, after the first data processing is performed by the programmable logic device, the intermediate data obtained in the first state and the pong state are stored in a first storage unit; and storing the intermediate data obtained in the ping state in a second storage unit.

For example, as shown in fig. 5A, the programmable logic device stores the intermediate data obtained in the state Master _ one (i.e., in the first state) and the state Master _ pan (i.e., in the pong state) in the first storage unit, and stores the intermediate data obtained in the state Master _ ping (i.e., in the ping state) in the second storage unit.

The first storage unit and the second storage unit may be implemented in a variety of ways, and the implementation ways are not limited in the present application. For example, different Data banks in a DDR (Double Data Rate Synchronous Random Access Memory) are used to form the first Memory unit and the second Memory unit, respectively. For another example, the first storage unit and the second storage unit are implemented by different RAMs (Random Access memories).

In some optional embodiments, the processing system alternately retrieves the intermediate data from the first storage unit and the second storage unit before performing the second data processing.

For example, after the FFT on the PL side is completed, the DDR-Ping address is first placed, then the DDR-Ping address is placed, and the cycle is performed sequentially, so when the PS takes the 2D-FFT data, the PS also needs to take the above sequence, that is, the first frame 2D-FFT data preparation corresponds to DDR-Ping, the next frame 2D-FFT data preparation corresponds to DDR-Ping, and the next frame 2D-FFT data preparation corresponds to DDR-Ping.

In the embodiment, by using a ping-pong storage manner, that is, two storage units are used for storing intermediate data of different subframes, compared with a sequential storage manner in the prior art, the capacity of the storage unit can be reduced, and the storage efficiency can be further improved. And the processing system alternately identifies and reads the intermediate data of different sub-frames from different storage units, so that the data reading efficiency can be improved.

Fig. 6 is a schematic flowchart of a process of processing radar data by a processing system side according to an embodiment of the present application, and an implementation of the radar data processing method according to the present application in the foregoing embodiment is described below by taking a process of processing radar data by a processing system side as a main line, with reference to fig. 3, fig. 5A, and fig. 5B. The method comprises the following specific steps:

s601: controlling radar initialization and calibration. The processing system controls radar initialization and calibration in preparation for subsequent radar launches.

S602: controlling the radar to emit waves. The processing system controls the radar transmission and sends a first signal chirp start (corresponding to the first data processing signal in the above-described embodiment) to the programmable logic.

For the programmable logic device side, the programmable logic device is in an initial state, i.e., IDLE (as shown in fig. 5A and 5B), before receiving the first signal chirp _ start shown in fig. 3; after the programmable logic device receives the first signal chirp _ start, the programmable logic device enters a state Master _ one shown in fig. 5A and 5B, and acquires radar data of the first subframe and performs first data processing on the radar data of the first subframe.

S603: it is determined whether a signal Nci _ done is received. That is, the processing system determines whether a signal Nci _ done has been received.

After the first data processing is performed on the radar data of the first sub-frame, the programmable logic device shown in fig. 3 obtains intermediate data of the first sub-frame, generates a first signal Nci _ done, and stores the intermediate data of the first sub-frame in a first memory address (shown in fig. 5A) of a memory.

If the processing system determines that the first signal Nci _ done is received, then step S604 is performed to prepare intermediate data of the first subframe; simultaneously, steps S601 and S602 are also carried out to control the radar to send waves and generate radar data of the next frame; and sending a second signal chirp start to the programmable logic device.

In response to the second signal chirp _ start, as shown in fig. 5B, the programmable logic device receives the second signal chirp _ start, enters the state Master _ pang, processes the first data of the radar data of the second subframe to obtain intermediate data of the second subframe, stores the intermediate data of the second subframe in a second memory address of the memory (shown in fig. 5A), and sends a second signal Nci _ done to the processing system.

After step S603 is performed again, the processing system determines that the non-primary signal Nci _ done (i.e., the second signal Nci _ done) is received, and then proceeds to step S606 to prepare intermediate data of the next subframe.

S604: intermediate data of the first subframe is prepared. For example, the processing system obtains the intermediate data of the first subframe from the memory based on the first memory address.

S605: CFAR treatment and DOA treatment. The processing system performs a second data process, the second data process comprising a CFAR process and a DOA process.

S606: intermediate data of the next subframe is prepared. And if the processing system is ready to acquire the intermediate data of the second subframe based on the second memory address.

As shown in fig. 3, the first signal is generated when the processing system completes the second data processing of the intermediate data of the first sub-frame. The process proceeds to step S606, where it is determined whether signal doa _ done is generated.

S607: a determination is made as to whether signal doa _ done is generated. If the processing system determines that the signal doa _ done is generated, step S601 is performed, and based on receiving the second signal Nci _ done and the first signal doa _ done, a third signal chirp _ start (as shown in fig. 3) is sent to the programmable logic device, and the editable logic device responds to the third signal chirp _ start, as shown in fig. 5A and 5B, enters a state Master _ ping, acquires radar data of a third subframe, and performs first data processing to obtain intermediate data of the third subframe.

If the processing system determines that signal doa _ done is not generated, it continues to wait and query signal doa _ done. If the processing system does not generate the signal doa _ done within the preset time in step S607, the signal err is sent to the editable logic device (shown in fig. 5B), and the editable logic device enters the initial state.

As shown in fig. 6, when the PS part completes the second data processing (step S603), the PS part acquires intermediate data of the next subframe from the PL part, and controls the radar to perform initialization and wave transmission. In order to increase the data processing speed of the PS part, in some optional embodiments, the PS part adopts a multi-core processing flow shown in fig. 6, wherein steps S601 to S603 (i.e. controlling the radar to perform initialization and wave generation) shown in fig. 6 adopt a first core (core0) to perform processing; steps S604 to S607 (i.e., acquiring the intermediate data of the next subframe and performing the second data processing) are processed using the second core (core 1).

As described above, the editable logic device associates with the memory address for storing data by setting the jump of the state, so that the intermediate data generated in different states are stored in the corresponding memory address, i.e. ping-pong storage. The processing system controls the signal chirp _ start through the signal Nci _ done and the signal doa _ done to realize control of first data processing on the editable logic device and realize simultaneous start of data processing; wherein the editable logic device sends information that the first data processing has been performed to the processing system via signal Nci _ done.

The radar data processing method is realized through a radar data processing system. Fig. 7 is a schematic structural diagram of a radar data processing system according to an embodiment of the present application. As shown in fig. 7, the radar data processing system includes a programmable logic device and a processing system.

The programmable logic device is used for responding to a first data processing signal which is sent by a processing system and aims at a current subframe, acquiring radar detection data of the current subframe, carrying out first data processing on the radar detection data of the current subframe to obtain intermediate data corresponding to the current subframe, and sending a first data processing completion signal aiming at the current subframe to the processing system;

the processing system is used for receiving the first data processing completion signal aiming at the current subframe, responding to the first data processing completion signal when not performing second data processing, performing the second data processing on the intermediate data of the current subframe, and simultaneously sending the first data processing signal aiming at the next subframe to the programmable logic device;

In some optional embodiments, the data screening is based on a constant false alarm detection implementation of the processing system; the angle processing is implemented based on angle-of-arrival calculations of the processing system.

In some optional embodiments, the processing system controls the radar to detect when the second data processing is not performed.

In some optional embodiments, the processing system sends the first data processing signal to the programmable logic device when the first data processing completion signal is not received and the second data processing is not performed.

In some optional embodiments, the programmable logic device stores the intermediate data in a memory after performing the first data processing; and the intermediate data of the current subframe and the intermediate data corresponding to the adjacent subframe adopt ping-pong storage.

According to the embodiment, the programmable logic device responds to a first data processing signal which is sent by the processing system and aims at the current subframe, carries out first data processing on radar detection data of the current subframe to obtain intermediate data corresponding to the current subframe, and sends a first data processing completion signal aiming at the current subframe to the processing system; when the processing system does not perform second data processing, responding to a first data processing completion signal, performing second data processing on intermediate data of a current subframe, and simultaneously sending a first data processing signal aiming at a next subframe to a programmable logic device, so that the programmable logic device responds to the first data processing signal aiming at the next subframe sent by the processing system, acquires radar detection data of the next subframe, performs first data processing on the radar detection data of the next subframe to obtain intermediate data corresponding to the next subframe, and sends the first data processing completion signal aiming at the next subframe to the processing system; and the processing system processes the second data of the current sub-frame in parallel with the first data of the next sub-frame processed by the programmable logic device. And controlling the programmable logic device to perform first data processing on the radar data of the next subframe while performing second data processing on the intermediate data of the current subframe through the control processing system so as to obtain the intermediate data of the next subframe. The method has the advantages of reducing the waiting time of a processing system and a programmable logic device, improving the processing speed of radar data, improving the frame rate and ensuring the real-time performance and feasibility of output target data.

Therefore, the radar data processing method is realized through the radar data processing system.

Fig. 8 is a hardware structure block diagram of an electronic device for implementing a radar data processing method according to an embodiment of the present application. The electronic device may be a server or a terminal device, and its internal structure diagram may be as shown in fig. 8. As shown in fig. 8, the electronic device 800 may have a relatively large difference due to different configurations or performances, and may include one or more Central Processing Units (CPUs) 810 (the CPU 810 may include but is not limited to a Processing device such as a microprocessor MCU or a programmable logic device FPGA), a memory 830 for storing data, one or more storage media 820 (e.g., one or more mass storage devices) for storing applications 823 or data 822. Memory 830 and storage medium 820 may be, among other things, transient or persistent storage. The program stored in storage medium 820 may include one or more modules, each of which may include a series of instruction operations for a server. Still further, central processor 810 may be configured to communicate with storage medium 820 to execute a series of instruction operations in storage medium 820 on electronic device 800. The electronic device 800 may also include one or more power supplies 850, one or more wired or wireless network interfaces 850, one or more input-output interfaces 840, and/or one or more operating systems 821, such as Windows, Mac OS, Unix, Linux, FreeBSD, and so forth.

The input-output interface 840 may be used to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the electronic device 800. In one example, i/o Interface 840 includes a Network adapter (NIC) that may be coupled to other Network devices via a base station to communicate with the internet. In one example, the input/output interface 840 may be a Radio Frequency (RF) module, which is used to communicate with the internet in a wireless manner.

The power supply 860 may be logically coupled to the cpu 810 through a power management system, thereby implementing functions of managing charging, discharging, and power consumption management through the power management system.

It will be understood by those skilled in the art that the structure shown in fig. 8 is only an illustration and is not intended to limit the structure of the electronic device. For example, electronic device 800 may also include more or fewer components than shown in FIG. 8, or have a different configuration than shown in FIG. 8.

Embodiments of the present application also provide a computer storage medium, in which at least one instruction or at least one program is stored, and the at least one instruction or the at least one program is loaded and executed by a processor to implement the above-mentioned radar data processing method.

Alternatively, in this embodiment, the storage medium may be located in at least one network server of a plurality of network servers of a computer network. Optionally, in this embodiment, the storage medium may include but is not limited to: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

The embodiment of the present application further provides an electronic device, where the electronic device at least includes a central processing unit 810 and a memory 830, where the memory 830 stores at least one instruction or at least one program, and the at least one instruction or the at least one program is loaded by the central processing unit 810 and executes the radar data processing method.

As can be seen from the embodiments of the radar data processing method, the system, the medium, and the electronic device provided by the present application, the programmable logic device responds to a first data processing signal for a current subframe sent by the processing system, acquires radar detection data for the current subframe, performs first data processing on the radar detection data for the current subframe to obtain intermediate data corresponding to the current subframe, and sends a first data processing completion signal for the current subframe to the processing system according to the intermediate data; the processing system receives a first data processing completion signal, responds to the first data processing completion signal when second data processing is not performed, performs second data processing on intermediate data of a current subframe, and simultaneously sends a first data processing signal for a next subframe to the programmable logic device, the programmable logic device responds to the first data processing signal for the next subframe sent by the processing system, acquires radar detection data of the next subframe, performs first data processing on the radar detection data of the next subframe to obtain intermediate data corresponding to the next subframe, and sends the first data processing completion signal for the next subframe to the processing system; and the processing system processes the second data of the current sub-frame in parallel with the first data of the next sub-frame processed by the programmable logic device. Therefore, the programmable logic device is controlled to perform first data processing on the radar data of the next subframe while the processing system is controlled to perform second data processing on the intermediate data of the current subframe so as to obtain the intermediate data of the next subframe, the waiting time of the programmable logic device and the processing system can be reduced, the processing speed of the radar data is improved, and the real-time performance and the feasibility of the output target data are ensured.

It should be noted that: the sequence of the embodiments of the present application is only for description, and does not represent the advantages or disadvantages of the embodiments. And specific embodiments thereof have been described above. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

The above description is only a preferred embodiment of the present application and should not be taken as limiting the present application, and any modifications, equivalents, improvements and the like that are made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A radar data processing method applied to electronic equipment, wherein the electronic equipment comprises a programmable logic device and a processing system, and the method is characterized by comprising the following steps:

the processing system receives the first data processing completion signal aiming at the current subframe, responds to the first data processing completion signal when not performing second data processing, performs the second data processing on the intermediate data of the current subframe to obtain target data of the current subframe, and simultaneously sends the first data processing signal aiming at the next subframe to a programmable logic device; the first processing completion signal is generated after the first data processing of the programmable logic device is completed, and the intermediate data of the current subframe is obtained by performing first data processing on the radar detection data of the current subframe by the programmable logic device;

the programmable logic device responds to a first data processing signal which is sent by a processing system and aims at the next subframe, obtains radar detection data of the next subframe, carries out first data processing on the radar detection data of the next subframe to obtain intermediate data corresponding to the next subframe, and sends a first data processing completion signal aiming at the next subframe to the processing system;

and the second data processing of the current sub-frame by the processing system is parallel to the first data processing of the next sub-frame by the programmable logic device.

2. The method of claim 1, further comprising:

3. The method of claim 1, wherein the programmable logic device is provided with a state machine comprising a ping state and a pong state, the method further comprising:

and when the programmable logic device receives the first data processing signals corresponding to the current subframe and the adjacent next subframe, the state machine jumps between the ping state and the pong state.

4. The method of claim 3, wherein the state machine comprises an initial state and a first state, the method further comprising:

the programmable logic device is in the initial state prior to receiving the first data processing signal for a first subframe;

5. The method of claim 3, further comprising:

and the intermediate data obtained by the programmable logic device in the pong state and the intermediate data obtained in the ping state are respectively stored in a first storage unit and a second storage unit by adopting ping-pong storage operation.

6. The method of claim 5, further comprising:

the processing system alternately acquires the intermediate data from the first storage unit and the second storage unit before performing the second data processing.

7. The method according to claim 1, characterized in that the first data processing comprises distance and/or velocity measurements based on fast fourier transform implementations.

8. The method according to claim 1 or 7, wherein the second data processing comprises data screening and/or angle processing; the data screening is realized based on the constant false alarm rate detection of the processing system; the angle processing is implemented based on angle-of-arrival calculations of the processing system.

9. A radar data processing system, the system comprising: a programmable logic device and a processing system;

the processing system receives the first data processing completion signal for the current subframe, responds to the first data processing completion signal when second data processing is not performed, performs the second data processing on the intermediate data of the current subframe to obtain target data of the current subframe, and simultaneously sends the first data processing signal for the next subframe to a programmable logic device; the first processing completion signal is generated after the first data processing of the programmable logic device is completed, and the intermediate data of the current subframe is obtained by performing first data processing on the radar detection data of the current subframe by the programmable logic device;

the programmable logic device is configured to respond to a first data processing signal, sent by a processing system, for the next subframe, obtain radar detection data of the next subframe, perform the first data processing on the radar detection data of the next subframe to obtain intermediate data corresponding to the next subframe, and send a first data processing completion signal, sent to the processing system, for the next subframe;

and the second data processing of the current sub-frame by the processing system and the first data processing of the next sub-frame by the programmable logic device are processed in parallel.

10. An electronic device, characterized in that the electronic device comprises a processor and a memory, in which at least one instruction or at least one program is stored, which is loaded by the processor and executes the radar data processing method according to any one of claims 1-8.