CN115037900A - Image signal transmission device and signal output circuit with bandwidth increasing mechanism thereof - Google Patents
Image signal transmission device and signal output circuit with bandwidth increasing mechanism thereof Download PDFInfo
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- CN115037900A CN115037900A CN202110241068.9A CN202110241068A CN115037900A CN 115037900 A CN115037900 A CN 115037900A CN 202110241068 A CN202110241068 A CN 202110241068A CN 115037900 A CN115037900 A CN 115037900A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
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Abstract
A signal output circuit with a bandwidth boosting mechanism, applied in an image signal transmission apparatus, comprises: a front stage driving circuit and a rear stage driving circuit. The pre-driver circuit includes a continuous time linear equalizer and is configured to receive a digital input signal for high frequency enhancement to increase a bandwidth of the digital input signal and generate a pre-output signal, wherein a zero and two poles of a frequency response of the pre-driver circuit are determined by a plurality of circuit parameter values of the pre-driver circuit. The rear stage driving circuit is configured to receive the front stage output signal for amplification to generate a rear stage output signal to the image signal receiving device.
Description
Technical Field
The present disclosure relates to signal output technologies, and more particularly, to an image signal transmission apparatus and a signal output circuit thereof with a bandwidth boosting mechanism
Background
The High Definition Multimedia Interface (HDMI) is a fully digital interface for transmitting uncompressed audio and video signals. Because the same wire rod can be adopted to simultaneously transmit audio and video signals, the transmission technology of the high-definition multimedia interface greatly simplifies the installation difficulty of the system circuit.
The system adopting the transmission technology comprises a source end for transmitting the video-audio signals and a receiving end for receiving the video-audio signals. The source needs to properly adjust the video signal by means of the signal output circuit, so that the receiving end receives the high-quality video signal. However, the signal output circuit often cannot achieve both of the signal quality and the power consumption.
Disclosure of Invention
In view of the problems of the prior art, an object of the present application is to provide an image signal transmitting apparatus and a signal output circuit having a bandwidth boosting mechanism thereof, so as to improve the prior art.
The present application includes a signal output circuit with a bandwidth boosting mechanism, applied in an image signal transmission apparatus (TX), comprising: a front stage driving circuit and a rear stage driving circuit. The pre-stage driving circuit comprises a Continuous Time Linear Equalizer (CTLE) and is configured to receive a digital input signal and perform high frequency enhancement to improve the bandwidth of the digital input signal so as to generate a pre-stage output signal, wherein a zero point and two poles of the frequency response of the pre-stage driving circuit are determined by a plurality of circuit parameter values of the pre-stage driving circuit. The rear stage driving circuit is configured to receive the front stage output signal and amplify the front stage output signal to generate a rear stage output signal to the image signal receiving device (RX).
The present application further includes an image signal transmitting apparatus applied to an image signal transmission system, including: a digital signal processing circuit and a signal output circuit. The digital signal processing circuit is configured to generate a digital input signal. A signal output circuit comprising: a front stage driving circuit and a rear stage driving circuit. The pre-stage driving circuit comprises a continuous time linear equalizer and is configured to receive a digital input signal and perform high frequency enhancement to improve the bandwidth of the digital input signal so as to generate a pre-stage output signal, wherein a zero point and two poles of the frequency response of the pre-stage driving circuit are determined by a plurality of circuit parameter values of the pre-stage driving circuit. The rear stage driving circuit is configured to receive the front stage output signal for amplification to generate a rear stage output signal to the image signal receiving device of the image signal transmission system.
The features, practical operation and efficacy of the present application will now be described in detail with reference to the preferred embodiments with reference to the accompanying drawings.
Drawings
The foregoing and other objects, features, advantages and embodiments of the present application will be more readily understood from the following description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a block diagram of an image signal transmission system according to some embodiments of the present application;
FIG. 2 is a circuit diagram of a pre-driver circuit according to some embodiments of the present application;
FIG. 3 is a schematic diagram of a frequency response of a pre-driver circuit according to some embodiments of the present application; and
fig. 4 is a diagram illustrating a frequency response of a pre-stage driving circuit according to some embodiments of the present disclosure under a condition that a resistance value of a variable resistor and a capacitance value of a variable capacitor are different.
Detailed Description
The term "coupled," as used herein, may also mean "electrically coupled," and the term "connected" may also mean "electrically connected. "coupled" and "connected" may also mean that two or more elements co-operate or interact with each other.
An objective of the present invention is to provide an image signal transmitting apparatus and a signal output circuit having a bandwidth boosting mechanism, which achieve the objectives of high bandwidth and low power consumption through the configuration of a preceding stage driving circuit.
Please refer to fig. 1. Fig. 1 shows a block diagram of an image signal transmission system 100 according to an embodiment of the present application. The image signal transmission system 100 includes an image signal transmission device (TX)110 and an image signal reception device (RX) 120.
In one embodiment, the video signal transmission system 100 is a system for transmitting video and audio according to a high-definition multimedia interface. The image signal transmission device 110 is a source terminal (source), such as but not limited to a set-top box, a DVD player, a computer, and so on. The image signal receiving device 120 is a receiving end (sink) such as, but not limited to, a television, a projector, or other display device. The video signal transmitter 110 is configured to process the video signal and transmit the processed video signal to the video signal receiver 120 for playing.
The image signal transmitting apparatus 110 includes a digital signal processing circuit 130 and a signal output circuit 140.
The digital signal processing circuit 130 is configured to generate digital input signals Vip, Vin in differential (differential) form. The signal output circuit 140 has a bandwidth boosting mechanism to enhance the output of the digital input signals Vip and Vin. The signal output circuit 140 includes: a front-stage driving circuit 150 and a rear-stage driving circuit 160.
The pre-driver circuit 150 is configured to receive the digital input signals Vip and Vin for high frequency enhancement, so as to increase the bandwidths of the digital input signals Vip and Vin, and further generate pre-output signals Vop1 and Von 1. The output signals Vop1 and Von1 at the front stage are also differential signals.
Please refer to fig. 2. Fig. 2 shows a circuit diagram of the pre-driver circuit 150 according to an embodiment of the present application. In one embodiment, the pre-driver circuit 150 includes a continuous time linear equalizer, and the continuous time linear equalizer includes two input transistors MN1, MN2, two load resistors R1, R2, two load capacitors C1, C2, a variable resistor R3, a variable capacitor C3, and two current sources I1, I2.
Each of the input transistors MN1, MN2 includes a gate, a drain, and a source. Wherein the gate of input transistor MN1 is configured to receive a digital input signal Vip. The gate of input transistor MN2 is configured to receive a digital input signal Vin. The drain of the input transistor MN1 is electrically coupled to the output terminal O1, and the drain of the input transistor MN2 is electrically coupled to the output terminal O2. The drain of the input transistor MN1 is configured to generate a previous stage output signal Vop1 to the output terminal O1, and the drain of the input transistor MN2 is configured to generate a previous stage output signal Von1 to the output terminal O2.
The load resistor R1 is electrically coupled between the drain of the input transistor MN1 and the operating voltage source VDD. The load resistor R2 is electrically coupled between the drain of the input transistor MN2 and the operating voltage source VDD. The load capacitor C1 is electrically coupled between the drain of the input transistor MN1 and the ground GND. The load capacitor C2 is electrically coupled between the drain of the input transistor MN2 and the ground GND. The variable resistor R3 and the variable capacitor C3 are electrically connected in parallel between the sources of the input transistors MN1 and MN 2. The current source I1 is electrically coupled between the source of the input transistor MN1 and the ground GND. The current source I2 is electrically coupled between the source of the input transistor MN2 and the ground GND.
In one embodiment, the zero and two poles of the frequency response of pre-driver circuit 150 are determined by a plurality of circuit parameter values of pre-driver circuit 150.
Please refer to fig. 3. Fig. 3 is a schematic diagram illustrating a frequency response of the pre-driver circuit 150 according to an embodiment of the present disclosure. Wherein the horizontal axis is frequency and the vertical axis is gain.
In one embodiment, the circuit parameters of the pre-stage driving circuit 150 include transconductance of transistors, resistance values of resistors, and capacitance values of capacitors. For example, transconductance (transconductance) of the input transistors MN1 and MN2 is gm, resistance of the load resistors R1 and R2 is Rd, capacitance of the load capacitors C1 and C2 is Cd, resistance of the variable resistor is Rs, and capacitance of the variable capacitor is Cs.
Therefore, as for the frequency response of the pre-driver circuit 150, the transfer function h(s) can be expressed as follows:
H(s)＝(gmRd)(1+sRsCs)/((1+sRcCs+(gmRs/2))/(1+sRdCd)')
also, the dc gain of the preceding stage driving circuit 150 can be expressed as follows:
(gmRd)/(1+(gmRs/2))
zero ω on the frequency response Z Can be represented by the following formula:
ω Z ＝1/(RsCs)
one pole ω of which P1 Can be represented by the following formula:
ω P1 ＝(1+gmRs/2)/(RsCs)
another pole ω P2 Can be represented by the following formula: 1/(RdCd)
ω P2 ＝1/(RdCd)
Therefore, by adjusting the above circuit parameters, the zero and two poles of the frequency response of the pre-driver circuit 150 can be changed accordingly, thereby increasing the dc gain and the high frequency component to different degrees.
Please refer to fig. 4. Fig. 4 is a schematic diagram illustrating a frequency response of the pre-stage driving circuit 150 in an embodiment of the present application under a condition that a resistance Rs of the variable resistor and a capacitance Cs of the variable capacitor are different. Wherein the horizontal axis is frequency and the vertical axis is gain.
In fig. 4, the direction of the arrow labeled Rs represents the trend of the frequency response as the resistance value Rs is larger. As shown in fig. 4, the larger the resistance Rs, the smaller the dc gain will be. On the other hand, the arrow labeled Cs represents the trend of the frequency response as the capacitance Cs is larger. As shown in fig. 4, the positions of the zero and the pole are shifted toward the low frequency direction as the capacitance Cs is larger.
Therefore, under the selection of the appropriate resistance Rs and capacitance Cs, the pre-stage driving circuit 150 can improve the response of the digital input signals Vip and Vin at high frequency, thereby increasing the bandwidths of the digital input signals Vip and Vin.
The rear stage driving circuit 160 is configured to receive the front stage output signals Vip and Vin for amplification, so as to generate the rear stage output signals Vop2 and Von2 to the image signal receiving device 120. In one embodiment, the post driver circuit includes a Current Mode Logic (CML) circuit. The rear stage output signals Vop2 and Von2 are also differential signals.
In some techniques, the signal output circuit is amplified by a two-stage current-mode logic circuit. However, in such a manner, the current-mode logic circuit consumes a large current, and thus the power saving purpose cannot be achieved.
In contrast, the signal output circuit of the present application can improve the bandwidth of the output signal through the arrangement of the preceding stage driving circuit implemented by the continuous time linear equalizer, under the condition of low current consumption, and simultaneously achieve the efficacy of high bandwidth and low power consumption.
It should be noted that the above-mentioned embodiment is only an example. In other embodiments, those skilled in the art can make variations without departing from the technical idea of the present application.
In summary, the image signal transmitting apparatus and the signal output circuit having the bandwidth boosting mechanism thereof in the present application can achieve the objectives of high bandwidth and low power consumption through the configuration of the preceding stage driving circuit.
Although the embodiments of the present application have been described above, these embodiments are not intended to limit the present application, and those skilled in the art can apply changes to the technical features of the present application according to the explicit or implicit contents of the present application, and all such changes are within the scope of the present application.
Although the present application has been described with reference to the above embodiments, it should be understood that the present application is not limited thereto, and various changes and modifications can be made by one skilled in the art without departing from the spirit and scope of the present application.
Description of reference numerals:
100 image signal transmission system
110 image signal transmission device
120 image signal receiving apparatus
130 digital signal processing circuit
140 signal output circuit
150 front stage driving circuit
160 rear stage driving circuit
C1, C2 load capacitance
C3 variable capacitor
Cs is the capacitance value of the variable capacitor
GND (ground)
I1, I2 Current Source
MN1, MN2 input transistors
O1, O2 output terminal
Vip, Vin digital input signal
Vop1, Von1 preceding stage output signal
Vop2, Von2 rear stage output signals
R1, R2 load resistance
R3 variable resistor
Rs is resistance value of variable resistor
ω P1 、ω P2 Pole (C)
ω Z Zero point
Claims (10)
1. A signal output circuit with bandwidth boosting mechanism applied in an image signal transmission device comprises:
a pre-driver circuit, comprising a continuous-time linear equalizer, configured to receive a digital input signal for high-frequency enhancement to increase the bandwidth of the digital input signal and thereby generate a pre-output signal, wherein a zero and two poles of the frequency response of the pre-driver circuit are determined by a plurality of circuit parameter values of the pre-driver circuit; and
a back stage driving circuit, configured to receive the front stage output signal for amplification, so as to generate a back stage output signal to an image signal receiving device.
2. The signal output circuit of claim 1, wherein the digital input signal, the previous stage output signal, and the next stage output signal are each a differential signal.
3. The signal output circuit according to claim 1, wherein the pre-driver circuit receives the pre-output signal from a digital signal processing circuit included in the image signal transmitting apparatus.
4. The signal output circuit of claim 1, wherein the continuous-time linear equalizer comprises:
two input transistors, each comprising:
a gate configured to receive the digital input signal;
a drain electrically coupled to an output terminal, configured to generate the preceding stage output signal to the output terminal; and
a source electrode;
two load resistors, each of which is electrically coupled between the drain of one of the two input transistors and an operating voltage source;
two load capacitors, each of which is electrically coupled between the drain of one of the two input transistors and a ground terminal;
a variable resistor and a variable capacitor electrically connected in parallel between the sources of the two input transistors; and
two current sources, each of which is electrically coupled between the source of one of the two input transistors and the ground.
5. The signal output circuit according to claim 4, wherein the circuit parameters include a resistance value of each of the two load resistors, a capacitance value of each of the two load capacitors, a resistance value of the variable resistor, and a capacitance value of the variable capacitor.
6. The signal output circuit according to claim 5, wherein the two load resistors have respective resistance values of Rd, the two load capacitors have respective capacitance values of Cd, the variable resistor has a resistance value of Rs, the variable capacitor has a capacitance value of Cs, and a transconductance of the two input transistors has a value of gm, the zero is 1/(RsCs), and the two poles are (1+ gmRs/2)/(RsCs) and 1/(RdCd), respectively.
7. The signal output circuit of claim 6, wherein a conversion function between the digital input signal and the previous stage output signal is:
(gmRd)(1+sRsCs)/((1+sRcCs+(gmRs/2))/(1+sRdCd)')。
8. the signal output circuit of claim 6, wherein a DC gain of the continuous-time linear equalizer is:
(gmRd)/(1+(gmRs/2))。
9. the signal output circuit of claim 1, wherein the post-driver circuit comprises a current-mode logic circuit.
10. An image signal transmission device applied in an image signal transmission system, comprising:
a digital signal processing circuit configured to generate a digital input signal; and
a signal output circuit, comprising:
a pre-driver circuit, comprising a continuous-time linear equalizer, configured to receive the digital input signal for high-frequency enhancement, to boost a bandwidth of the digital input signal, and to generate a pre-output signal, wherein a zero and two poles of a frequency response of the pre-driver circuit are determined by a plurality of circuit parameter values of the pre-driver circuit; and
the back stage driving circuit is configured to receive the front stage output signal and amplify the front stage output signal to generate a back stage output signal to an image signal receiving device of the image signal transmission system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110241068.9A CN115037900A (en) | 2021-03-04 | 2021-03-04 | Image signal transmission device and signal output circuit with bandwidth increasing mechanism thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110241068.9A CN115037900A (en) | 2021-03-04 | 2021-03-04 | Image signal transmission device and signal output circuit with bandwidth increasing mechanism thereof |
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| Publication Number | Publication Date |
|---|---|
| CN115037900A true CN115037900A (en) | 2022-09-09 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202110241068.9A Pending CN115037900A (en) | 2021-03-04 | 2021-03-04 | Image signal transmission device and signal output circuit with bandwidth increasing mechanism thereof |
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| CN (1) | CN115037900A (en) |
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