CN115037430A

CN115037430A - I, Q-path DAC synchronous design method

Info

Publication number: CN115037430A
Application number: CN202210137718.XA
Authority: CN
Inventors: 谷艳; 陈雷; 华璐; 刘风华; 王琰; 刘亚鹏; 行涛; 谢应辉; 王兆辉; 乐立鹏; 马城城; 方新嘉; 王伊卜
Original assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Current assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Priority date: 2022-02-15
Filing date: 2022-02-15
Publication date: 2022-09-09
Anticipated expiration: 2042-02-15
Also published as: CN115037430B

Abstract

The invention discloses a synchronous design method of I, Q-path DAC. In the design, digital baseband signals of multiple levels need to be converted into analog signals by using digital and analog converters and sent to an IQ vector modulator to form radio frequency signals for sending, and if IQ vector phases need to be guaranteed, I, Q two paths of DACs need to work synchronously, but an I path and a Q path use two independent MUXDACs, so that a mode is needed to link the two independent DACs and judge whether synchronous work is realized. The invention adopts the correlation characteristics of the output clocks of the two DACs and the data, compares the output clocks of the two DACs, judges whether the work of the DACs is synchronous or not by using the 2-time-multiplied 8-phase clock sampling of the output clocks of the DACs, and can realize the processing of high-frequency data by using lower frequency in design realization.

Description

I, Q-path DAC synchronous design method

Technical Field

The invention relates to a synchronous design method of I, Q-path DAC, which can be applied to high-speed DAC interface design of wireless, satellite and ground communication systems.

Background

In the data transmission design of a satellite communication system, digital baseband signals of multiple levels need to be converted into analog signals by using digital and analog converters and the analog signals are sent to an IQ vector modulator to form radio frequency signals for sending, and the synchronous operation of I, Q two paths of DACs is needed to be ensured if IQ vector phases need to be ensured. If the working frequency is low, the two DACs working independently can sample corresponding IQ data in the same clock period, but under the condition of high working rate, such as transmitting 1.5Gsps data, under the condition of DACMEX 4, the working frequency needs to reach 375MHz, and the synchronization problem of the IQ vector needs to be considered.

Disclosure of Invention

The technical problem solved by the invention is as follows: the method is simple and easy to realize, simultaneously adopts 8-phase clock sampling with the frequency 2 times of the output clock of the DAC to realize high-frequency sampling requirement by using the frequency of 1/8, reduces the time sequence difficulty in the circuit, simultaneously ensures the sampling precision, and adopts a feedback design method for a delay module, thereby overcoming the change trend of delay under different voltages and different temperatures while adjusting the delay.

The specific solution of the invention is as follows: an I, Q-path DAC synchronous design method comprises the following steps:

(1) setting the working modes of the two DACs which work independently to be the same, and comparing the output clocks of the two DACs;

(2) sampling a comparison result obtained in the step (1);

(3) and judging whether the DAC works synchronously according to the sampling result, if so, keeping the working state, if not, generating a reset indication signal and counting, and if not, adjusting the delay module, wherein the counting still cannot be synchronous when reaching a preset value.

I, Q two paths of DACs are required to work synchronously, and two independent MUXDACs are used for the I path and the Q path.

The output clocks of the two DACs are compared using a comparator CLKXOR 2.

The delays of the output clocks of the two independently operating DACs to the inputs of the comparators CLKXOR2 are equal, including off-chip and on-chip delays, and the shorter the delay the better to reduce the delay differences caused under different voltage, different temperature conditions.

And (3) sampling the comparison result obtained in the step (1) by adopting an 8-phase clock with the frequency 2 times of the DAC output clock in the step (2).

The 8-phase clocks include 8 phase clocks of 0 degree, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees, 315 degrees.

The 8 phase clocks are delayed equally at the time of sampling.

The step (3) is implemented by judging whether the DAC works synchronously according to the sampling result: and (3) judging whether the work of the DACs is synchronous according to the result of the step (2), switching to the same clock for judgment, judging whether the synchronous requirement is met after correct sampling, namely whether the phases of the output clocks of the two DACs are consistent, if the output clocks of the two DACs are synchronous, keeping the current state, if the output clocks of the two DACs are not synchronous, generating an indication signal, resetting the two DACs simultaneously, counting, if the output clocks of the two DACs are synchronous, adjusting a delay module, and after the delay is adjusted, repeating the step (2) and the step (3) until the synchronization is achieved.

The adjusting delay module, specifically, increases or decreases the delay, and gradually adjusts with an accuracy of less than 80 ps.

Compared with the prior art, the invention has the following beneficial effects:

according to the invention, through CLKDORX 2 comparison of two independent DAC output clocks, 8-phase clock with frequency 2 times of DAC input clock is adopted for sampling, and result judgment is carried out at low frequency to judge whether the two independent DAC output clocks are synchronous or not.

Drawings

Fig. 1 is a schematic diagram of the principle of the present invention.

FIG. 2 is a schematic flow chart.

Detailed Description

The invention relates to a synchronous design method of I, Q-path DACs, which comprises the following steps:

(2) sampling a comparison result obtained in the step (1);

I, Q two-way DACs are required to work synchronously, and two independent MUXDACs are used for the I-way and the Q-way.

The output clocks of the two DACs are compared using a comparator CLKXOR 2.

The 8-phase clocks include 8 phase clocks of 0 degree, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees, 315 degrees. The 8 phase clocks are delayed equally at the time of sampling.

And (3) judging whether the DAC works synchronously according to the sampling result, wherein the implementation mode comprises the following steps: and (3) judging whether the work of the DACs is synchronous according to the result of the step (2), switching to the same clock for judgment, judging whether the synchronous requirement is met after correct sampling, namely whether the phases of the output clocks of the two DACs are consistent, if the output clocks of the two DACs are synchronous, keeping the current state, if the output clocks of the two DACs are not synchronous, generating an indication signal, resetting the two DACs simultaneously, counting, if the output clocks of the two DACs are synchronous, adjusting a delay module, and after the delay is adjusted, repeating the step (2) and the step (3) until the synchronization is achieved.

The delay module is adjusted, specifically to increase or decrease the delay, and is adjusted in steps with an accuracy of less than 80 ps.

The invention is described in further detail below with reference to figures 1 and 2 and the specific implementation of which:

(1) the two independent DAC operation modes are set to be identical, the delay from the output clocks DA1_ CLK and DA2_ CLK of the two independent DAC to the input end of the comparator CLKOXOR 2 is equal, the delay comprises the delay inside and outside the chip, and the shorter the delay is, the better the delay is, so as to reduce the delay difference caused by different voltages and different temperatures.

(2) The comparison result of the step 1 is sampled by 8-phase clocks with the frequency 2 times that of the output clock of the DAC, the 8-phase clocks comprise 8 phase clocks of 0 degree, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees and 315 degrees, namely CLK0, CLK45, CLK90, CLK135, CLK180, CLK225, CLK270 and CLK315 in the figure, and the 8-phase clocks are required to be delayed equally in sampling in design.

(3) Judging whether the DAC works synchronously according to sampling results, namely, matched _0, matched _45, matched _90, matched _135, matched _180, matched _225, matched _270 and matched _315, switching to the same clock for judgment, judging whether the synchronous requirement is met after correct sampling, keeping the current state if the synchronous requirement is met, generating an indication signal if the synchronous requirement is not met, simultaneously resetting two DACs, counting whether the number of the DACs reaches a certain number or not is not synchronous, adjusting a delay module, increasing or decreasing the delay by the delay module, gradually adjusting with the precision smaller than 80ps, and repeating the step (2) and the step (3) until the synchronous requirement is met after the delay is adjusted.

Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make modifications and variations of the present invention without departing from the spirit and scope of the present invention.

Claims

1. An I, Q-path DAC synchronous design method is characterized by comprising the following steps:

(2) sampling a comparison result obtained in the step (1);

2. The synchronous design method for the I, Q-way DAC, according to claim 1, wherein: i, Q two-way DACs are required to work synchronously, and two independent MUXDACs are used for the I-way and the Q-way.

3. The synchronous design method of the I, Q DACs according to claim 2, wherein: the output clocks of the two DACs are compared using a comparator CLKXOR 2.

4. The synchronous design method of the I, Q-way DAC, according to claim 3, wherein: the delays of the output clocks of the two independently operating DACs to the inputs of the comparator CLKXOR2 are equal, including off-chip and on-chip delays, and the shorter the delay the better to reduce the delay differences caused under different voltage, different temperature conditions.

5. The synchronous design method for the I, Q-way DAC, according to claim 1, wherein: and (3) sampling the comparison result obtained in the step (1) by adopting an 8-phase clock with the frequency 2 times of the DAC output clock in the step (2).

6. The synchronous design method for the I, Q-way DAC, according to claim 1, wherein: the 8-phase clocks include 8 phase clocks of 0 degree, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees, 315 degrees.

7. The synchronous design method for the I, Q-way DAC, according to claim 1, wherein: the 8 phase clocks are delayed equally at the time of sampling.

8. The synchronous design method for the I, Q-way DAC, according to claim 1, wherein: the step (3) is implemented by judging whether the DAC works synchronously according to the sampling result: and (3) judging whether the work of the DACs is synchronous according to the result of the step (2), switching to the same clock for judgment, judging whether the synchronous requirement is met after correct sampling, namely whether the phases of the output clocks of the two DACs are consistent, if the output clocks of the two DACs are synchronous, keeping the current state, if the output clocks of the two DACs are not synchronous, generating an indication signal, resetting the two DACs simultaneously, counting, if the output clocks of the two DACs are synchronous, adjusting a delay module, and after the delay is adjusted, repeating the step (2) and the step (3) until the synchronization is achieved.

9. The synchronous design method for the I, Q-way DAC, according to claim 1, wherein: the adjusting delay module, specifically, increases or decreases the delay, and gradually adjusts with an accuracy of less than 80 ps.