CN115036359A - Shielding gate groove type MOSFET device and manufacturing method thereof - Google Patents

Shielding gate groove type MOSFET device and manufacturing method thereof Download PDF

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CN115036359A
CN115036359A CN202210966839.5A CN202210966839A CN115036359A CN 115036359 A CN115036359 A CN 115036359A CN 202210966839 A CN202210966839 A CN 202210966839A CN 115036359 A CN115036359 A CN 115036359A
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epitaxial layer
type
groove
polycrystalline silicon
oxide layer
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朱袁正
黄薛佺
周锦程
杨卓
叶鹏
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Wuxi NCE Power Co Ltd
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Wuxi NCE Power Co Ltd
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Abstract

The invention provides a shielded gate groove type MOSFET device and a manufacturing method thereof, wherein the shielded gate groove type MOSFET device comprises an N-type substrate, three epitaxial layers with different concentrations are arranged above the substrate, grooves are arranged in the epitaxial layers, split polycrystalline silicon gates and polycrystalline silicon field plates are arranged in the grooves, the thickness of oxide layers on two sides of the polycrystalline silicon field plates in the grooves is larger than that between the polycrystalline silicon gates and a P-type body region, P-type body regions are arranged on two sides of the grooves, and an N-type source region and a P-type source region are arranged in the P-type body region. The oxide layer thickened at the bottom of the groove can effectively reduce the electric field intensity of the internal peak value of the oxide layer, and the reliability of the device is improved; the multilayer epitaxial structure enables the electric field distribution of the voltage-resistant region to be more uniform, effectively reduces the local peak electric field intensity of the drift region and prevents the local high electric field from being broken down; the split polysilicon gate can effectively reduce the gate-source capacitance Cgs and improve the switching speed of the device.

Description

Shielding gate groove type MOSFET device and manufacturing method thereof
Technical Field
The invention belongs to the technical field of power semiconductor device structure design and manufacture, and particularly relates to a shielded gate trench type MOSFET device and a manufacturing method thereof.
Background
With the increasing demand for power management integrated circuits in the fields of aerospace, ship driving, automotive electronics, consumer electronics, smart grid, and other applications, in order to increase the integration level and efficiency of power integrated circuits and reduce the manufacturing cost, high-voltage Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), digital circuits, and analog circuits need to be integrated onto a single power chip, and meanwhile, integrated power devices must maintain a large current in an on state and can withstand a high voltage in an off state, so that characteristic on-resistance (Ron, sp) and Breakdown Voltage (BV) are two of the most important figures of merit (FOM) for power MOSFET devices. Among them, vertical double-diffused metal oxide semiconductor field effect transistor (VDMOS) is the most commonly used discrete type power semiconductor device. The voltage-resisting direction of the discrete power device is longitudinal, so that the breakdown voltage of the discrete power device is irrelevant to the size of a transverse unit cell, the size of the transverse unit cell can be greatly reduced under the same BV, and the characteristic on-resistance is greatly reduced. For the basic VDMOS, the voltage-resisting level can be improved by reducing the doping of the drift region, but at the same time, the low doping of the drift region can cause the increase of the on-resistance and the increase of the operating state loss of the device. On the basis of a VDMOS structure, the trench type (SGT) power device with the shielding gate structure further improves the breakdown voltage and reduces the specific on-resistance. In the trench type power device with the shielded gate structure, the gate is arranged in the trench, and the design can effectively reduce the peak electric field intensity in the gate oxide layer, thereby improving the gate oxide reliability and the breakdown voltage. In addition, after the polycrystalline silicon field plate below the grid is in short circuit with the source electrode, the electric field of the drift region can be modulated in an MOS depletion mode, so that the concentration of the drift region can be higher under the same withstand voltage, and the specific on-resistance is lower. On the other hand, the capacitance between the gate and the drain is reduced due to the presence of the shield gate, and therefore the shield gate device has a lower gate charge.
In order to improve breakdown voltage of an existing SGT device, a field plate and a source electrode are in short circuit, but the possibility of structure optimization still exists, for example, the problems that a local peak electric field is too large due to nonuniform electric field distribution, and a dielectric layer near the field plate is reliable under high voltage are solved, and the optimized structure of the SGT device is still to be developed.
Disclosure of Invention
The invention provides a shielded gate trench type MOSFET device and a manufacturing method thereof aiming at the problems of the device, overcomes the defect of overlarge local peak electric field of the drift region of the common shielded gate trench power semiconductor device, effectively enables the distribution of the electric field in the drift region to be more uniform, and improves the reliability of the device.
In order to realize the technical purpose, the technical scheme of the invention is as follows:
a shielded gate trench type MOSFET device comprises drain metal, an N-type substrate, an N-type drift region, a trench and a P-type body region, wherein the N-type substrate is arranged between the drain metal and the N-type drift region, the trench is arranged at one end of the N-type drift region far away from the N-type substrate, the P-type body region is arranged on the surface of the N-type drift region at two sides of the trench,
the N-type drift distinguishing three layers comprise a first epitaxial layer close to the N-type substrate, a second epitaxial layer close to the first epitaxial layer and a third epitaxial layer close to the second epitaxial layer, the second epitaxial layer is positioned between the first epitaxial layer and the third epitaxial layer,
the P-type body region is provided with a third epitaxial layer surface, a heavily doped N-type source region is arranged on the P-type body region surface, a source region contact groove and a heavily doped P-type source region are arranged on one side, far away from the groove, in the P-type body region, the source region contact groove penetrates through the N-type source region and is in contact with the heavily doped P-type source region in the P-type body region to form ohmic contact, source metal is filled in the source region contact groove, and the source metal covers the groove and the N-type source region surface;
the slot passes in third epitaxial layer and the second epitaxial layer gets into first epitaxial layer, the ditch inslot is equipped with the polycrystalline silicon grid and the polycrystalline silicon field board of split, just the polycrystalline silicon grid of split is located the top of polycrystalline silicon field board, the polycrystalline silicon grid of split with keep apart through the second oxide layer between the polycrystalline silicon field board, the polycrystalline silicon field board be equipped with first oxide layer between the inslot wall, the polycrystalline silicon grid of split with be equipped with gate oxide between the inslot wall, be equipped with the third oxide layer in the polycrystalline silicon grid of split between the adjacent polycrystalline silicon grid. The thickness of the first oxide layer is larger than that of the gate oxide layer.
The thickness range of the first oxide layer is 1000A to 8000A, and the thickness range of the gate oxide layer is 100A to 1000A.
The depth of the lower surface of the split polysilicon gate exceeds the depth of the lower surface of the P-type body region, and the depth of the upper surface of the split polysilicon gate is shallower than the depth of the lower surface of the N-type source region.
The depth of the bottom of the polysilicon field plate exceeds the depth of the lower surface of the second epitaxial layer, and the depth of the upper surface of the polysilicon field plate can be higher or lower than the depth of the lower surface of the third epitaxial layer.
The width of the lower surface of the third oxide layer is larger than that of the upper surface of the polysilicon field plate.
The resistivity of the second epitaxial layer is lower than the resistivity of the first epitaxial layer and the resistivity of the third epitaxial layer.
The resistivity range of the second epitaxial layer is 0.1 ohm-cm to 0.3 ohm-cm, and the resistivity ranges of the first epitaxial layer and the third epitaxial layer are 0.3 ohm-cm to 0.6 ohm-cm.
The thickness of the second epitaxial layer and the thickness of the third epitaxial layer are smaller than the thickness of the first epitaxial layer.
The second epitaxial layer thickness with third epitaxial layer thickness range is 0.5um to 2.5um, first epitaxial layer thickness range is 2.5um to 5 um.
And a field plate groove is arranged in the third oxidation layer, penetrates through the second oxidation layer and reaches the upper surface of the polycrystalline silicon field plate, active electrode metal is filled in the field plate groove, and the source electrode metal is connected with the polycrystalline silicon field plate.
A manufacturing method of a shielded gate trench type MOSFET device comprises the following steps:
the method comprises the following steps: selecting an N-type substrate, growing a first epitaxial layer on the N-type substrate, growing a second epitaxial layer on the first epitaxial layer, growing a third epitaxial layer on the second epitaxial layer, wherein the first epitaxial layer, the second epitaxial layer and the third epitaxial layer form an N-type drift region;
step two: selectively etching a groove on the surface of the third epitaxial layer, wherein the depth of the groove extends to the first epitaxial layer;
step three: growing a first oxide layer at the bottom of the groove, and depositing a polysilicon field plate in the groove;
step four: depositing a second oxide layer in the groove, wherein the second oxide layer isolates the polysilicon field plate;
step five: growing an oxide layer on the inner wall of the groove by using a high-temperature oxidation method to form a gate oxide layer, depositing polycrystalline silicon on the surface of the third epitaxial layer, selectively etching off the polycrystalline silicon grid in the middle of the groove, and depositing a third oxide layer to form a split polycrystalline silicon grid;
step six: injecting P-type ions into the surfaces of the third epitaxial layers on the two sides of the groove to form a P-type body region;
step seven: injecting N-type ions into the surface of the P-type body region to form a heavily doped N-type source region;
step eight: etching the P-type body region on one side of the surface of the P-type body region, which is far away from the groove, to form a source region contact groove, and injecting P-type ions into the bottom of the source region contact groove to form a heavily doped P-type source region;
step nine: and filling metal into the source region contact groove to the surface of the third epitaxial layer, forming ohmic contact between the metal and the heavily doped P-type source region, selectively etching the metal to form source metal, and depositing drain metal below the N-type substrate.
Compared with the prior device structure and manufacturing technology, the invention has the following advantages:
1. use multilayer epitaxial layer as device drift region, through the doping concentration who increases the second epitaxial layer, effectively reduce the intraformational electric field intensity of third epitaxial layer and improve the intraformational electric field intensity of second epitaxial simultaneously for whole drift region electric field distribution is more even, and electric field distribution curve is more gentle, simultaneously, reduces drift region local peak value electric field intensity, avoids local breakdown and then improves the device reliability.
2. The oxide layer around the field plate at the bottom of the dielectric groove is thickened by wet oxidation, and when the field plate and the drift region are loaded with high voltage, the thickened oxide layer can effectively reduce the electric field intensity therein, so that the oxide layer is prevented from being broken down in advance, and the breakdown strength and the overall reliability of the device are improved.
3. The concentration of the second epitaxial layer is higher than that of the first epitaxial layer and the third epitaxial layer, so that when the device faces high drain-source voltage, the depletion of the second epitaxial layer is relatively slow, the change of the capacitance of a depletion layer is relatively slow, finally, the change rate of the gate-drain capacitance Cgd and the drain-source capacitance Cds of the device caused by the change of the drain voltage is relatively slow, and the noise generated by the nonlinear capacitance is reduced.
4. The split gate structure is used, the polysilicon gate is divided into a left part and a right part, oxide is deposited for isolation, the area of the grid opposite to the bottom drain electrode is reduced, the polysilicon field plate is usually connected with source electrode metal, the grid-source capacitance Cgs between the grid electrode and the source electrode is further reduced, the switching speed of the device is effectively improved, and the device is faster to switch under the high-frequency working condition, lower in energy consumption and better in performance.
Drawings
Fig. 1 is a cross-sectional structural view of a conventional shielded gate trench MOSFET device.
Fig. 2 is a sectional structural view of embodiment 1 of the present invention.
Fig. 3 is a sectional structural view of embodiment 2 of the present invention.
Description of the reference numerals: 1-N type substrate; 2-a first epitaxial layer; 3-a first oxide layer; 4, forming a groove; 5-a polysilicon field plate; 6-polysilicon grid; 7-N-type source region; 8-P-type body region; 9-P-type source region; 10-source region contact trench; 11-source metal; 12-a drain metal; 13-gate oxide layer; 14 — a second epitaxial layer; 15-a third epitaxial layer; 16-a second oxide layer; 17-a third oxide layer; 18-field plate trench.
Detailed Description
In order that the above objects, features and advantages of the present invention can be more clearly understood, a more particular description of the invention will be rendered by reference to the appended drawings. It should be noted that the embodiments and features of the embodiments of the present application may be combined with each other without conflict.
It should be noted that "up", "down", "left" and "right" mentioned in this embodiment are positional relationships when the high breakdown voltage trench power device structure is in the illustrated state, "long" is a lateral dimension when the high breakdown voltage trench power device structure is in the illustrated state, and "deep" is a longitudinal dimension when the high breakdown voltage trench power device structure is in the illustrated state.
It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Example 1
The present embodiment provides a shielded gate trench MOSFET device, referring to fig. 2, including a drain metal 12, an N-type substrate 1 over the drain metal 12, an N-type drift region, a trench 4 over the N-type drift region, and P-type body regions 8 on both sides of the trench.
The N type drift distinguishes three layers, a first epitaxial layer 2 is arranged at the lowest part, a second epitaxial layer 14 is arranged above the first epitaxial layer 2, and a third epitaxial layer 15 is arranged above the second epitaxial layer 14.
The P-type body region 8 is arranged on the surface of the third epitaxial layer 15, and the surface of the P-type body region 8 is provided with a heavily doped N-type source region 7; a source region contact groove 10 and a heavily doped P-type source region 9 are arranged on one side, far away from the groove 4, in the P-type body region 8, and the source region contact groove 10 penetrates through the N-type source region 7 and is in contact with the heavily doped P-type source region 9 in the P-type body region 8 to form ohmic contact; the source region contact groove is filled with source metal 11; the source metal 11 covers the surface of the trench 4 and the surface of the N-type source region 7.
The groove 4 penetrates through the third epitaxial layer 15 and the second epitaxial layer 14 to enter the first epitaxial layer 2, a split polysilicon gate 6 and a polysilicon field plate 5 are arranged in the groove 4, and the split polysilicon gate 6 is positioned above the polysilicon field plate 5. A gate oxide layer 13 is arranged between the split polycrystalline silicon grid electrode 6 and the P-shaped body region 8, a first oxide layer 3 is arranged between the polycrystalline silicon field plate 5 and the outer wall of the groove 4, a second oxide layer 16 is arranged between the split polycrystalline silicon grid electrode 6 and the polycrystalline silicon field plate 5, and a third oxide layer 17 is arranged between adjacent polycrystalline silicon grid electrodes 6 in the split polycrystalline silicon grid electrode.
The width of the lower half part of the trench 4 is wider than that of the upper half part of the trench 4, specifically, the width of the trench 4 in the third epitaxial layer 15 is smaller than that of the trench 4 in the second epitaxial layer 14 and the first epitaxial layer 2, and the width of the first oxide layer 3 can be increased by the larger width of the lower half part, so that the breakdown of the first oxide layer 3 is effectively avoided.
The depth of the lower surface of the split polysilicon gate 6 exceeds the depth of the lower surface of the P-type body region 8, and the depth of the upper surface of the split polysilicon gate 6 is shallower than the depth of the lower surface of the N-type source region 7. The split polysilicon gate 6 arranged at the position can invert the P-type body region 8 adjacent to the gate oxide layer 13 into an electronic channel when the device is conducted, so that the normal conduction of the device is ensured.
The depth of the bottom of the polysilicon field plate 5 exceeds the depth of the lower surface of the second epitaxial layer 14, the depth of the upper surface of the polysilicon field plate 5 can be higher or lower than the depth of the lower surface of the third epitaxial layer 15, and the depth of the upper surface of the polysilicon field plate 5 is lower than the depth of the lower surface of the split polysilicon gate 6. The polysilicon field plate arranged at the position can effectively deplete the second epitaxial layer 14 with higher concentration. In addition, because the concentration of the first epitaxial layer 2 is lower than that of the second epitaxial layer 14, the electric field at the position of the first epitaxial layer 2 is lower, and the depth of the bottom of the polysilicon field plate 5 reaches the first epitaxial layer, so that the reliability of the first oxide layer 3 between the bottom of the polysilicon field plate 5 and the bottom of the trench 4 can be effectively improved.
The width of the lower surface of the third oxide layer 17 is larger than that of the upper surface of the polysilicon field plate 5, and the arrangement mode reduces the facing area of the polysilicon gate 6 and the polysilicon field plate 5, so that the gate-source capacitance Cgs of the MOSFET device is reduced.
The thickness of the first oxide layer 3 is larger than that of the gate oxide layer 13. Preferably, the first oxide layer 3 has a thickness range of 1000A to 8000A and the gate oxide layer 13 has a thickness range of 100A to 1000A. In an embodiment, the first oxide layer 3 is selected to have a thickness of 2000 a and the gate oxide layer 13 has a thickness of 200 a.
The resistivity of the second epitaxial layer 14 is lower than the resistivity of the first epitaxial layer 2 and the resistivity of the third epitaxial layer 15. Preferably, the resistivity of the second epitaxial layer 14 ranges from 0.1 Ω · cm to 0.3 Ω · cm, and the resistivity of the first epitaxial layer 2 and the third epitaxial layer 15 ranges from 0.3 Ω · cm to 0.6 Ω · cm. In the embodiment, the resistivity of the second epitaxial layer 14 is 0.2 Ω · cm, and the resistivity of the first epitaxial layer 2 and the third epitaxial layer 15 is 0.4 Ω · cm.
The thickness of the second epitaxial layer 14 and the thickness of the third epitaxial layer 15 are less than the thickness of the first epitaxial layer 2. Preferably, the thickness of the second epitaxial layer 14 and the thickness range of the third epitaxial layer 15 are 0.5um to 2.5um, and the thickness range of the first epitaxial layer 2 is 2.5um to 5 um. In an embodiment, the thickness of the first epitaxial layer 2 is 4um, the thickness of the second epitaxial layer 14 is 1um, and the thickness of the third epitaxial layer 15 is 1.5 um.
As shown in fig. 1, which is a cross-sectional structure view of a conventional shielded gate trench MOSFET device, an N-type substrate 1 is arranged on a drain metal 12, an N-type epitaxial layer 2 is arranged on the N-type substrate 1, a trench 4 is arranged in the N-type epitaxial layer 2, a polysilicon gate 6 and a polysilicon field plate 5 wrapped by a first oxide layer 3 are arranged in the trench 4, P-type body regions 8 are arranged at two sides of the trench 4, a heavily doped N-type source region 7 is further arranged on the surface of the P-type body region 8, a source region contact trench 10 is further arranged on the surface of the P-type body region 8, source metal 11 is filled in the source region contact trench 10, a heavily doped P-type source region 9 is further arranged at the bottom of the source region trench, and the source metal 11 covers the N-type source region 7 and the surface of the trench 4. For a conventional shielded gate trench MOSFET device, when the device is turned off, a high voltage is applied to the drain, and the P-type body region 8 and the N-type epitaxial layer 2 are depleted. Meanwhile, the polysilicon field plate 5 can also generate an auxiliary depletion effect on the N-type epitaxial layer 2. Thus, the location of the high electric field will typically occur at the intersection of the N-type epitaxial layer 2 and the P-type body region 8 and at the intersection of the first oxide layer 3 and the N-type epitaxial layer 2 outside the polysilicon field plate 5, in particular when the oxide layer is thin, typically having a first oxide layer thickness of about 200 a for a 40V shielded gate trench MOSFET device, where the electric field in the thin oxide layer is high and the oxide layer is very prone to breakdown, causing device failure.
For the structure of this embodiment, the N-type drift region is provided with three epitaxial layers, i.e., the first epitaxial layer 2, the second epitaxial layer 14 and the third epitaxial layer 15, wherein the doping concentration of the second epitaxial layer 14 is relatively high, and the doping concentrations of the first epitaxial layer 2 and the third epitaxial layer 15 are relatively low, so that when the drain of the device is in an off state and a high voltage is applied to the drain of the device, a high electric field is not generated when the P-type body region 8 and the third epitaxial layer 15 with relatively low concentration are depleted. The polysilicon field plate 5 has an auxiliary depletion effect on the second epitaxial layer 14 with higher doping concentration, the electric field intensity in the second epitaxial layer 14 is improved, finally, the electric field intensity distribution in the drift region is more even, and the breakdown voltage of the device is also improved. In addition, when the device faces higher breakdown voltage, the voltage at the position of the second epitaxial layer 14 is also higher, and the first oxide layer 3 around the polysilicon field plate 5 is thickened, so that the increase of the electric field intensity in the oxide layer can be avoided, and the breakdown of the first oxide layer 3 is effectively prevented. The polysilicon grid 6 adopts a split gate structure, and the polysilicon field plate 5 is connected with the source metal 11, so that the direct contact area between the grid and the source is greatly reduced, the grid-source capacitance between the grid and the source is effectively reduced, the breakdown voltage and the reliability of the shielded grid groove power device can be improved by the measures, and the use performance of the device under a high-frequency condition is optimized.
The manufacturing method of the shielded gate trench type MOSFET device provided by the embodiment includes the following steps:
the method comprises the following steps: selecting an N-type substrate 1, growing a first epitaxial layer 2 on the N-type substrate, growing a second epitaxial layer 14 on the first epitaxial layer 2, growing a third epitaxial layer 15 on the second epitaxial layer 14, wherein the first epitaxial layer 2, the second epitaxial layer 14 and the third epitaxial layer 15 form an N-type drift region;
step two: selectively etching a groove 4 on the surface of the third epitaxial layer 15, wherein the depth of the groove extends to the first epitaxial layer 2;
step three: growing a first oxide layer 3 at the bottom of the trench 4, and depositing a polysilicon field plate 5 in the trench 4;
step four: depositing a second oxide layer 16 in the trench 4, wherein the second oxide layer 16 isolates the polysilicon field plate 5;
step five: growing an oxide layer on the inner wall of the trench 4 by using a high-temperature oxidation method to form a gate oxide layer 13, depositing polycrystalline silicon on the surface of a third epitaxial layer 15, selectively etching off the polycrystalline silicon gate 6 in the middle of the trench 4, and depositing a third oxide layer 17 to form a split polycrystalline silicon gate 6;
step six: injecting P-type ions into the surface of the third epitaxial layer 15 on two sides of the trench 4 to form a P-type body region 8;
step seven: injecting N-type ions into the surface of the P-type body region 8 to form a heavily doped N-type source region 7;
step eight: etching a P-type body region 8 on one side of the surface of the P-type body region 8, which is far away from the groove 4, to form a source region contact groove 10, and injecting P-type ions into the bottom of the source region contact groove 10 to form a heavily doped P-type source region 9;
step nine: and filling metal into the source region contact groove 10 to the surface of the third epitaxial layer 15, wherein the metal and the heavily doped P-type source region 9 form ohmic contact, selectively etching the metal to respectively form source metal 11, and depositing drain metal 12 below the N-type substrate.
Example 2
The present embodiment provides a shielded gate trench MOSFET device, referring to fig. 3, including a drain metal 12, an N-type substrate 1 over the drain metal 12, an N-type drift region, a trench 4 over the N-type drift region, and P-type body regions 8 on both sides of the trench.
The N type drift distinguishes three layers, a first epitaxial layer 2 is arranged at the lowest part, a second epitaxial layer 14 is arranged above the first epitaxial layer 2, and a third epitaxial layer 15 is arranged above the second epitaxial layer 14.
The surface of the P-type body region 8 is provided with a heavily doped N-type source region 7; a source region contact groove 10 is formed in one side, far away from the groove 4, of the P-type body region 8, and the source region contact groove 10 penetrates through the N-type source region 7 and is in contact with a heavily doped P-type source region 9 in the P-type body region 8 to form ohmic contact; the source region contact groove is filled with source metal 11; the source metal 11 covers the surface of the trench 4 and the surface of the N-type source region 7.
A split polysilicon gate 6 and a polysilicon field plate 5 are arranged in the trench 4, and the split polysilicon gate 6 is positioned above the polysilicon field plate 5. A gate oxide layer 13 is arranged between the split polycrystalline silicon grid 6 and the P-type body region 8, a first oxide layer 3 is arranged between the polycrystalline silicon field plate 5 and the outer wall of the groove 4, a second oxide layer 16 is arranged between the polycrystalline silicon grid 6 and the polycrystalline silicon field plate 5, a third oxide layer 17 is arranged between the adjacent polycrystalline silicon grid 6 in the split polycrystalline silicon grid, a field plate groove 18 is arranged in the third oxide layer 17, the field plate groove 18 penetrates through the second oxide layer 16 to reach the upper surface of the polycrystalline silicon field plate 5, an active electrode metal 11 is filled in the field plate groove 18, and the source electrode metal 11 is connected with the polycrystalline silicon field plate 5.
The lower half of the groove 4 is wider than the upper half of the groove 4. The depth of the lower surface of the split polysilicon gate 6 exceeds the depth of the lower surface of the P-type body region 8, and the depth of the upper surface of the split polysilicon gate 6 is shallower than the depth of the lower surface of the N-type source region 7. The depth of the bottom of the polysilicon field plate 5 exceeds the depth of the lower surface of the second epitaxial layer 14, and the depth of the upper surface of the polysilicon field plate 5 can be higher or lower than the depth of the lower surface of the third epitaxial layer 15. The width of the lower surface of the third oxide layer 17 is larger than that of the upper surface of the polysilicon field plate 5.
In this embodiment the first oxide layer 3 has a thickness of 2000 a and the gate oxide layer 13 has a thickness of 200 a. The resistivity of the second epitaxial layer 14 is 0.15 Ω · cm, and the resistivity of the first epitaxial layer 2 and the third epitaxial layer 15 is 0.3 Ω · cm. The second epitaxial layer 14 thickness with third epitaxial layer 15 thickness is 1.5um, 2 thicknesses of first epitaxial layer are 3 um.
The embodiment can avoid the situation that the polysilicon field plate 5 is led out separately in the peripheral area of the MOSFET chip and then connected to the source metal 11, thereby reducing the area of the peripheral lead wire area of the MOSFET chip, reducing the complexity of device design and saving the production cost of the chip.
The difference between the manufacturing method of the shielded gate trench MOSFET device provided in this embodiment and embodiment 1 is that:
step eight: etching a P-type body region 8 on one side of the surface of the P-type body region 8, which is far away from the groove 4, to form a source region contact groove 10, etching an oxide layer on the surface of the third oxide layer 17 to form a field plate groove 18, and injecting P-type ions into the bottom of the source region contact groove 10 to form a heavily doped P-type source region 9;
step nine: and filling metal into the source region contact groove 10 and the field plate groove 18 to the surface of the third epitaxial layer 15, wherein the metal and the heavily doped P-type source region 9 form ohmic contact, the metal and the polysilicon field plate 5 form ohmic contact, selectively etching the metal to respectively form source metal 11, and depositing drain metal 12 below the N-type substrate.
The foregoing is a further detailed description of the invention in connection with specific preferred embodiments and it is not intended to limit the invention to the specific embodiments described. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (13)

1. The utility model provides a shielded gate trench type MOSFET device, includes drain metal, N type substrate, N type drift region, slot and P type somatic region, N type substrate sets up between drain metal and N type drift region, the slot sets up the one end of keeping away from N type substrate in N type drift region, the N type drift region surface of P type somatic region setting in the slot both sides, its characterized in that:
the N-type drift distinguishing three layers comprise a first epitaxial layer close to the N-type substrate, a second epitaxial layer close to the first epitaxial layer and a third epitaxial layer close to the second epitaxial layer, wherein the second epitaxial layer is positioned between the first epitaxial layer and the third epitaxial layer;
the P-type body region is provided with a third epitaxial layer surface, a heavily doped N-type source region is arranged on the P-type body region surface, a source region contact groove and a heavily doped P-type source region are arranged on one side, far away from the groove, in the P-type body region, the source region contact groove penetrates through the N-type source region and is in contact with the heavily doped P-type source region in the P-type body region to form ohmic contact, source metal is filled in the source region contact groove, and the source metal covers the groove and the N-type source region surface;
the slot passes in third epitaxial layer and the second epitaxial layer gets into first epitaxial layer, the ditch inslot is equipped with the polycrystalline silicon grid and the polycrystalline silicon field board of split, just the polycrystalline silicon grid of split is located the top of polycrystalline silicon field board, the polycrystalline silicon grid of split with keep apart through the second oxide layer between the polycrystalline silicon field board, the polycrystalline silicon field board be equipped with first oxide layer between the inslot wall, the polycrystalline silicon grid of split with be equipped with gate oxide between the inslot wall, be equipped with the third oxide layer in the polycrystalline silicon grid of split between the adjacent polycrystalline silicon grid.
2. The shielded gate trench MOSFET of claim 1 wherein said first oxide layer has a thickness greater than a thickness of said gate oxide layer.
3. A shielded gate trench type MOSFET device according to claim 2, characterized in that the first oxide layer has a thickness ranging from 1000 a to 8000 a and the gate oxide layer has a thickness ranging from 100 a to 1000 a.
4. The shielded gate trench MOSFET of claim 1 wherein the width of the trench in the third epitaxial layer is less than the width of the trench in the second epitaxial layer and the first epitaxial layer.
5. The shielded gate trench MOSFET of claim 1 wherein said split polysilicon gates have a lower surface depth that exceeds a depth of said lower P-type body regions and an upper surface depth that is shallower than a depth of said lower N-type source regions.
6. The shielded gate trench MOSFET of claim 1 wherein the depth of the bottom of the polysilicon field plate exceeds the depth of the lower surface of the second epitaxial layer and the depth of the upper surface of the polysilicon field plate can be higher or lower than the depth of the lower surface of the third epitaxial layer.
7. The shielded gate trench MOSFET of claim 1 wherein the width of the lower surface of said third oxide layer is greater than the width of the upper surface of said polysilicon field plate.
8. The shielded gate trench MOSFET of claim 1 wherein the resistivity of said second epitaxial layer is lower than the resistivity of said first epitaxial layer and the resistivity of said third epitaxial layer.
9. The shielded gate trench MOSFET of claim 7 wherein said second epitaxial layer has a resistivity in the range of 0.1 Ω -cm to 0.3 Ω -cm and said first and third epitaxial layers have a resistivity in the range of 0.3 Ω -cm to 0.6 Ω -cm.
10. The shielded gate trench MOSFET device of claim 1 wherein said second epitaxial layer thickness and said third epitaxial layer thickness are less than said first epitaxial layer thickness.
11. The shielded gate trench MOSFET of claim 10 wherein the second and third epitaxial layer thicknesses range from 0.5um to 2.5um and the first epitaxial layer thickness range from 2.5um to 5 um.
12. The shielded gate trench MOSFET of claim 1 wherein a field plate trench is formed in the third oxide layer, the field plate trench extends through the second oxide layer to reach the upper surface of the polysilicon field plate, and the field plate trench is filled with active metal and connected to the polysilicon field plate.
13. The method of claim 1, further comprising the steps of:
the method comprises the following steps: selecting an N-type substrate, growing a first epitaxial layer on the N-type substrate, growing a second epitaxial layer on the first epitaxial layer, growing a third epitaxial layer on the second epitaxial layer, wherein the first epitaxial layer, the second epitaxial layer and the third epitaxial layer form an N-type drift region;
step two: selectively etching a groove on the surface of the third epitaxial layer, wherein the depth of the groove extends to the first epitaxial layer;
step three: growing a first oxide layer at the bottom of the groove, and depositing a polysilicon field plate in the groove;
step four: depositing a second oxide layer in the groove, wherein the second oxide layer isolates the polysilicon field plate;
step five: growing an oxide layer on the inner wall of the groove by using a high-temperature oxidation method to form a gate oxide layer, depositing polycrystalline silicon on the surface of the third epitaxial layer, selectively etching off the polycrystalline silicon grid in the middle of the groove, and depositing a third oxide layer to form a split polycrystalline silicon grid;
step six: injecting P-type ions into the surfaces of the third epitaxial layers on the two sides of the groove to form a P-type body region;
step seven: injecting N-type ions into the surface of the P-type body region to form a heavily doped N-type source region;
step eight: etching the P-type body region on one side of the surface of the P-type body region, which is far away from the groove, to form a source region contact groove, and injecting P-type ions into the bottom of the source region contact groove to form a heavily doped P-type source region;
step nine: and filling metal into the source region contact groove to the surface of the third epitaxial layer, forming ohmic contact between the metal and the heavily doped P-type source region, selectively etching the metal to form source metal, and depositing drain metal below the N-type substrate.
CN202210966839.5A 2022-08-12 2022-08-12 Shielding gate groove type MOSFET device and manufacturing method thereof Pending CN115036359A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103545368A (en) * 2012-07-13 2014-01-29 力祥半导体股份有限公司 Trench gate MOSFET
CN106057674A (en) * 2016-05-31 2016-10-26 上海华虹宏力半导体制造有限公司 Shield grid groove MSOFET manufacturing method
CN107546257A (en) * 2017-08-23 2018-01-05 恒泰柯半导体（上海）有限公司 The epitaxial layer structure of metal oxide channel semiconductor field-effect transistor
CN113823567A (en) * 2021-11-23 2021-12-21 南京华瑞微集成电路有限公司 Split-gate trench MOS (metal oxide semiconductor) with optimized electric field characteristic and manufacturing method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103545368A (en) * 2012-07-13 2014-01-29 力祥半导体股份有限公司 Trench gate MOSFET
CN106057674A (en) * 2016-05-31 2016-10-26 上海华虹宏力半导体制造有限公司 Shield grid groove MSOFET manufacturing method
CN107546257A (en) * 2017-08-23 2018-01-05 恒泰柯半导体（上海）有限公司 The epitaxial layer structure of metal oxide channel semiconductor field-effect transistor
CN113823567A (en) * 2021-11-23 2021-12-21 南京华瑞微集成电路有限公司 Split-gate trench MOS (metal oxide semiconductor) with optimized electric field characteristic and manufacturing method thereof

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