CN115033181A - Bus-based data elastic buffer system and data transmission method - Google Patents
Bus-based data elastic buffer system and data transmission method Download PDFInfo
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- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
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- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
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Abstract
The invention discloses a data elastic buffer system based on a bus and a data transmission method, wherein the system comprises: an apb bus; the apb configuration register module; a data buffer structure; i2s control module; an i2s bus; the data buffer structure is respectively connected with the apb configuration register module and the i2s control module in a communication mode, wherein the apb configuration register module is connected with the apb bus, the i2s control module is connected with the i2s bus, the apb configuration register module and the i2s control module establish communication connection with the data buffer structure by adopting a handshake protocol, and read-write operation is executed in the data buffer structure through the handshake protocol. The system and the method can ensure the continuity of the Gray coded pointer when synchronizing to the opposite clock domain by adopting a handshake protocol in the elastic buffer structure to ensure that the i2s bus reads data from the elastic buffer structure for enough time.
Description
Technical Field
The invention relates to the technical field of bus structures and data transmission, in particular to a data elastic buffer system and a data transmission method based on a bus.
Background
In the existing data elastic buffer structure, most of asynchronous fifo is used for pointer synchronization by using gray codes, and the bit width of a pointer is expanded by one bit to assist in judging whether fifo is empty or full. However, the above prior art has the following technical problems: 1. in the process of converting the binary pointer into the gray code and synchronizing the gray code to the clock domain of the opposite side, missing sampling can occur when the slow clock domain samples the fast clock domain, so that the empty and full signals are more conservative to reduce the efficiency; 2. due to the occurrence of missing sampling, the pointer of the fast clock domain is synchronized to the slow clock domain, so that the pointer change of the gray code passing the past is not continuous, but the change of the gray code of several bits occurs at one time.
Disclosure of Invention
One of the objectives of the present invention is to provide a bus-based data elastic buffer system and a data transmission method, which can ensure the continuity of gray coded pointers when synchronizing to the clock domain of the other party by using a handshake protocol in an elastic buffer structure to enable an i2s bus to read data from the elastic buffer structure for a sufficient time.
Another object of the present invention is to provide a bus-based data elastic buffer system and a data transmission method, which perform synchronization of read and write pointers through the handshake protocol, so as to reduce missing sampling of a slow clock domain and a fast clock domain, thereby improving efficiency of determining an empty/full signal.
Another object of the present invention is to provide a bus-based data elastic buffer system and a data transmission method, which can fully ensure the continuity and accuracy of data change and make more accurate judgment of fast empty and fast full due to the reduction of missing sampling.
To achieve at least one of the above objects, the present invention further provides a bus-based data elastic buffering system, comprising:
an apb bus;
the apb configuration register module;
a data buffer structure;
i2s control module;
an i2s bus;
the data buffer structure is respectively connected with the apb configuration registering module and the i2s control module in a communication mode, wherein the apb configuration registering module is connected with the apb bus, the i2s control module is connected with the i2s bus, the apb configuration registering module and the i2s control module adopt a handshake protocol to establish a communication connection with the data buffer structure, and read-write operation is executed in the data buffer structure through the handshake protocol.
According to a preferred embodiment of the present invention, the data buffer structure comprises a data storage unit and a data synchronization unit, wherein the data storage unit is connected to the data synchronization unit.
According to another preferred embodiment of the present invention, the data buffer structure further comprises a write control unit and a read control unit, the write control unit and the read control unit are respectively connected to the data storage unit and the data synchronization unit in a communication manner, and the write control unit and the read control unit execute a synchronization operation of writing data and reading data by using a handshake protocol.
To achieve at least one of the above objects, the present invention further provides a bus-based data transmission method, comprising:
acquiring state data in a data buffer structure, and judging whether the state data is valid data or not according to the state data;
generating effective read or write enable according to the effective data;
converting the effective read-write enable pointer into Gray codes, and synchronizing the effective read-write enable from the current clock domain to the target clock domain according to the Gray codes;
after synchronizing to a target clock domain, synchronizing the effective read or write enable to a current clock domain to execute data buffer structure state updating;
and judging whether valid data exists to execute the next read or write synchronous operation according to the updated data buffer structure.
According to a preferred embodiment of the present invention, the status data of the data buffer structure comprises empty, full, fast empty, fast full, read empty and read full status, and the status data constitutes an interrupt of data transmission in the buffer structure.
According to another preferred embodiment of the present invention, the data transmission method includes a data writing method: the apb configuration register module and the i2s control module input data and write enable corresponding to the bus into the data buffer structure, if the data buffer structure detects external write data and judges that the state in the current data buffer structure is full interrupt, the currently detected external write data is invalid data, and the correspondingly input write enable is invalid enable.
According to another preferred embodiment of the present invention, during data writing, the apb configuration register module and the i2s control module input data and write enable of a corresponding bus into the data buffer structure, when the data buffer structure detects external write data, if the current buffer structure is determined to be in a non-full state, the write enable data is valid write enable, the corresponding external write data is valid data, and the write enable is synchronized into the read clock domain and is synchronized into the current write clock domain through the handshake protocol.
According to another preferred embodiment of the present invention, the data transmission method includes a readout method: the apb configuration register module or the i2s control module inputs data and read enable of a corresponding bus into the data buffer structure, and if the data buffer structure detects external read data, if the current state in the data buffer structure is determined to be an air break, the currently detected external read data is regarded as invalid data, and the currently detected read enable is regarded as invalid enable.
According to another preferred embodiment of the present invention, the data transmission method includes a readout method: the apb configuration register module or the i2s control module inputs data corresponding to the bus and self read enable into the data buffer structure, if the data buffer structure detects external read data, if the state in the current data buffer structure is judged to be non-air break, the currently detected external read data is taken as effective data, the currently detected read enable is taken as effective enable, and the corresponding external read enable is synchronized into the write clock domain and the current read clock domain through the handshake protocol.
According to another preferred embodiment of the present invention, when synchronizing the valid read enable or write enable to the corresponding clock domain, the corresponding write pointer gray code or read pointer gray code is converted into binary data, the read pointer binary data is subtracted from the converted write pointer binary data, and the state data in the data buffer structure is regenerated according to the subtraction result and synchronized to the corresponding clock domain.
The invention further provides a computer-readable storage medium, which stores a computer program that can be executed by a processor to perform a data transmission method as described above.
Drawings
FIG. 1 is a schematic diagram of a bus-based data elastic buffer system according to the present invention.
Fig. 2 is a schematic diagram of a bus-based data transmission method according to the present invention.
FIG. 3 is a flow chart showing a write mode according to the present invention.
FIG. 4 is a flow chart showing a read mode according to the present invention.
Detailed Description
The following description is presented to disclose the invention so as to enable any person skilled in the art to practice the invention. The preferred embodiments in the following description are given by way of example only, and other obvious variations will occur to those skilled in the art. The underlying principles of the invention, as defined in the following description, may be applied to other embodiments, variations, modifications, equivalents, and other technical solutions without departing from the spirit and scope of the invention.
It is understood that the terms "a" and "an" should be interpreted as meaning that a number of one element or element is one in one embodiment, while a number of other elements is one in another embodiment, and the terms "a" and "an" should not be interpreted as limiting the number.
Referring to fig. 1-4, the present invention discloses various bus-based data elastic buffer system structures and data transmission methods, wherein the data elastic buffer system comprises: the invention writes data into or reads data from the data buffer structure through the above-mentioned apb configuration register module and i2s control module, wherein the apb configuration register module and i2s control module are in communication connection with the buffer structure through a handshake protocol. The buffer module comprises a data storage unit (stram) and a data synchronization unit, wherein the data storage unit is used for storing and reading valid data, and the data storage unit is connected with the data synchronization unit and used for synchronizing data reading and writing.
It should be noted that the data buffer structure further includes a data write control unit and a read control unit, where the write control unit and the read control unit acquire state data in the data buffer structure, further generate valid data and invalid data according to the state data in the data buffer structure, and further execute data transmission operations in different clock domains according to the valid data.
Specifically, the clock domain includes a read clock domain and a write clock domain, where the read clock domain has the read control unit therein, the write clock domain includes the write control unit therein, the apb configuration register module is respectively connected to the write control unit and the read control unit, and can obtain corresponding data from an apb bus through the apb configuration register module, write the data into the data buffer structure through the apb configuration register module, determine state data of the current data buffer structure through the read control unit and the write control unit in the data buffer structure, and further perform operations such as data writing, reading, and transmission after determining validity of the parent data and the enable according to the state data. Similarly, the i2s control module may input data in the i2s bus into a corresponding data buffer structure, and read the data in the data buffer structure, and a read control unit and a write control unit in the data buffer structure obtain status data of the data buffer structure, and perform operations such as writing, reading, and transmitting of the data and the enable after judging validity of current data and the enable according to the status data.
The invention respectively executes the read-write operation of data through the read clock domain and the write clock domain in the data buffer structure. The state of the data buffer structure comprises 6 state signals of empty, full, fast empty, fast full, read empty, read full and the like, each state signal realizes an interrupt, wherein the 6 state signals are directly judged according to the filling degree of a data queue in the data buffer structure, an empty signal is the condition that the data queue in the data buffer structure has no data signal, a full signal is the signal that the data queue in the data buffer structure is full, a fast empty signal is a threshold value according to a preset queuing sequence, and if the sorting value of the data queue in the current buffer data structure is smaller than the preset fast empty signal threshold value, the corresponding fast empty signal interrupt is output through the preset fast empty signal threshold value. Similarly, a fast full signal threshold is set, and if the data queue ordering value in the current buffer data structure is greater than the fast full signal threshold, a fast full signal interrupt is output according to the fast full signal threshold. In a read mode, a read empty signal interrupt is further output according to a data queue ordering value in a current buffer data structure, wherein the method for generating the read empty interrupt comprises the following steps: and if no data exists in the data queue in the current buffer data structure, outputting a read-empty interrupt signal. And if the data queue in the current buffer data structure is filled with data, outputting a read full interrupt signal.
It is worth mentioning that the present invention utilizes a handshake protocol to implement different data transmission and synchronization operations under the condition of different status data of the data queue sorting values in the buffering data structure. In one preferred embodiment of the present invention, the apb configuration register module is in a write mode, the apb bus writes data and a write enable into the data buffer structure through the apb configuration register module, and the i2s control module generates a read enable, the read enable is transmitted into the data buffer structure. When the apb configuration register module is in a read mode, the i2s control module generates data and write enable, writes the generated data and write enable into the data buffer structure, and reads corresponding data by the read enable generated by the apb configuration register module.
Referring to the flow chart in the write mode shown in fig. 3, the apb configuration register module or i2s control module determines that there is an external data write operation corresponding to the bus, acquires data corresponding to the bus, and generates a corresponding write enable, the apb configuration register module or i2s control module determines status data in the current data buffer structure, if the status data in the current data buffer structure is in a full interrupt state, the currently acquired data is further invalid data, and the currently generated write enable is invalid enable, at which time the data of the external bus cannot be written into the data buffer structure. If the corresponding apb configuration register module or i2s control module judges that the data in the current data buffer structure is not in a full interrupt state, and may be an interrupt signal such as empty, fast empty, read empty, etc., the corresponding apb configuration register module or i2s control module takes the data written on the bus as valid data, and transmits the write enable generated by itself as a valid enable generation request to the read clock domain, and stores the valid data written on the bus into a data storage unit (scram), and simultaneously converts a write pointer into gray codes according to the valid write enable data in a way of handshake protocol and then synchronizes to the read clock domain, wherein the write pointer is converted into the gray codes and then executes synchronization operation in a form of two-stage triggers. After the synchronous operation of the write pointer is completed, the write pointer converted into gray code is further converted into binary data, the binary data of the write pointer minus the binary data of the corresponding current read pointer is used as a basis for finally judging the state in the data buffer structure, wherein the value of a sorting queue of the corresponding data in the data buffer structure can be obtained by subtracting the current binary data of the read pointer from the binary data corresponding to the write pointer, and therefore the final state data is judged according to a preset data buffer structure state threshold value.
Please refer to fig. 4, which is a schematic flow chart of a read mode, wherein the apb configuration register module or i2s control module determines that there is an external read data request, the apb configuration register module or i2s control module generates a corresponding read enable, the apb configuration register module or i2s control module determines the status data of the current data buffer structure, if the status data of the current data buffer structure is an air break, it indicates that there is no corresponding data in the queue of the current data buffer structure, the apb configuration register module or i2s control module takes the corresponding external read data as invalid data, and the corresponding read enable is an invalid enable, at this time, because the data and the read enable are invalid, it can be ensured that reading and writing in the data queue of the data buffer structure are ordered, and an occurrence of a miss-sampling phenomenon is avoided. When the apb configuration register module or the i2s control module determines that the status data of the current data buffer structure is in a non-empty status, wherein the non-empty status includes fast empty, fast full, read full, and the like. At this time, the apb configuration register module or i2s control module takes the current external read data (from the data buffer structure) as valid data, takes the read enable as valid enable, further sends a synchronization request to the write clock domain through the valid read enable, converts the read pointer corresponding to the valid read enable into data in a gray code form, synchronizes the data in the write clock domain, converts the read pointer data converted into the gray code form into binary data, subtracts the write pointer binary data in the current data buffer structure from the read pointer data converted into the binary data, and determines the final state data in the current data buffer structure according to the subtraction result as the basis for determining the state data of the current data buffer structure and the preset state data threshold.
It is worth mentioning that the invention utilizes the handshake protocol of the one-time response mode, applies the handshake protocol to the read-write enable control, and through the control of the read-write enable, when the read-write enable is effective, the request signal is generated, and the response signal is generated by synchronizing to the opposite side clock domain, and the generated request signal is pulled down after synchronizing back to the original clock domain, thereby controlling the read-write pointer to be capable of accurately counting after synchronizing to the opposite side clock domain, and avoiding the phenomenon of read-write mis-sampling.
In another preferred embodiment of the present invention, if the apb configuration register module or the i2s control module determines that the current data buffer structure is a fast full interrupt, the generation of the write enable is stopped, so as to stop the corresponding bus from writing data into the data buffer structure, until the current data buffer structure sends out a fast empty signal, the write enable is regenerated to perform the write operation.
In particular, according to the embodiments of the present disclosure, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method illustrated in the flow chart. In such an embodiment, the computer program may be downloaded and installed from a network via the communication section, and/or installed from a removable medium. The computer program, when executed by a Central Processing Unit (CPU), performs the above-described functions defined in the method of the present application. It should be noted that the computer readable medium mentioned above in the present application may be a computer readable signal medium or a computer readable storage medium or any combination of the two. The computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples of the computer readable storage medium may include, but are not limited to: an electrical connection having one or more wire segments, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present application, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In this application, however, a computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless section, wire section, fiber optic cable, RF, etc., or any suitable combination of the foregoing.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
It will be understood by those skilled in the art that the embodiments of the present invention described above and illustrated in the drawings are given by way of example only and not by way of limitation, the objects of the invention having been fully and effectively achieved, the functional and structural principles of the present invention having been shown and described in the embodiments, and that various changes or modifications may be made in the embodiments of the present invention without departing from such principles.
Claims (10)
1. A bus-based data elastic buffering system, the system comprising:
an apb bus;
the apb configuration register module;
a data buffer structure;
i2s control module;
an i2s bus;
the data buffer structure is respectively connected with the apb configuration register module and the i2s control module in a communication mode, wherein the apb configuration register module is connected with the apb bus, the i2s control module is connected with the i2s bus, the apb configuration register module and the i2s control module establish communication connection with the data buffer structure by adopting a handshake protocol, and read-write operation is executed in the data buffer structure through the handshake protocol.
2. The bus-based data elastic buffer system according to claim 1, wherein the data buffer structure comprises a data storage unit and a data synchronization unit, wherein the data storage unit is connected to the data synchronization unit;
the data buffer structure further comprises a write control unit and a read control unit, the write control unit and the read control unit are respectively in communication connection with the data storage unit and the data synchronization unit, and the write control unit and the read control unit adopt a handshake protocol to execute synchronous operation of writing data and reading data.
3. A method for bus-based data transfer, the method comprising:
acquiring state data in a data buffer structure, and judging whether the state data is valid data or not according to the state data;
generating a valid read or write enable according to the valid data;
converting the effective read-write enable pointer into Gray codes, and synchronizing the effective read-write enable from the current clock domain to the target clock domain according to the Gray codes;
after synchronizing to a target clock domain, synchronizing the effective read or write enable to a current clock domain to execute data buffer structure state updating;
and judging whether valid data exists to execute the next read or write synchronous operation according to the updated data buffer structure.
4. A method according to claim 1, wherein the status data of the data buffer structure comprises empty, full, fast empty, fast full, read empty and read full status, and the status data constitutes an interrupt of data transmission in the buffer structure.
5. The bus-based data transmission method according to claim 1, wherein the data transmission method comprises a data writing method: the apb configuration register module and the i2s control module input data and write enable corresponding to the bus into the data buffer structure, if the data buffer structure detects external write data and judges that the state in the current data buffer structure is full interrupt, the currently detected external write data is invalid data, and the correspondingly input write enable is invalid enable.
6. The bus-based data transmission method according to claim 1, wherein, during data writing, the apb configuration register module and the i2s control module input data and write enable corresponding to the bus into the data buffer structure, when the data buffer structure detects external write data, if the current buffer structure is determined to be in a non-full state, the write enable data is valid write enable, the corresponding external write data is valid data, and the write enable is synchronized into the read clock domain and is synchronized into the current write clock domain through the handshake protocol.
7. The method as claimed in claim 1, wherein the apb configuration register module or the i2s control module inputs data corresponding to the bus and a read enable into the data buffer structure, and if the data buffer structure detects external read data, and if the current status in the data buffer structure is determined to be an air break, the currently detected external read data is regarded as invalid data, and the currently detected read enable is regarded as invalid enable.
8. The bus-based data transmission method according to claim 1, wherein the data transmission method comprises a read-out method: the apb configuration register module or the i2s control module inputs data corresponding to the bus and self read enable into the data buffer structure, if the data buffer structure detects external read data, if the state in the current data buffer structure is judged to be non-air break, the currently detected external read data is taken as effective data, the currently detected read enable is taken as effective enable, and the corresponding external read enable is synchronized into the write clock domain and the current read clock domain through the handshake protocol.
9. A method according to claim 1, wherein when synchronizing the valid read enable or write enable to the corresponding clock domain, the corresponding write pointer gray code or read pointer gray code is converted to binary data, the read pointer binary data is subtracted from the converted write pointer binary data, and the state data in the data buffer structure is regenerated according to the subtraction result and synchronized to the corresponding clock domain.
10. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program which can be executed by a processor to perform a bus-based data transmission method according to any one of claims 3 to 9.
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