CN115033047A - Band-gap reference voltage source with single-point calibration - Google Patents
Band-gap reference voltage source with single-point calibration Download PDFInfo
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- CN115033047A CN115033047A CN202210710954.6A CN202210710954A CN115033047A CN 115033047 A CN115033047 A CN 115033047A CN 202210710954 A CN202210710954 A CN 202210710954A CN 115033047 A CN115033047 A CN 115033047A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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Abstract
The invention relates to a band-gap reference voltage source with single-point calibration. Mismatch in the operational amplifier is converted into ripple for cancellation by using a ripple detection circuit and a chopping technique. And the mismatch of other devices is subjected to single-point trimming by the trimming DAC, so that the calibration of the process deviation is completed. This greatly improves the accuracy of the output voltage of the bandgap reference voltage source. The invention has wide application prospect in the field of high-precision band-gap reference voltage sources.
Description
Technical Field
The invention relates to a band-gap reference voltage source with single-point calibration.
Background
With the continuous upgrade of the integrated circuit industry, the use of chips has been deeply advanced to people's lives. Unlike other chips, sensors and analog-to-digital converter chips are a bridge between nature and electrical signals, and thus are becoming important for research in the industry and academia. The bandgap reference source is an important component of the sensor and the adc chip, and is generally applied to the integrated system due to its simple structure. With the rapid development of electronic technology and process manufacturing, the design of chips such as high-precision analog-to-digital converters and sensors is gradually becoming the mainstream in the field of integrated circuits. The circuits need the bandgap reference source to provide stable voltage, which makes the industry have higher requirements on the performance of the bandgap reference source chip. Band-gap reference source chips with low power consumption, low mismatch, low offset, high power supply rejection ratio and fast response are gradually becoming the focus of research.
The bandgap reference voltage source has high requirements on the process, but the process deviation occurring in the chip manufacturing directly affects the performance of the circuit. This is often unavoidable, so the calibration scheme of the output voltage is the key of the bandgap reference voltage source design.
Disclosure of Invention
The invention aims to provide a band-gap reference voltage source with single-point calibration, which greatly improves the precision of the output voltage of the band-gap reference voltage source.
In order to achieve the purpose, the technical scheme of the invention is as follows: a bandgap reference voltage source with single point calibration, comprising:
the ripple detection circuit is used for detecting the direction of ripple waves in the output offset voltage signal of the core circuit operational amplifier of the band-gap reference voltage source, namely the mismatching direction of the core circuit operational amplifier;
the state machine is used for converting the output signal of the ripple detection circuit into an analog voltage signal;
and the two trimming DACs are used for converting the analog voltage signal into a trimming voltage signal and outputting the trimming voltage signal to the core circuit operational amplifier.
In an embodiment of the present invention, the present invention further includes a clock generation module for generating a clock signal and a switching signal required by each module.
In an embodiment of the present invention, the analog voltage signal is an 8-bit code stream, and the two trimming DACs convert the 8-bit code stream and respectively output trimming voltages V decreasing from high to low trim1 And a trimming voltage V increasing from low to high trim2 。
In an embodiment of the present invention, the ripple detection circuit includes a self-zeroing system composed of three stages of operational amplifiers, and a dynamic comparator; the self-zeroing system comprises three operational amplifiers which are connected in sequence, two inputs of the three operational amplifiers are connected with input capacitors, and switches are connected between the first inputs and the first outputs and between the second inputs and the second outputs of the three operational amplifiers; when the switch is closed, the three operational amplifiers are connected into a buffer structure, and the self-zeroing system is in a reset state at the moment; when the switch is switched off, the self-zero-adjusting system is in an amplifying state, and the ripple waves in the input offset voltage signals are amplified.
In an embodiment of the present invention, the dynamic comparator includes a fourth operational amplifier and a latch; the structure of the fourth operational amplifier is a negative resistance amplifier structure; the latch is composed of a discharge transistor, an NMOS trigger for opening/closing an upper path and a lower path, a PMOS trigger for opening/closing the upper path and the lower path, and a PMOS pre-charge transistor.
In an embodiment of the present invention, the state machine is composed of an 8-bit reversible counter, and the output signal RP of the ripple detection circuit represents the polarity of the ripple; the RP is used as a signal for judging addition and subtraction of the 8-bit counter, and when the RP is in a high level, the 8-bit counter counts up; when RP is low level, the 8-bit counter counts down; the counter outputs 8-bit digital code streams which are converted into trimming voltages through the two trimming DACs.
Compared with the prior art, the invention has the following beneficial effects: the invention utilizes the ripple detection circuit to convert the mismatch in the operational amplifier into ripple waves for elimination. And the mismatch of other devices is subjected to single-point trimming by the trimming DAC, so that the calibration of the process deviation is completed. This greatly improves the accuracy of the output voltage of the bandgap reference voltage source. The invention has wide application prospect in the field of high-precision band-gap reference voltage sources.
Drawings
FIG. 1 is a schematic diagram of a single point calibration bandgap reference voltage source.
Fig. 2 shows the working principle of digital trimming voltage.
Fig. 3 is a schematic diagram of a ripple detection circuit.
Fig. 4 is a timing diagram of ripple detection.
Fig. 5 is a schematic diagram of a comparator.
Fig. 6 is a clock generation circuit and an 8-bit counter.
FIG. 7 is a schematic diagram of single point trimming; (a) the output voltage of the band-gap reference source with process deviation; (b) and (4) the output voltage of the band-gap reference source after trimming.
Detailed Description
The technical scheme of the invention is specifically explained below with reference to the accompanying drawings.
The invention relates to a band-gap reference voltage source with single-point calibration, which comprises:
the ripple detection circuit is used for detecting the direction of ripple waves in the output offset voltage signal of the core circuit operational amplifier of the band gap reference voltage source, namely the mismatching direction of the core circuit operational amplifier;
the state machine is used for converting the output signal of the ripple detection circuit into an analog voltage signal;
and the two trimming DACs are used for converting the analog voltage signal into a trimming voltage signal and outputting the trimming voltage signal to the core circuit operational amplifier.
And the clock generation module is used for generating clock signals and switching signals required by the modules.
The following is a specific implementation process of the present invention.
The invention provides a calibration scheme for a band-gap reference voltage source, and the whole circuit diagram is shown in figure 1. The technical scheme adopted by the invention is as follows: firstly, mismatch of an operational amplifier is converted into ripples, mismatch information is converted into analog voltage through a state machine, and finally the analog voltage is fed back to the operational amplifier to achieve elimination of the mismatch; secondly, the influence caused by the mismatch of other devices except the operational amplifier is eliminated by a single-point trimming method.
As shown in FIG. 1, the output signal V of the operational amplifier of the core circuit A Is the input signal of the ripple detection loop, and V A Is a signal with ripple. The ripple detection loop detects the direction of the ripple, i.e., the direction of the op-amp mismatch. The RP signal is a signal with ripple polarity representing the mismatch direction, with high being in the forward direction and low being in the reverse direction. And the RP controls the state machine at the rear stage to output 8-bit code streams. The clock generation module generates clock signals and switching signals required by each module to control the ripple detection loopAnd (4) a ripple detection process of the circuit. The two DACs complete the conversion of 8-bit code stream and output trimming voltage V decreasing from high to low trim1 And a trimming voltage V increasing from low to high trim2 . The output voltage ripple of the core circuit is reduced by the two trimming voltages, and the trimming voltage changes as shown in fig. 2. Trimming voltage V at initial stage trim1 And V trim2 Are all set to V o . If the ripple wave detection circuit detects that the ripple wave is in the positive direction, the trimming voltage changes according to the A direction, namely V trim1 Rises to V trim2 Descending; if the ripple detection circuit detects that the ripple is reverse, the trimming voltage changes according to the B direction, namely V trim1 Falls to V trim2 And (4) rising. Since the system is continuous, the ripple amplitude on the output voltage can be minimized after many cycles, and the circuit thereafter is in dynamic balance, according to the above operating principle.
As shown in fig. 3, the ripple detection circuit includes two parts: the self-zeroing system consists of three-stage operational amplifier and dynamic comparator. SW is a control signal of a switch of the self-zero-adjusting system, the switch is closed when the high level is reached, the operational amplifier is connected into a structure of a buffer, and the system is in a reset state at the moment; when the low level is output, the switch is opened, the self-zero-adjusting system is in an amplifying state, and V is converted into a voltage ref To the extent that the comparator can detect the ripple in (b). Capacitor C 1 、C 2 And C 3 The offset voltage is used for isolating direct current quantity and storing the offset voltage of the operational amplifier when the self-zeroing system works. When the SW is high level, the switch is closed, and the output end and the input end of the operational amplifier are in short circuit, namely the operational amplifier is a unity gain amplifier. The input is now equal to the output and the offset voltage is applied across the input capacitor. When the signal is amplified, the voltage on the capacitor is amplified along with the input signal. Due to the characteristics of this circuit configuration, the offset voltage can be cancelled. As shown in fig. 4, COMP _ DFF is a clock of the D flip-flop, and controls the output of the comparison signal. CH is a chopped signal, Clk is the clock of the comparator, and when Clk is high, the comparator starts to work normally and can compare signals at input ends. COMP _ DFF and rising edge of switch signal SW have a delay t 1 The purpose is to provide a system that, after the system amplifies the ripple,and the mismatch direction is obtained by comparing after the whole circuit is stabilized. When SW is low level, Clk is high level, at this time, the system is in a stable amplification state, and the comparator starts to work normally. COMP _ DFF and chopping signal CH rising edge have a time delay t 0 . When CH is low level, the voltage of the input end of the comparator is not equal to the common mode level, and amplification comparison can be carried out.
The static comparator is not clocked and is therefore relatively less affected by offset voltages and other non-idealities. In contrast, in the other comparator of the comparators, the dynamic comparator is controlled by the clock, and the static power consumption is very small. The total power consumption of the comparator is relatively small. Since the ripple detection circuit does not need to be detecting every moment, the design selects a dynamic comparator with relatively small power consumption.
As shown in fig. 5, the comparator consists of two parts: an operational amplifier and a latch. The structure of the operational amplifier is a negative resistance amplifier structure for amplifying an input signal so that the operating currents of the M8 and M11 transistors are not the same in magnitude, thereby controlling the operation of the latch. The latch is composed of a discharge transistor, an NMOS trigger for opening and closing an upper path and a lower path, a PMOS trigger and a PMOS pre-charge transistor. A flip-flop that is gated on the drain region has advantages over a flip-flop that is gated on the source region in re-establishing speed and offset voltage. Since the carrier mobility at zero substrate bias is almost twice that at several volts substrate bias, the flip-flop re-establishes faster than in drain gating. Furthermore, since the switching transistor isolates the flip-flop from the output node, it can be considered as a load device of the flip-flop, and the load capacitance can be considered as a gate capacitance of the PMOS flip-flop itself. The offset voltage caused by channel length fluctuations is much lower than at zero volt substrate bias. Therefore, the channel length of the transistor is reduced to increase the trigger speed. The output node of the P flip-flop is connected to an inverter.
The dynamic process of the comparator can be divided into a reset phase and a comparison phase. In the reset phase, Clk is at low level, and the transistor M is switched 12 And M 13 And closing. And a PMOS pre-charge transistor M 14 And M 17 And (4) opening. Thereby from M 15 And M 16 The two PMOS trigger nodes formed are charged to the supply voltage. And is composed of M 9 And M 10 The resulting NMOS trigger node is discharged to ground through the discharge transistor. When Clk is high, the charge current starts to flow from the PMOS flip-flop to the NMOS flip-flop. Part of the current passes through M 8 And M 11 And flows to ground. As long as M 8 And M 11 A difference occurs in the current of (A) resulting in M 9 And M 10 When the drain voltage exceeds the threshold voltage, a large voltage difference is generated at the output terminal. When the flip-flop reaches above unity gain, the voltage difference is rapidly amplified. The amplified voltage difference is transferred to the PMOS flip-flop through the switching tube equivalent to the common gate amplifier and amplified to be close to the power supply voltage.
The state machine mainly comprises an 8-bit reversible counter, and the output signal RP of the ripple detection circuit represents the polarity of the ripple. The RP is used as a signal for judging addition and subtraction of the 8-bit counter, and when the RP is in a high level, the 8-bit counter counts up; when RP is low, the 8-bit counter counts down. The clock signal of the counter is the switching signal SW in the ripple detection circuit. The SW transition from low to high represents the comparator comparison is over and the mismatch trimming can begin. When the rising edge of the switch signal SW comes, the counter is increased or decreased by one. The counter outputs a digital code of 8 bits which can be converted to a trimming voltage by the DAC. As shown in fig. 6, COMP _ DFF is the clock of the comparator back-end D flip-flop, which outputs the comparison result of the ripple. The chopping clock CH is a COMP _ DFF delayed signal, Clk cnt Is one of the output signals of the clock generation module.
The single-point trimming operation principle is as shown in fig. 7, when the switching signal ctrl is at a low level, the trimming DAC is turned off, and the output reference voltage is not trimmed at this time. When the switching signal ctrl is at a high level, the trimming DAC is turned on, and the output reference voltage is trimmed at this time. The trimming process is carried out after the offset voltage of the operational amplifier is eliminated. DATA<0:5>The digital coding signal of the trimming DAC is input with a parallel digital code of 6 bits, and the output voltage of the band-gap reference voltage source can be adjusted. FIG. 7 (a) shows the presence of process variationThe output voltage of the bandgap reference source is different from chip to chip. Because of process deviation, random errors occur in the output voltage of the bandgap reference source, and therefore the error of trimming the output voltage needs to be considered. If the temperature is T 0 The voltage value is a standard value, all band-gap reference sources with outputs not equal to the standard value are required to be modified at the temperature, the modification DAC is set to be 6 bits in consideration of the area and the power consumption cost, and the modification result is shown in fig. 7 (b).
The above are preferred embodiments of the present invention, and all changes made according to the technical solutions of the present invention that produce functional effects do not exceed the scope of the technical solutions of the present invention belong to the protection scope of the present invention.
Claims (6)
1. A bandgap reference voltage source with single point calibration, comprising:
the ripple detection circuit is used for detecting the direction of ripple waves in the output offset voltage signal of the core circuit operational amplifier of the band gap reference voltage source, namely the mismatching direction of the core circuit operational amplifier;
the state machine is used for converting the output signal of the ripple detection circuit into an analog voltage signal;
and the two trimming DACs are used for converting the analog voltage signal into a trimming voltage signal and outputting the trimming voltage signal to the core circuit operational amplifier.
2. The bandgap reference voltage source with single-point calibration as claimed in claim 1, further comprising a clock generation module for generating clock signals and switching signals required by each module.
3. The bandgap reference voltage source of claim 1, wherein the analog voltage signal is an 8-bit code stream, and the two trimming DACs convert the 8-bit code stream to output trimming voltages V decreasing from high to low respectively trim1 And a trimming voltage V increasing from low to high trim2 。
4. The bandgap reference voltage source with single-point calibration according to claim 1, wherein the ripple detection circuit comprises a self-zeroing system consisting of three stages of operational amplifiers, a dynamic comparator; the self-zeroing system comprises three operational amplifiers which are connected in sequence, two inputs of the three operational amplifiers are connected with input capacitors, and switches are connected between the first inputs and the first outputs and between the second inputs and the second outputs of the three operational amplifiers; when the switch is closed, the three operational amplifiers are connected into a buffer structure, and the self-zeroing system is in a reset state at the moment; when the switch is switched off, the self-zero-adjusting system is in an amplifying state, and the ripples in the input offset voltage signals are amplified.
5. The bandgap reference voltage source with single point calibration as claimed in claim 4, wherein said dynamic comparator comprises a fourth operational amplifier and a latch; the fourth operational amplifier is in a negative resistance amplifier structure; the latch is composed of a discharge transistor, an NMOS trigger for opening/closing an upper path and a lower path, a PMOS trigger for opening/closing the upper path and the lower path, and a PMOS pre-charge transistor.
6. The bandgap reference voltage source with single-point calibration according to claim 1, wherein the state machine is composed of an 8-bit up-down counter, and the ripple detection circuit output signal RP represents the ripple polarity; the RP is used as a signal for judging addition and subtraction of the 8-bit counter, and when the RP is in a high level, the 8-bit counter counts up; when RP is low level, the 8-bit counter counts down; the counter outputs 8-bit digital code streams which are converted into trimming voltages through the two trimming DACs.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115291665A (en) * | 2022-09-13 | 2022-11-04 | 南京大学 | Band-gap reference circuit with offset cancellation |
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