CN115021750B - Digital-analog converter with doubled output speed and coding method thereof - Google Patents
Digital-analog converter with doubled output speed and coding method thereof Download PDFInfo
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- CN115021750B CN115021750B CN202210807257.2A CN202210807257A CN115021750B CN 115021750 B CN115021750 B CN 115021750B CN 202210807257 A CN202210807257 A CN 202210807257A CN 115021750 B CN115021750 B CN 115021750B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0634—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale
- H03M1/0656—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal
- H03M1/066—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/742—Simultaneous conversion using current sources as quantisation value generators
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Abstract
The invention discloses a digital-analog converter with doubled output speed and a coding method thereof, belonging to the technical field of digital-analog conversion, wherein the digital-analog converter comprises: the clock data synchronization modules are provided with at least two clock data synchronization modules, are electrically connected with the input end and are used for ensuring that data switching signals of the input end are kept synchronous; one end of the decoding/delaying module is electrically connected with the clock data synchronization module, the other end of the decoding/delaying module is electrically connected with the input end of the current source array, and the decoding/delaying module is used for decoding high-order data at the input end, randomizing the decoding by adopting a dynamic element matching method, and simultaneously ensuring that low-order data are synchronized with the decoded data; a current source array; a bias circuit; the invention aims to provide a digital-to-analog converter with doubled output rate and a coding method thereof, which can change the system error and improve the performance precision of the digital-to-analog converter by designing different opening sequences for unit current sources in a current source array.
Description
Technical Field
The invention relates to the technical field of digital-to-analog conversion, in particular to a digital-to-analog converter with doubled output rate and an encoding method thereof.
Background
With the development of signal processing and communication technologies, the speed and precision of conversion between digital-to-analog signals have great limitations on systems, and the digital-to-analog converter with high speed and high precision, namely a digital-to-analog converter (DAC), has obvious effects. The existing high-speed digital-to-analog converter DAC generally adopts a current steering digital-to-analog converter DAC, in order to realize higher output rate, a multi-channel parallel structure is generally adopted, the design of a gating circuit of the DAC is a key point, the general gating circuit occupies a large area of a chip, and meanwhile, smaller resource consumption is difficult to apply, so that the output rate is improved.
Meanwhile, a high-precision digital-to-analog converter needs to have good matching performance among current sources, but in the existing circuit, devices are difficult to avoid having mismatch, a system error is one of main factors influencing the matching performance among unit current sources, and the system error mainly comprises a linear gradient error and a square gradient error. The random error can be significantly reduced by increasing the area, but increasing the circuit area will deteriorate the systematic error, resulting in a vicious cycle, and the problem of high accuracy cannot be solved.
Disclosure of Invention
The invention aims to provide a digital-to-analog converter with doubled output rate and a coding method thereof, which can change the system error and improve the performance precision of the digital-to-analog converter by designing different opening sequences for unit current sources in a current source array.
In order to achieve the purpose, the invention adopts the following technical scheme: a digital-to-analog converter with doubled output rate, comprising:
the clock data synchronization modules are provided with at least two clock data synchronization modules, are electrically connected with the input end and are used for ensuring that data switching signals of the input end are kept synchronous;
one end of the decoding/delaying module is electrically connected with the clock data synchronization module, the other end of the decoding/delaying module is electrically connected with the input end of the current source array, and the decoding/delaying module is used for decoding high-order data at the input end, randomizing the decoding by adopting a dynamic element matching method, and simultaneously ensuring that low-order data are synchronized with the decoded data;
the current source array is used for converting the digital code signal input by the input end into an analog current signal;
and the bias circuit is electrically connected with the current source array and used for providing unit current for the current source array and providing grid voltage for each current source of the current source array.
Preferably, the current source array includes:
the MOS tube M1 is electrically connected with the bias circuit and is used for providing current for the other elements of the current source array;
the MOS tube M2 is electrically connected with the bias circuit and the MOS tube M1 and is used for improving the output impedance of the current source array;
the MOS tube M3 is electrically connected with the MOS tube M2, is accessed to a first clock signal and is used for selecting the on or off of partial branches of the current source array;
the MOS tube M4 is electrically connected with the MOS tube M2, is accessed with a second clock signal and is used for selecting the connection or disconnection of the rest part of branches of the current source array, and the first clock signal and the second clock signal are opposite signals;
the MOS tube M5 and the MOS tube M6 are electrically connected with the MOS tube M3 and are used for converting the input digital code signal into a first analog current signal;
and the MOS tube M7 and the MOS tube M8 are electrically connected with the MOS tube M4 and used as another group of data switches for converting the input digital code signal into a second analog current signal.
Preferably, when the MOS transistor M3 inputs a low level signal, the MOS transistor M5 and the MOS transistor M6 are selected as data switches; when the MOS transistor M4 inputs a low level signal, the MOS transistor M7 and the MOS transistor M8 are selected as data switches.
Preferably, the decoding/delaying module includes a module for decoding the high n bits of the input digital code signal to obtain 2 n -a temperature code of 1 bit, 2 n Dividing the temperature codes of 1 bit into n groups, setting a shift direction, wherein n-1 is the number of bits of the maximum shift distance, and performing shift operation by combining the output of the linear feedback shift register and the shift direction of the temperature codes of each group to obtain random temperature codes.
Preferably, the linear feedback shift register is used to implement a pseudo-random sequence, and the feedback function is: f (x) = x ^23+ x ^5+1.
Preferably, the device further comprises a serial-to-parallel conversion interface electrically connected to the clock data synchronization module, and configured to convert a serial signal input from the input terminal into a parallel signal.
A coding method of digital-to-analog converter with doubled output rate is applied to the digital-to-analog converter with doubled output rate, and high n bits of input digital code signals are decoded to obtain 2 n -a temperature code of 1 bit, 2 n Dividing the temperature codes of 1 bit into n groups, setting a shift direction, wherein n-1 is the number of bits of the maximum shift distance, and performing shift operation by combining the output of the linear feedback shift register and the shift direction of the temperature codes of each group to obtain random temperature codes.
Preferably, the feedback function of the linear feedback shift register is: f (x) = x ^23+ x ^5+1.
The technical scheme of the invention has the beneficial effects that: the method has the advantages that different opening sequences are designed for unit current sources in the current source array, system errors can be changed, the performance precision of the digital-to-analog converter is improved, the influence of mismatch on the performance of the digital-to-analog converter can be reduced by a dynamic element matching method, the reset function is realized, the positive output end of the digital-to-analog converter is full-amplitude output through a reset signal, and the negative output end of the digital-to-analog converter is 0. By improving the current source switch structure, when the digital-to-analog converter works in a frequency range, the output speed of the digital-to-analog converter is doubled without adding an additional multi-channel gating circuit, so that the circuit resource is saved, and the dynamic performance of the digital-to-analog converter is improved by matching a dynamic element with a DEM algorithm.
Drawings
FIG. 1 is a schematic block diagram of one embodiment of the present invention;
FIG. 2 is a schematic diagram of a current source array according to an embodiment of the present invention;
FIG. 3 is a block timing diagram of one embodiment of the present invention;
FIG. 4 is a decoding diagram of dynamic element matching according to an embodiment of the present invention.
Wherein: the device comprises a clock data synchronization module 1, a decoding/delaying module 2, a current source array 3, a bias circuit 4 and a serial-parallel conversion interface 5.
Detailed Description
The technical scheme of the invention is further explained by the specific implementation mode in combination with the attached drawings.
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In the description of the present invention, "a plurality" means two or more unless otherwise specified.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in a specific case to those of ordinary skill in the art.
Referring to fig. 1 to 4, a digital-to-analog converter with doubled output rate includes:
the clock data synchronization modules are provided with at least two clock data synchronization modules, are electrically connected with the input end and are used for ensuring that data switching signals of the input end are kept synchronous;
one end of the decoding/delaying module is electrically connected with the clock data synchronization module, the other end of the decoding/delaying module is electrically connected with the input end of the current source array, and the decoding/delaying module is used for decoding high-order data at the input end, randomizing the decoding by adopting a dynamic element matching method, and simultaneously ensuring that low-order data are synchronized with the decoded data;
the current source array is used for converting a digital code signal input by the input end into an analog current signal;
and the bias circuit is electrically connected with the current source array and is used for providing unit current for the current source array and providing grid voltage for each current source of the current source array.
With the development of signal processing and communication technologies, the speed and precision of conversion between digital-to-analog signals have great limitations on systems, and the digital-to-analog converter with high speed and high precision, namely a digital-to-analog converter (DAC), has obvious effects. The existing high-speed digital-to-analog converter DAC generally adopts a current steering digital-to-analog converter DAC, in order to realize higher output rate, a multi-path parallel structure is generally adopted, the design of a gating circuit of the DAC is a key point, the general gating circuit occupies a large area of a chip, and meanwhile, the general gating circuit is difficult to apply smaller resource consumption, so that the output rate is improved.
Meanwhile, a high-precision digital-to-analog converter needs to have good matching performance among current sources, but in the existing circuit, devices are difficult to avoid having mismatch, a system error is one of main factors influencing the matching performance among unit current sources, and the system error mainly comprises a linear gradient error and a square gradient error. The random error can be significantly reduced by increasing the area, but increasing the circuit area will deteriorate the systematic error, resulting in a vicious cycle, and the problem of high accuracy cannot be solved.
This application can change the system error through the different opening order of unit current source design in to the current source array, improves the precision of digital analog converter performance, can reduce the influence of mismatch to digital analog converter performance through the method of dynamic component matching, has the reset function, makes digital analog converter's positive output end be full output through reset signal, and the negative output end is 0. By improving the current source switch structure, when the digital-to-analog converter works in a frequency range, the output speed of the digital-to-analog converter is doubled without adding an additional multi-channel gating circuit, so that the circuit resource is saved, and the dynamic performance of the digital-to-analog converter is improved by matching a dynamic element with a DEM algorithm.
The bias circuit has the function of providing grid voltage for the current source array, and internally comprises a Bandgap circuit and a V-I conversion circuit, and provides bias grid voltage for the current source circuit.
The clock data synchronization module aligns input data, aligns a temperature code which is input at a high position and decoded with a digital code which is input at a low position, and prevents data errors.
Preferably, the current source array includes:
the MOS tube M1 is electrically connected with the bias circuit and is used for providing current for the other elements of the current source array;
the MOS tube M2 is electrically connected with the bias circuit and the MOS tube M1 and is used for improving the output impedance of the current source array;
the MOS tube M3 is electrically connected with the MOS tube M2, is accessed to a first clock signal and is used for selecting the on or off of partial branches of the current source array;
the MOS tube M4 is electrically connected with the MOS tube M2, is accessed with a second clock signal and is used for selecting the on or off of the branches of the rest part of the current source array, and the first clock signal and the second clock signal are opposite signals;
the MOS tube M5 and the MOS tube M6 are electrically connected with the MOS tube M3 and are used for converting the input digital code signal into a first analog current signal;
and the MOS tube M7 and the MOS tube M8 are electrically connected with the MOS tube M4 and used as another group of data switches for converting the input digital code signal into a second analog current signal.
The current source array doubles the conversion rate of the whole digital-to-analog converter through dynamic logic, and realizes the rate doubling effect through corresponding control time sequence, and the current source array comprises 2^ n-1+ n current sources, wherein the current source array comprises 2^ n-1 MSB current sources and n LSB current sources; in the current source array, the positive output ends of all MSB circuit sources are connected with the positive output end of the LSB circuit source, and form the positive output of the whole digital-to-analog converter; the negative output ends of all MSB circuit sources are connected with the negative output end of the LSB circuit source to form the negative output of the whole digital-to-analog converter, and the current difference of the positive output and the negative output is the differential output of the whole digital-to-analog converter, namely the invention is designed for the digital-to-analog converter with differential output.
The MOS transistor M1 is used as an MOS transistor for providing current, and the influence of the mismatch on the performance of the whole circuit needs to be considered in the design; the MOS transistor M2 is a Cascode stage, so that the output impedance of the current source is improved, and the whole circuit has better dynamic performance; the MOS tube M3 and the MOS tube M4 are clock switches, a passing branch of a current source is selected through a clock signal, and then an input digital code is converted into an analog current signal through a data switch; the MOS transistor M5 and the MOS transistor M6, and the MOS transistor M7 and the MOS transistor M8 are two pairs of data switches, and when the digital-to-analog converter normally works, the input digital code is converted according to the principle that the PMOS is switched off at a high level and switched on at a low level.
The MOS transistor M1 and the MOS transistor M2 are in a saturation region in the working process, current is provided to a node A, then the MOS transistor M3 and the MOS transistor M4 are switched through a clock, control signals are CLKn and CLK respectively, the CLKn signal is an inverse signal of the CLK signal, and since PMOS is conducted at low level, the current of the node A flows to a node B through the MOS transistor M3 when the CLK is at high level, and the current of the node A flows to a node C through the MOS transistor M4 when the CLK is at low level. The current generated by the MOS transistor M1 can be selected according to the height of a clock signal, and when the clock signal is at a high level, the input digital code IN1 is converted into the current to the MOS transistor M5 and the MOS transistor M6 through a data switch; when the clock signal is at high level, the input digital code IN2 is converted into current through the data switch pair MOS transistor M7 and MOS transistor M8. After digital-to-analog conversion is completed each time, each current source outputs corresponding current at the positive output end and the negative output end according to the size of the input code. It can be seen from the figure that the input digital codes IN1 and IN2 change once IN a CLK period, and the output of the current source changes once per CLK/2 period, so that the conversion rate of the digital-to-analog converter is doubled, and the process can be realized by only adding a pair of clock switches, if the whole digital-to-analog converter is adapted to the normal working condition, one end of the switching signal can be fixed to be a high level, the other end of the switching signal can be fixed to be a low level, and the input digital codes IN1 and IN2 are the same data, which can be the same as the normal digital-to-analog converter.
In the application, when a low level signal is input into the MOS transistor M3, the MOS transistor M5 and the MOS transistor M6 are selected as data switches; when the MOS transistor M4 inputs a low level signal, the MOS transistor M7 and the MOS transistor M8 are selected as data switches.
The current source array enables the data rate to be doubled through the arrangement of a switch structure, and the switch structure comprises two pairs of data switches: the MOS transistor M5, the MOS transistor M6, the MOS transistor M7 and the MOS transistor M8 are composed of 4 MOS transistors; a pair of clock switches: MOS pipe M3 and MOS pipe M4, 2 MOS pipes altogether constitute. Through the direction output by the data switch selection circuit, one path of data of the corresponding data switch is selected and output through the clock switch, wherein the frequency of the clock signal is the same as that of the clock data synchronization module at the previous stage, and one group of data switches or the other group of data switches are respectively selected through the high and low levels of the clock signal, so that the current source array outputs corresponding current, and the speed is doubled at the working frequency; if necessary, the frequency of the clock switch can be adjusted to realize higher-speed output, and each current source comprises two pairs of data switches and one pair of clock switches.
Specifically, the decoding/delaying module comprises a module for decoding the high n bits of the input digital code signal to obtain 2 n -a temperature code of 1 bit, 2 n -1 bit temperature code into n groups, setting shiftAnd (3) carrying out shift operation by combining the output of the linear feedback shift register and the shift directions of the temperature codes of all the groups to obtain random temperature codes, wherein n-1 is the number of bits of the maximum shift distance. The linear feedback shift register is used for realizing a pseudo-random sequence, and the feedback function of the linear feedback shift register is as follows: f (x) = x ^23+ x ^5+1.
The decoding/delaying module comprises a decoding and delaying function and is used for operating the data of input 2n bits, wherein the decoding module performs decoding operation on the input high n bits and decodes the input high n bits into the temperature code of 2^ n-1 bits, and the delaying module performs delaying operation on the input low n bits to align the input low n bits with the high data. The temperature code of 2^ n-1 bits controls 2^ n-1 MSB current sources, and the low-n bit input controls n LSB current sources.
The decoding/time-delay module further encodes the temperature code by adopting a Dynamic Element Matching (DEM) technology, so that the current source groups selected by the decoding/time-delay module are different when the temperature code is input identically, the periodic occurrence of mismatch errors of the current sources can be effectively inhibited, the harmonic energy is reduced, and certain noise can be generated. The dynamic element matching DEM algorithm designed by the invention is processed by grouping, current sources corresponding to high-order input codes are divided into an odd group and an even group after being numbered, and then the translated temperature codes have a randomization effect through rotation; this effect is achieved by means of a pseudo-random code, which is implemented by means of a linear feedback shift register, controlling the direction and number of shifts by means of the pseudo-random code, thereby achieving the desired effect.
The digital code input to the data switch is not consistent with the digital code input to the digital-to-analog converter from the outside, and the digital code can enter the data switch after being decoded by a decoder inside the digital-to-analog converter, so that the current corresponding to the digital code is output. In the invention, the temperature code translated by the high order is randomized, and for the input code of the high order n, 2 can be obtained according to the temperature code decoding n -1 bit output code, 2 n The-1 data is divided into n groups and then shifted according to a specific mode, the maximum shift distance is n-1 bits, and finally a randomized code word is obtained and input into the data switch.
For further explanation, assuming that the upper data has 4 bits, i.e. bits { U3, U2, U1, U0}, respectively, then a 15-bit codeword can be obtained after decoding, i.e. { B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0}, and corresponds to the following general decoding: u3 → { B14, B13, B12, B11, B10, B9, B8, B7}, U2 → { B6, B5, B4, B3}, U1 → { B2, B1}, U0 → { B0}. This time, dividing B14-B0 into 4 groups, which are denoted as groups 1, 2, 3, and 4, and are respectively: { B0, B4, B8, B12}, { B1, B5, B9, B13}, { B2, B6, B10, B14}, { B3, B7, B11}. It can be seen that there are a maximum of 4 current sources per group, so the number of shifts is maximum at bit 3. And then, shifting each group according to the pseudo-random sequence to randomly disorder each group. Wherein the shift directions of the 1 st group and the 2 nd group are the same, and the shift is right; the moving directions of the 3 rd group and the 4 th group are the same, and the moving direction is left moving. The invention also realizes a pseudo-random sequence through a pseudo-random code through a linear feedback shift register, and the feedback expression is as follows: f (x) = x ^23+ x ^5+1, and the lower 6 bits thereof are taken as the basis of the shift bit number. Wherein the M2-M0 bit outputs of the pseudo-random sequence control the 1 st and 3 rd groups and the M5-M3 bit outputs control the 2 nd and 4 th groups. When the output appears "1", each group is shifted by 1 bit in the shift direction. As shown in fig. 3. If the M2-M0 bit output of the pseudorandom sequence is "111", group 1 is shifted right by 3 bits to { B4, B8, B12, B0}, and group 3 is shifted left by 3 bits to { B14, B2, B6, B10}; the M5-M3 bit output is "100", the group 2 right shift by 1 bit becomes { B13, B1, B5, B9}, and the group 4 left shift by 1 bit becomes { B7, B11, B3}. At this time, the corresponding relationship between U3-U0 and B14-B0 is: u3 → { B10, B9, B0, B3, B6, B5, B12, B11}, U2 → { B2, B1, B8, B7}, U1 → { B14, B13}, U0 → { B4}, and if U3-U0 is "0110" at this time, the selected current source will be { B2, B1, B8, B7, B14, B13}. According to the method, the current sources corresponding to U3-U0 are different every time, energy generated by current source mismatch cannot be generated periodically, harmonic waves are formed, and the performance of the digital-to-analog converter is reduced.
Preferably, the device further comprises a serial-to-parallel conversion interface electrically connected to the clock data synchronization module and used for converting the serial signal input from the input terminal into a parallel signal.
Two groups of data signals are adopted, the two groups of data signals are simultaneously input through a serial-parallel conversion interface, and the two groups of data signals are kept synchronous through a clock data synchronization module.
A coding method of digital-to-analog converter with doubled output rate is applied to the digital-to-analog converter with doubled output rate, and high n bits of input digital code signals are decoded to obtain 2 n -a temperature code of 1 bit, 2 n The temperature codes with 1 bit are divided into n groups, the shifting direction is set, n-1 is the number of bits with the maximum shifting distance, and the shifting operation is carried out by combining the output of the linear feedback shifting register and the shifting direction of the temperature codes of each group to obtain random temperature codes. The feedback function of the linear feedback shift register is as follows: f (x) = x ^23+ x ^5+1.
In the description herein, references to the description of the terms "embodiment," "example," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The technical principle of the present invention is described above in connection with specific embodiments. The description is made for the purpose of illustrating the principles of the invention and should not be construed in any way as limiting the scope of the invention. Based on the explanations herein, those skilled in the art will be able to conceive of other embodiments of the present invention without inventive effort, which would fall within the scope of the present invention.
Claims (7)
1. A digital-to-analog converter with doubled output rate, comprising:
the clock data synchronization modules are provided with at least two clock data synchronization modules, are electrically connected with the input end and are used for ensuring that data switching signals of the input end are kept synchronous;
one end of the decoding/delaying module is electrically connected with the clock data synchronization module, the other end of the decoding/delaying module is electrically connected with the input end of the current source array, and the decoding/delaying module is used for decoding high-order data at the input end, randomizing the decoding by adopting a dynamic element matching method, and simultaneously ensuring that low-order data are synchronized with the decoded data;
the current source array is used for converting the digital code signal input by the input end into an analog current signal;
the bias circuit is electrically connected with the current source array and used for providing unit current for the current source array and providing grid voltage for each current source of the current source array;
the current source array includes:
the MOS tube M1 is electrically connected with the bias circuit and is used for providing current for the other elements of the current source array;
the MOS tube M2 is electrically connected with the bias circuit and the MOS tube M1 and is used for improving the output impedance of the current source array;
the MOS tube M3 is electrically connected with the MOS tube M2, is accessed to a first clock signal and is used for selecting the on or off of partial branches of the current source array;
the MOS tube M4 is electrically connected with the MOS tube M2, is accessed with a second clock signal and is used for selecting the connection or disconnection of the rest part of branches of the current source array, and the first clock signal and the second clock signal are opposite signals;
the MOS tube M5 and the MOS tube M6 are electrically connected with the MOS tube M3 and are used for converting the input digital code signal into a first analog current signal;
and the MOS tube M7 and the MOS tube M8 are electrically connected with the MOS tube M4 and used as another group of data switches for converting the input digital code signal into a second analog current signal.
2. The DAC with doubled output rate according to claim 1, wherein MOS transistor M5 and MOS transistor M6 are selected as data switches when MOS transistor M3 inputs low level signal; when the MOS transistor M4 inputs a low level signal, the MOS transistor M7 and the MOS transistor M8 are selected as data switches.
3. The DAC with doubled output rate as claimed in claim 1, wherein the decoding/delay module comprises a module for decoding the high n bits of the input digital code signal to obtain 2 n -a temperature code of 1 bit, 2 n Dividing the temperature codes of 1 bit into n groups, setting a shift direction, wherein n-1 is the number of bits of the maximum shift distance, and performing shift operation by combining the output of the linear feedback shift register and the shift direction of the temperature codes of each group to obtain random temperature codes.
4. The DAC with doubled output rate according to claim 3, wherein the linear feedback shift register is used to implement pseudo-random sequence, and the feedback function is: f (x) = x ^23+ x ^5+1.
5. The DAC with doubled output rate according to claim 1, further comprising a serial-to-parallel conversion interface electrically connected to the clock data synchronization module for converting serial signals inputted from the input terminal into parallel signals.
6. A coding method of a digital-to-analog converter with doubled output rate, applied to the digital-to-analog converter with doubled output rate of any one of claims 1 to 5, characterized in that the high n bits of the input digital code signal are decoded to obtain 2 n -a temperature code of 1 bit, 2 n Dividing the temperature codes of 1 bit into n groups, setting a shift direction, wherein n-1 is the number of bits of the maximum shift distance, and performing shift operation by combining the output of the linear feedback shift register and the shift direction of the temperature codes of each group to obtain random temperature codes.
7. The method as claimed in claim 6, wherein the feedback function of the linear feedback shift register is: f (x) = x ^23+ x ^5+1.
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Citations (2)
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|---|---|---|---|---|
| CN102332922A (en) * | 2011-07-25 | 2012-01-25 | 复旦大学 | Current source and drive circuit for improving high frequency characteristic of digital analog converter |
| WO2021258949A1 (en) * | 2020-06-22 | 2021-12-30 | 东南大学 | Current steering digital-to-analog converter based on hybrid coding |
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| US20070126616A1 (en) * | 2005-12-07 | 2007-06-07 | Min Hyung Cho | Dynamically linearized digital-to-analog converter |
| CN101741389A (en) * | 2009-12-21 | 2010-06-16 | 西安电子科技大学 | Segmented current-steering digital-to-analog converter |
| CN104052491B (en) * | 2014-06-25 | 2017-03-15 | 中国电子科技集团公司第五十八研究所 | Digital to analog converter |
| CN109639276B (en) * | 2018-11-23 | 2022-12-02 | 华中科技大学 | Double-time-interleaved current-steering DAC with DRRZ correction function |
| CN109672444B (en) * | 2018-12-19 | 2022-12-23 | 南京国博电子股份有限公司 | Ultra-high-speed digital-to-analog converter with multi-channel clock interweaving |
| CN111256849B (en) * | 2020-02-24 | 2021-11-23 | 苏州迅芯微电子有限公司 | Thermometer decoding structure applied to high-speed DAC circuit |
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| CN102332922A (en) * | 2011-07-25 | 2012-01-25 | 复旦大学 | Current source and drive circuit for improving high frequency characteristic of digital analog converter |
| WO2021258949A1 (en) * | 2020-06-22 | 2021-12-30 | 东南大学 | Current steering digital-to-analog converter based on hybrid coding |
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