CN115019718A - GOA circuit and display panel - Google Patents
GOA circuit and display panel Download PDFInfo
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- CN115019718A CN115019718A CN202210794633.9A CN202210794633A CN115019718A CN 115019718 A CN115019718 A CN 115019718A CN 202210794633 A CN202210794633 A CN 202210794633A CN 115019718 A CN115019718 A CN 115019718A
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- 101100069049 Caenorhabditis elegans goa-1 gene Proteins 0.000 abstract description 7
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
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Abstract
In the GOA circuit and the display panel provided in the embodiments of the present application, the first bootstrap capacitor and the second bootstrap capacitor are disposed in the level pass module. First, when the GOA1:2 output architecture outputs the scan signal, the second scan signal of the current stage is not coupled by the pull-up of the first scan signal of the current stage, so that the second scan signal of the current stage is coupled from the normal high potential to a higher potential, thereby the phenomenon of abnormal charging in the plane is not generated, and the normal display of the display panel is not affected. Secondly, the risk that the first node is coupled to the high potential more quickly can be reduced, so that the possibility of abnormal output of the first scanning signal at the current stage is reduced, the stability of the GOA circuit is improved, and normal display of the display panel is facilitated. In addition, the GOA circuit provided by the embodiment of the application can adopt the one-level GOA circuit to drive two lines of pixels, thereby being beneficial to the narrow frame design of the display panel.
Description
Technical Field
The application relates to the technical field of display, in particular to a GOA circuit and a display panel.
Background
At present, the Gate driving circuit is integrated on the Array substrate of the display panel by the GOA (Gate Driver on Array, chinese) technology, so that the Gate driving integrated circuit part can be omitted, the product cost can be reduced from two aspects of material cost and manufacturing process, and the display panel is more suitable for manufacturing narrow-frame display products.
At present, in order to realize a narrow frame, a GOA1:2 output architecture is generally adopted, and in the conventional GOA1:2 output architecture, a bootstrap capacitor is generally disposed in a pull-up module region. Therefore, when the GOA1:2 output structure outputs the scan signal, the second scan signal G (n +1) of the current stage is coupled incorrectly due to the pull-up of the first scan signal G (n), which causes the second scan signal G (n +1) of the current stage to be coupled from the normal high potential to the higher potential, thereby causing the abnormal charging in the plane and affecting the normal display of the display panel. In addition, the width and length of the conventional level pass thin film transistor are small, so that the pull-up thin film transistor generates negative bias and electric leakage, the first node is coupled to a high potential more quickly, the pull-up thin film transistor is in abnormal open risk, the first scanning signal G (n) of the level is output abnormally, the stability of the GOA circuit is affected, and the normal display of the display panel is affected.
Therefore, how to provide a GOA circuit to realize a narrow frame on the basis of ensuring normal display of a display panel is a difficult problem for existing panel manufacturers to try to overcome.
Disclosure of Invention
An object of the embodiment of the application is to provide a GOA circuit and a display panel, which can solve the technical problem that the conventional GOA circuit cannot realize a narrow frame on the basis of ensuring normal display of the display panel.
The embodiment of the application provides a GOA circuit, includes: cascaded multistage GOA circuit sharing unit, each grade GOA circuit sharing unit all includes: the device comprises a pull-up control module, a stage transmission module, an output module, a pull-down maintaining module, an inverter module, a first bootstrap capacitor and a second bootstrap capacitor;
the first pull-up control module is used for pulling up the potential of the first node to the potential of the reference high level under the control of the upper-stage first-stage transmission signal;
the stage transmission module is connected with a first clock signal and a second clock signal and is electrically connected to the first node, and the stage transmission module is used for outputting a first stage transmission signal and a second stage transmission signal under the potential control of the first node;
the output module is connected to a first clock signal and a second clock signal and is electrically connected to the first node, and the output module is used for outputting a first scanning signal of the current stage and a second scanning signal of the current stage under the potential control of the first node;
the pull-down module is connected to a pull-down signal and a reference low level signal and is electrically connected to a first node, and the pull-down module is used for pulling down the potential of the first node to the potential of the reference low level under the control of the pull-down signal;
the first pull-down maintaining module is connected to the reference low-level signal and electrically connected to the first node and the second node, and the first pull-down maintaining module is configured to maintain the potentials of the first node, the current-stage first scanning signal and the current-stage second scanning signal at the potential of the reference low-level signal under the control of the potential of the second node;
the first inverter module is connected to a first low-frequency clock signal and is electrically connected to the first node and the second node, and the first inverter module is used for maintaining the potential of the first node and the potential of the second node to be inverted;
one end of the first bootstrap capacitor is electrically connected to the first node, the other end of the first bootstrap capacitor is electrically connected to the current-stage first scanning signal, one end of the second bootstrap capacitor is electrically connected to the first node, and the other end of the second bootstrap capacitor is electrically connected to the current-stage second scanning signal.
In the GOA driving circuit of the present application, the pull-up control module includes a pull-up control thin film transistor, a gate of the pull-up control thin film transistor is connected to the previous first level transmission signal, one of a source and a drain of the pull-up control thin film transistor is connected to the reference high level signal, and the other of the source and the drain of the pull-up control thin film transistor is electrically connected to the first node.
In the GOA driving circuit of the present application, the gate of the first level transmission thin film transistor is electrically connected to the first node, one of the source and the drain of the first level transmission thin film transistor is connected to the first clock signal, the other of the source and the drain of the first level transmission thin film transistor is connected to the first level transmission signal, the gate of the second level transmission thin film transistor is electrically connected to the first node, the one of the source and the drain of the second level transmission thin film transistor is connected to the second clock signal, and the other of the source and the drain of the second level transmission thin film transistor is connected to the second level transmission signal.
In the GOA driving circuit of the present application, the output module includes a first output thin film transistor and a second output thin film transistor, a gate of the first output thin film transistor is electrically connected to the first node, one of a source and a drain of the first output thin film transistor is connected to the first clock signal, the other of the source and the drain of the first output thin film transistor is connected to the first scanning signal of the present stage, a gate of the second output thin film transistor is electrically connected to the first node, one of the source and the drain of the second output thin film transistor is connected to the second clock signal, and the other of the source and the drain of the second output thin film transistor is connected to the second scanning signal of the present stage.
In the GOA driving circuit of the present application, the pull-down module includes a first pull-down thin film transistor, a gate of the first pull-down thin film transistor is connected to the pull-down signal, one of a source and a drain of the first pull-down thin film transistor is connected to the reference low level signal, and the other of the source and the drain of the first pull-down thin film transistor is electrically connected to the first node.
In the GOA driving circuit of the present application, the pull-down module further accesses to a next-stage first-stage transmission signal, and the pull-down module is further configured to pull down the potential of the first node to the potential of the reference low level under the control of the next-stage first-stage transmission signal.
In the GOA driving circuit of the present application, the pull-down module further includes a second pull-down thin film transistor, a gate of the second pull-down thin film transistor is connected to the next-stage first-stage transmission signal, one of a source and a drain of the second pull-down thin film transistor is connected to the reference low level signal, and the other of the source and the drain of the second pull-down thin film transistor is electrically connected to the first node.
In the GOA driving circuit of the present application, the first inverter module includes a first inverter thin film transistor, a second inverter thin film transistor, a third inverter thin film transistor, and a fourth inverter thin film transistor, the gate of the first inverter thin film transistor is connected to the first low frequency clock signal, one of the source and the drain of the first inverter thin film transistor is connected to the first low frequency clock signal, the other of the source and the drain of the first inverter thin film transistor is electrically connected to a third node, the gate of the second inverter thin film transistor is electrically connected to the first node, one of the source and the drain of the second inverter thin film transistor is connected to the reference low level signal, the other of the source and the drain of the second inverter thin film transistor is electrically connected to the third node, and the gate of the third inverter thin film transistor is electrically connected to the third node, one of a source and a drain of the third inverted thin film transistor is connected to the first low-frequency clock signal, the other of the source and the drain of the third inverted thin film transistor is electrically connected to the second node, a gate of the fourth inverted thin film transistor is connected to the first node, one of the source and the drain of the fourth inverted thin film transistor is electrically connected to the second node, and the other of the source and the drain of the fourth inverted thin film transistor is connected to the reference low-level signal.
In the GOA driving circuit of the present application, the first pull-down sustain module includes a first pull-down sustain thin film transistor, a second pull-down sustain thin film transistor, and a third pull-down sustain thin film transistor, the gate of the first pull-down sustain thin film transistor is electrically connected to the second node, one of the source and the drain of the first pull-down sustain thin film transistor is connected to the reference low level signal, the other of the source and the drain of the first pull-down sustain thin film transistor is electrically connected to the first node, the gate of the second pull-down sustain thin film transistor is electrically connected to the second node, one of the source and the drain of the second pull-down sustain thin film transistor is connected to the reference low level signal, and the other of the source and the drain of the second pull-down sustain thin film transistor is connected to the current-stage first scan signal, the gate of the third pull-down maintaining thin film transistor is electrically connected to the second node, one of the source and the drain of the third pull-down maintaining thin film transistor is connected to the reference low level signal, and the other of the source and the drain of the third pull-down maintaining thin film transistor is connected to the present-stage second scanning signal.
In the GOA driving circuit of the present application, the first pull-down sustain module includes a fourth pull-down sustain thin film transistor, a gate of the fourth pull-down sustain thin film transistor is electrically connected to the second node, one of a source and a drain of the fourth pull-down sustain thin film transistor is connected to the reference low level signal, and the other of the source and the drain of the fourth pull-down sustain thin film transistor is electrically connected to the first node and connected to the current-stage first scan signal and the current-stage second scan signal.
In the GOA driving circuit of the present application, the GOA circuit sharing unit further includes a second inverter module and a second pull-down maintaining module, the second inverter module is connected to a second low frequency clock signal, and electrically connected to the first node and the fourth node, the second inverter module is used for maintaining the potential of the first node and the potential of the fourth node in opposite phases, the second pull-down maintaining module accesses the reference low level signal, the present-stage first scan signal and the present-stage second scan signal, and the second pull-down maintaining module is configured to maintain the potentials of the first node, the current-stage first scan signal, and the current-stage second scan signal at the potential of the reference low-level signal under the control of the potential of the fourth node.
In the GOA driving circuit of the present application, the second inverter module includes a fifth inverter thin film transistor, a sixth inverter thin film transistor, a seventh inverter thin film transistor, and an eighth inverter thin film transistor, the gate of the fifth inverter thin film transistor is connected to the second low frequency clock signal, one of the source and the drain of the fifth inverter thin film transistor is connected to the second low frequency clock signal, the other of the source and the drain of the fifth inverter thin film transistor is electrically connected to a fifth node, the gate of the sixth inverter thin film transistor is electrically connected to the first node, one of the source and the drain of the sixth inverter thin film transistor is connected to the reference low level signal, the other of the source and the drain of the sixth inverter thin film transistor is electrically connected to the fifth node, and the gate of the seventh inverter thin film transistor is electrically connected to the fifth node, one of a source and a drain of the seventh inverting thin film transistor is connected to the second low-frequency clock signal, the other of the source and the drain of the seventh inverting thin film transistor is electrically connected to the fourth node, a gate of the eighth inverting thin film transistor is connected to the first node, one of the source and the drain of the eighth inverting thin film transistor is electrically connected to the fourth node, and the other of the source and the drain of the eighth inverting thin film transistor is connected to the reference low-level signal.
In the GOA driving circuit of the present application, the second pull-down sustain module includes a fifth pull-down sustain thin film transistor, a sixth pull-down sustain thin film transistor, and a seventh pull-down sustain thin film transistor, a gate of the fifth pull-down sustain thin film transistor is electrically connected to the fourth node, one of a source and a drain of the fifth pull-down sustain thin film transistor is connected to the reference low level signal, the other of the source and the drain of the fifth pull-down sustain thin film transistor is electrically connected to the first node, a gate of the sixth pull-down sustain thin film transistor is electrically connected to the fourth node, one of the source and the drain of the sixth pull-down sustain thin film transistor is connected to the reference low level signal, and the other of the source and the drain of the sixth pull-down sustain thin film transistor is connected to the current-stage first scan signal, a gate of the seventh pull-down maintaining thin film transistor is electrically connected to the fourth node, one of a source and a drain of the seventh pull-down maintaining thin film transistor is connected to the reference low level signal, and the other of the source and the drain of the seventh pull-down maintaining thin film transistor is connected to the current-stage second scanning signal.
In the GOA driving circuit of the present application, the second pull-down sustain module includes an eighth pull-down sustain thin film transistor, a gate of the eighth pull-down sustain thin film transistor is electrically connected to the fourth node, one of a source and a drain of the eighth pull-down sustain thin film transistor is connected to the reference low level signal, and the other of the source and the drain of the eighth pull-down sustain thin film transistor is electrically connected to the first node and connected to the current-stage first scan signal and the current-stage second scan signal.
The embodiment of the present application further provides a display panel, where the display panel includes a display area and a non-display area surrounding the display area, and the non-display area is integrated with the GOA circuit.
The GOA circuit and the display panel provided in the embodiments of the present application include a pull-up control module, a level pass module, an output module, a pull-down maintaining module, an inverter module, a first bootstrap capacitor, and a second bootstrap capacitor. The first bootstrap capacitor and the second bootstrap capacitor provided in the embodiments of the present application are disposed in the stage transfer module. First, when the GOA1:2 output architecture outputs the scan signal, the second scan signal of the current stage is not coupled by the pull-up of the first scan signal of the current stage, so that the second scan signal of the current stage is coupled from the normal high potential to a higher potential, thereby the phenomenon of abnormal charging in the plane is not generated, and the normal display of the display panel is not affected. Secondly, the risk that the first node is coupled to the high potential more quickly can be reduced, so that the possibility of abnormal output of the first scanning signal at the current stage is reduced, the stability of the GOA circuit is improved, and normal display of the display panel is facilitated. In addition, the GOA circuit provided by the embodiment of the application can adopt the one-level GOA circuit to drive two lines of pixels, thereby being beneficial to the narrow frame design of the display panel.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a GOA circuit according to an embodiment of the present disclosure.
Fig. 2 is a schematic structural diagram of a first implementation of a GOA unit in a GOA circuit according to an embodiment of the present disclosure.
Fig. 3 is a circuit diagram illustrating a first implementation of a GOA unit in a GOA circuit according to an embodiment of the present disclosure.
Fig. 4 is a schematic structural diagram of a second implementation of a GOA unit in a GOA circuit according to an embodiment of the present disclosure.
Fig. 5 is a circuit diagram illustrating a second implementation manner of a GOA unit in a GOA circuit according to an embodiment of the present disclosure.
Fig. 6 is a schematic structural diagram of a third implementation of a GOA unit in a GOA circuit according to an embodiment of the present disclosure.
Fig. 7 is a first circuit diagram of a third implementation of a GOA unit in a GOA circuit according to an embodiment of the present disclosure.
Fig. 8 is a second circuit diagram of a third implementation of a GOA unit in a GOA circuit according to an embodiment of the present disclosure.
Fig. 9 is a timing diagram of signals of a GOA unit in the GOA circuit according to the embodiment of the present disclosure.
Fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The transistors used in all embodiments of the present application may be thin film transistors or field effect transistors or other devices with the same characteristics, and since the source and drain of the transistors used herein are symmetrical, the source and drain may be interchanged. In the embodiment of the present application, to distinguish two poles of a transistor except for a gate, one of the two poles is referred to as a source, and the other pole is referred to as a drain. The form in the drawing provides that the middle end of the switching transistor is a grid, the signal input end is a source, and the output end is a drain. In addition, the transistors used in the embodiments of the present application are N-type transistors, wherein the N-type transistors are turned on when the gates are at a high level and turned off when the gates are at a low level.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a GOA circuit according to an embodiment of the present disclosure. As shown in fig. 1, the GOA circuit provided in the embodiment of the present application includes multiple cascaded GOA units. Fig. 1 illustrates an N-1 level GOA unit, an nth level GOA unit, and an N +1 level GOA unit in cascade.
When the Nth-level GOA unit works, the scanning signal output by the Nth-level GOA unit is at a high potential and is used for turning on a transistor switch of each pixel in a row in a display panel and charging a pixel electrode in each pixel through a data signal; the Nth-level signal is used for controlling the work of the (N +1) th-level GOA unit; when the N +1 th-level GOA unit works, the scanning signal output by the N +1 th-level GOA unit is at a high potential, and the scanning signal output by the nth-level GOA unit is at a low potential.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a GOA unit in a GOA circuit according to an embodiment of the present disclosure. As shown in fig. 2, the GOA unit includes: the pull-up control module 101, the stage pass module 102, the output module 103, the pull-down module 104, the first pull-down maintaining module 105, and the first inverter module 106.
The pull-up control module 101 is connected to the first-level transmission signal ST (n-4) and the reference high-level signal VGH, and is electrically connected to the first node P, and the pull-up control module 101 is configured to pull up a potential of the first node P to a potential of the reference high-level signal VGH under the control of the first-level transmission signal ST (n-4).
The level pass module 102 is coupled to the first clock signal Ck (n) and the second clock signal Ck (n +1) and electrically connected to the first node P, and the level pass module 102 is configured to output a level first level pass signal ST (n) and a level second level pass signal ST (n +1) under the control of a potential of the first node P.
The output module 103 is coupled to the first clock signal Ck (n) and the second clock signal Ck (n +1) and electrically connected to the first node P, and the output module 103 is configured to output the first scanning signal G (n) and the second scanning signal G (n +1) under the control of the potential of the first node P.
The pull-down module 104 is connected to the pull-down signal CLR and the reference low level signal VGL, and is electrically connected to the first node P, and the pull-down module 104 is configured to pull down a potential of the first node P to a potential of the reference low level signal VGL under the control of the pull-down signal CLR.
The first pull-down maintaining module 105 is connected to the reference low level signal VGL and electrically connected to the first node P and the second node Q, and the first pull-down maintaining module 105 is configured to maintain the potentials of the first node P, the current-stage first scan signal G (n) and the current-stage second scan signal G (n +1) at the reference low level signal VGL under the control of the potential of the second node Q.
The first inverter module 106 is electrically connected to the first node P and the second node Q, and the first inverter module 106 is connected to the first low frequency clock signal LC 1. The first inverter module 106 is used for maintaining the potential of the second node Q and the potential of the first node P in an inverted state.
The GOA circuit sharing unit further includes a first bootstrap capacitor Cst1 and a second bootstrap capacitor Cst 2. One end of the first bootstrap capacitor Cst1 is electrically connected to the first node P, and the other end of the first bootstrap capacitor Cst1 is electrically connected to the current-stage first scan signal g (n). One end of the second bootstrap capacitor Cst2 is electrically connected to the first node P, and the other end of the second bootstrap capacitor Cst2 is electrically connected to the current-stage second scan signal G (n + 1).
It should be noted that the first bootstrap capacitor Cst1 and the second bootstrap capacitor Cst2 of the GOA circuit provided in the embodiment of the present application are disposed in the stage transmission module 102. First, when the GOA1:2 output architecture outputs the scan signal, the second scan signal G (n +1) of the current stage is not coupled by the pull-up of the first scan signal G (n) of the current stage, which causes the second scan signal G (n +1) of the current stage to be coupled from the normal high potential to the higher potential, so that the phenomenon of abnormal charging in the plane is not generated, and the normal display of the display panel is not affected. Secondly, the risk that the first node P is coupled to the high potential more quickly can be reduced, so that the possibility of abnormal output of the first scanning signal g (n) at the current stage is reduced, the stability of the GOA circuit is improved, and normal display of the display panel is facilitated.
In addition, the GOA circuit provided by the embodiment of the application can adopt the one-level GOA circuit to drive two lines of pixels, thereby being beneficial to the narrow frame design of the display panel.
Referring to fig. 3, fig. 3 is a circuit diagram illustrating a first implementation manner of a GOA unit in a GOA circuit according to an embodiment of the present disclosure. As shown in fig. 3, the pull-up control module 101 includes a pull-up tft T11, the gate of the pull-up tft T11 is connected to the previous-stage first-stage transmission signal ST (n-4), one of the source and the drain of the pull-up tft T11 is connected to the reference high-level signal VGH, and the other of the source and the drain of the pull-up tft T11 is electrically connected to the first node P.
The cascode module 102 includes a first cascode tft T21 and a second cascode tft T22. The gate of the first-level pass tft T21 is electrically connected to the first node P, one of the source and the drain of the first-level pass tft T21 is connected to the first clock signal ck (n), and the other of the source and the drain of the first-level pass tft T21 is connected to the current-level first-level pass signal st (n). The gate of the second pass thin film transistor T22 is electrically connected to the first node P, one of the source and the drain of the second pass thin film transistor T22 is connected to the second clock signal Ck (n +1), and the other of the source and the drain of the second pass thin film transistor T22 is connected to the current pass second signal ST (n + 1).
The first output module 103 includes a first output thin film transistor T31 and a second output thin film transistor T32. The gate of the first output thin film transistor T31 is connected to the first node P, one of the source and the drain of the first output thin film transistor T31 is connected to the first clock signal ck (n), and the other of the source and the drain of the first output thin film transistor T31 is connected to the current-stage first scan signal g (n). The gate of the second output thin film transistor T32 is connected to the first node P, one of the source and the drain of the second output thin film transistor T32 is connected to the second clock signal Ck (n +1), and the other of the source and the drain of the second output thin film transistor T32 is connected to the present-stage second scan signal G (n + 1).
The pull-down module 104 includes a first pull-down thin film transistor T41. The gate of the first pull-down thin film transistor T41 is connected to the pull-down signal CLR, one of the source and the drain of the first pull-down thin film transistor T41 is connected to the reference low level signal VGL, and the other of the source and the drain of the first pull-down thin film transistor T41 is electrically connected to the first node P.
The first inverter module 106 includes a first inverter thin film transistor T51, a second inverter thin film transistor T52, a third inverter thin film transistor T53, and a fourth inverter thin film transistor T54. The gate of the first inversion thin film transistor T51 is connected to the first low-frequency clock signal LC1, one of the source and the drain of the first inversion thin film transistor T51 is connected to the first low-frequency clock signal LC1, and the other of the source and the drain of the first inversion thin film transistor T51 is electrically connected to the third node M. The gate of the second inversion thin film transistor T52 is electrically connected to the first node P, one of the source and the drain of the second inversion thin film transistor T52 is connected to the reference low level signal VGL, and the other of the source and the drain of the second inversion thin film transistor T52 is electrically connected to the third node M. The gate of the third inverted thin film transistor T53 is electrically connected to the third node M, one of the source and the drain of the third inverted thin film transistor T53 is connected to the first low frequency clock signal LC1, and the other of the source and the drain of the third inverted thin film transistor T53 is electrically connected to the second node Q. A gate of the fourth inversion thin film transistor T54 is connected to the first node P, one of a source and a drain of the fourth inversion thin film transistor T54 is electrically connected to the second node Q, and the other of the source and the drain of the fourth inversion thin film transistor T54 is connected to the reference low signal VGL.
The first pull-down sustain module 105 includes a first pull-down sustain thin film transistor T61, a second pull-down sustain thin film transistor T62, and a third pull-down sustain thin film transistor T63. The gate of the first pull-down sustain thin film transistor T61 is electrically connected to the second node Q, one of the source and the drain of the first pull-down sustain thin film transistor T61 is connected to the reference low level signal VGL, and the other of the source and the drain of the first pull-down sustain thin film transistor T61 is electrically connected to the first node P. The gate of the second pull-down sustain thin film transistor T62 is electrically connected to the second node Q, one of the source and the drain of the second pull-down sustain thin film transistor T62 is connected to the reference low level signal VGL, and the other of the source and the drain of the second pull-down sustain thin film transistor T62 is connected to the current-stage first scan signal g (n). The gate of the third pull-down sustain thin film transistor T63 is electrically connected to the second node Q, one of the source and the drain of the third pull-down sustain thin film transistor T63 is connected to the reference low level signal VGL, and the other of the source and the drain of the third pull-down sustain thin film transistor T63 is connected to the present-stage second scan signal G (n + 1).
Specifically, referring to fig. 4, fig. 4 is a schematic structural diagram of a second embodiment of a GOA unit in a GOA circuit according to an embodiment of the present disclosure. As shown in fig. 4, the first pull-down module 104 further receives the next-stage first level signal ST (n +6), and the first pull-down module 104 is further configured to pull down the potential of the first node P to the potential of the reference low-level signal VGL under the control of the next-stage second level signal ST (n + 6).
Specifically, referring to fig. 5, fig. 5 is a circuit diagram illustrating a second implementation of a GOA unit in a GOA circuit according to an embodiment of the present disclosure. As shown in fig. 5, the pull-down module 104 further includes a second pull-down thin film transistor T42, a gate of the second pull-down thin film transistor T42 is connected to the second-stage first-stage signal ST (n +6), one of a source and a drain of the second pull-down thin film transistor T42 is connected to the first reference low-level signal VGL, and the other of the source and the drain of the second pull-down thin film transistor T42 is electrically connected to the first node P.
In the pull-down module 104 according to the embodiment of the present disclosure, the first pull-down thin film transistor T41 and the second pull-down thin film transistor T42 are asymmetric to pull down the potential of the first node P to the potential of the reference low level signal VGL.
It should be noted that, since the GOA circuit provided in the embodiments of the present application is applied to a large-sized high-definition narrow-bezel display panel, the required load capacity is also large when pulling down. First, the pull-down module provided in the embodiment of the present application uses two asymmetric pull-down thin film transistors to perform a pull-down operation, so as to avoid a technical problem of insufficient load. Second, when the pull-down module provided in the embodiment of the present application performs pull-down by using two asymmetric pull-down thin film transistors, two pull-down processes need to be performed, so that the phenomenon that some nodes and signals are not pulled down to a preset value can be avoided. Thirdly, the pull-down module that this application embodiment provided adopts two kinds of asymmetric pull-down thin film transistors to carry out the pull-down operation, and it compares with the pull-down module adopts a pull-down thin film transistor to carry out the pull-down operation, and pull-down thin film transistor's size can set up littleer to be favorable to the design of the narrow frame of display panel.
Specifically, referring to fig. 6, fig. 6 is a schematic structural diagram of a third implementation of a GOA unit in a GOA circuit according to an embodiment of the present disclosure. As shown in fig. 6, the GOA circuit sharing unit further includes a second inverter module 107 and a second pull-down maintaining module 108. The second inverter module 107 is coupled to the second low frequency clock signal LC2 and electrically connected to the first node P and the fourth node N, the second inverter module 107 is configured to maintain the voltage level of the first node P and the voltage level of the fourth node N to be inverted, and the second pull-down maintaining module 108 is coupled to the reference low level signal VGL, the current-level first scan signal G (N) and the current-level second scan signal G (N +1) and electrically connected to the first node P and the fourth node N. The second pull-down maintaining module 108 is used for maintaining the potentials of the first node P, the current stage first scan signal G (N) and the current stage second scan signal G (N +1) at the potential of the reference low level signal VGL under the control of the potential of the fourth node N.
Specifically, referring to fig. 7, fig. 7 is a first circuit diagram of a third implementation of a GOA unit in a GOA circuit according to an embodiment of the present disclosure. As shown in the figure 7 of the drawings,
the second inverter module 107 includes a fifth inverter thin film transistor T55, a sixth inverter thin film transistor T56, a seventh inverter thin film transistor T57, and an eighth inverter thin film transistor T58. The gate of the fifth inversion thin film transistor T55 is connected to the second low frequency clock signal LC2, one of the source and the drain of the fifth inversion thin film transistor T55 is connected to the second low frequency clock signal LC2, and the other of the source and the drain of the fifth inversion thin film transistor T55 is electrically connected to the fifth node S. The gate of the sixth inversion thin film transistor T56 is electrically connected to the first node P, one of the source and the drain of the sixth inversion thin film transistor T56 is connected to the reference low level signal VGL, and the other of the source and the drain of the sixth inversion thin film transistor T56 is electrically connected to the fifth node S. The gate of the seventh inverting thin film transistor T57 is electrically connected to the fifth node S, one of the source and the drain of the seventh inverting thin film transistor T57 is connected to the second low frequency clock signal LC2, and the other of the source and the drain of the seventh inverting thin film transistor T57 is electrically connected to the fourth node N. The gate of the eighth inverted thin film transistor T58 is connected to the first node P, one of the source and the drain of the eighth inverted thin film transistor T58 is electrically connected to the fourth node N, and the other of the source and the drain of the eighth inverted thin film transistor T58 is connected to the reference low signal VCL.
The second pull-down sustain module 108 includes a fifth pull-down sustain thin film transistor T65, a sixth pull-down sustain thin film transistor T66, and a seventh pull-down sustain thin film transistor T67. The gate of the fifth pull-down maintaining thin film transistor T65 is electrically connected to the fourth node N, and one of the source and the drain of the fifth pull-down maintaining thin film transistor T65 is connected to the reference low level signal VGL. The other of the source and the drain of the fifth pull-down maintaining thin film transistor T65 is electrically connected to the first node P. The gate of the sixth pull-down sustain thin film transistor T66 is electrically connected to the fourth node N, one of the source and the drain of the sixth pull-down sustain thin film transistor T66 is connected to the reference low level signal VGL, and the other of the source and the drain of the sixth pull-down sustain thin film transistor T66 is connected to the current-stage first scan signal g (N). The gate of the seventh pull-down sustain tft T67 is electrically connected to the fourth node N, one of the source and the drain of the seventh pull-down sustain tft T67 is connected to the reference low level signal VGL, and the other of the source and the drain of the seventh pull-down sustain tft T67 is connected to the current-stage second scan signal g (N).
Each pull-down maintaining thin film transistor provided by the embodiment of the application is connected with a node or a signal and is used for maintaining the low potential of the node or the signal. It should be noted that, by the above arrangement, all nodes and signals can be guaranteed to maintain the required low potential, so that the phenomenon of signal confusion is avoided, and the stability of the GOA circuit is improved. In addition, the application provides two pull-down maintaining modules for ensuring that all nodes and signals maintain required low potential, so that the phenomenon of signal disorder is avoided, and the stability of the GOA circuit is improved.
Specifically, referring to fig. 8, fig. 8 is a second circuit diagram of a third implementation of a GOA unit in a GOA circuit according to an embodiment of the present disclosure. As shown in figure 8 of the drawings,
the first pull-down sustain module 105 includes a fourth pull-down sustain thin film transistor T64, a gate of the fourth pull-down sustain thin film transistor T64 is electrically connected to the second node Q, one of a source and a drain of the fourth pull-down sustain thin film transistor T64 is connected to the reference low level signal VGL, and the other of the source and the drain of the fourth pull-down sustain thin film transistor T64 is electrically connected to the first node P and is connected to the current-stage first scan signal G (n) and the current-stage second scan signal G (n + 1).
The second pull-down maintaining module 108 includes an eighth pull-down maintaining thin film transistor T68, a gate of the eighth pull-down maintaining thin film transistor T68 is electrically connected to the fourth node N, one of a source and a drain of the eighth pull-down maintaining thin film transistor T68 is connected to the reference low level signal VGL, and the other of the source and the drain of the eighth pull-down maintaining thin film transistor T68 is electrically connected to the first node P and is connected to the current-stage first scanning signal G (N) and the current-stage second scanning signal G (N + 1).
It should be noted that, one pull-down maintaining thin film transistor provided in the embodiment of the present application may maintain low potentials of multiple signals or nodes, so as to reduce the number of pull-down maintaining thin film transistors, and further reduce the occupied space of the GOA circuit, which is beneficial to the design of a narrow frame of a display panel.
Specifically, referring to fig. 9, fig. 9 is a timing diagram of a signal of a GOA unit in the GOA circuit according to the embodiment of the present disclosure.
In the first clock period t1, the pull-up control module 101 pulls up the potential of the first node P, so that the stage transmission module 102 and the output module 103 are turned on, because the first clock signal Ck (n) and the second clock signal Ck (n +1) are both low potential, the first scan signal G (n), the second scan signal G (n +1), the first stage transmission signal ST (n), and the second stage transmission signal ST (n +1) are both low potential.
In the second clock period t2, the pull-up control module 101 is turned off, the first node P keeps high, and the first clock signal Ck (n) and the second clock signal Ck (n +1) become high sequentially, so that the current stage first scan signal G (n), the current stage second scan signal G (n +1), the current stage first stage transmission signal ST (n) and the current stage second stage transmission signal ST (n +1) are high. At this stage, the first scanning signal g (n) at the current stage is at a high level, so that the scanning line corresponding to the first scanning signal g (n) at the current stage is charged, a row of pixels requiring the scanning line corresponding to the first scanning signal g (n) at the current stage to provide the scanning signal is turned on, and the pixels at the row are turned on. The current-stage second scan signal G (n +1) is at a high potential, so that the scan line corresponding to the current-stage second scan signal G (n +1) is charged, and a row of pixels requiring the scan line corresponding to the current-stage second scan signal G (n +1) to provide the scan signal is turned on, and the row of pixels is turned on.
Meanwhile, in this stage, since the current-stage first-stage transmission signal ST (n) is at a high potential, the potential of the first node P is further pulled up by the first bootstrap capacitor Cst1, and since the current-stage second-stage transmission signal ST (n +1) is at a high potential, the potential of the first node P is further pulled up by the second bootstrap capacitor Cst2, so as to ensure that the output current-stage first scanning signal G (n) and the output current-stage second scanning signal G (n +1) are at a high potential, and thus, the abnormal current-stage first-stage transmission signal ST (n) and the abnormal current-stage second-stage transmission signal ST (n +1) are prevented from being input into the plane during the coupling process.
In the fourth clock period t4, the pull-down module 104 pulls down the potential of the first node P to the low potential twice, and after the potential of the first node P is the low potential, the potentials of the second node Q and the fourth node N become high due to the existence of the first inverter module 106 and the second inverter module 107, so that the first pull-down maintaining module 105 and the second pull-down maintaining module 108 maintain the potentials of the first node P, the current-stage first scan signal G (N) and the current-stage second scan signal G (N +1) to be the low potential.
The first inverter module 106 and the first pull-down sustain module 105 form a group, and the second inverter module 107 form a group. And two groups work in succession to ensure the stability of the GOA circuit.
The GOA circuit provided in the embodiments of the present application includes a pull-up control module, a stage pass module, an output module, a pull-down maintaining module, an inverter module, a first bootstrap capacitor, and a second bootstrap capacitor. The first bootstrap capacitor and the second bootstrap capacitor provided in the embodiments of the present application are disposed in the stage transfer module. First, when the GOA1:2 output architecture outputs the scan signal, the second scan signal of the current stage is not coupled by the pull-up of the first scan signal of the current stage, so that the second scan signal of the current stage is coupled from the normal high potential to a higher potential, thereby the phenomenon of abnormal charging in the plane is not generated, and the normal display of the display panel is not affected. And secondly, the risk that the first node is coupled to the high potential more quickly can be reduced, so that the possibility of abnormal output of the first scanning signal at the current stage is reduced, the stability of the GOA circuit is improved, and normal display of the display panel is facilitated. In addition, the GOA circuit provided by the embodiment of the application can adopt the one-level GOA circuit to drive two lines of pixels, thereby being beneficial to the narrow frame design of the display panel.
Referring to fig. 10, fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure. The embodiment of the present application further provides a display panel 100, where the display panel 100 includes a display area 100a and a non-display area 100b disposed around the display area 100a, where the non-display area 100b is integrated with the GOA circuit 10, and the description of the GOA circuit 10 may be specifically referred to above for the GOA circuit 10, and is not repeated herein.
The foregoing detailed description is directed to a GOA circuit and a display panel provided in the embodiments of the present application, and specific examples are used herein to explain the principles and implementations of the present application, and the description of the embodiments is only for assisting understanding of the method and the core idea of the present application, and is not intended to limit the scope of the present invention, and all equivalent structures or equivalent procedures that are performed by using the contents of the description and the drawings of the present application or are directly or indirectly applied to other related technical fields are encompassed by the scope of the present invention; to sum up, the content of the present specification should not be construed as limiting the present application, since the scope of the application and the detailed description thereof will vary for those skilled in the art according to the spirit of the present application.
Claims (15)
1. A GOA circuit, comprising: cascaded multistage GOA circuit sharing unit, each grade of GOA circuit sharing unit all includes: the device comprises a pull-up control module, a stage transmission module, an output module, a pull-down module, a first pull-down maintaining module, a first inverter module, a first bootstrap capacitor and a second bootstrap capacitor;
the first pull-up control module is used for pulling up the potential of the first node to the potential of the reference high level under the control of the upper-stage first-stage transmission signal;
the stage transmission module is connected with a first clock signal and a second clock signal and is electrically connected to the first node, and the stage transmission module is used for outputting a first stage transmission signal and a second stage transmission signal under the potential control of the first node;
the output module is connected to a first clock signal and a second clock signal and is electrically connected to the first node, and the output module is used for outputting a first scanning signal of the current stage and a second scanning signal of the current stage under the potential control of the first node;
the pull-down module is connected to a pull-down signal and a reference low level signal and is electrically connected to a first node, and the pull-down module is used for pulling down the potential of the first node to the potential of the reference low level under the control of the pull-down signal;
the first pull-down maintaining module is connected to the reference low-level signal and electrically connected to the first node and the second node, and the first pull-down maintaining module is configured to maintain the potentials of the first node, the current-stage first scanning signal and the current-stage second scanning signal at the potential of the reference low-level signal under the control of the potential of the second node;
the first inverter module is connected to a first low-frequency clock signal and is electrically connected to the first node and the second node, and the first inverter module is used for maintaining the potential of the first node and the potential of the second node to be inverted;
one end of the first bootstrap capacitor is electrically connected to the first node, the other end of the first bootstrap capacitor is electrically connected to the current-stage first scanning signal, one end of the second bootstrap capacitor is electrically connected to the first node, and the other end of the second bootstrap capacitor is electrically connected to the current-stage second scanning signal.
2. The GOA circuit of claim 1, wherein the pull-up control module comprises a pull-up control thin film transistor, a gate of the pull-up control thin film transistor is connected to the previous-stage first-stage transmission signal, one of a source and a drain of the pull-up control thin film transistor is connected to the reference high-level signal, and the other of the source and the drain of the pull-up control thin film transistor is electrically connected to the first node.
3. The GOA circuit according to claim 1, wherein the pass-cascade module comprises a first pass thin film transistor and a second pass thin film transistor, a gate of the first pass thin film transistor is electrically connected to the first node, one of a source and a drain of the first pass thin film transistor is connected to the first clock signal, the other of the source and the drain of the first pass thin film transistor is connected to the first pass signal, a gate of the second pass thin film transistor is electrically connected to the first node, one of the source and the drain of the second pass thin film transistor is connected to the first clock signal, and the other of the source and the drain of the second pass thin film transistor is connected to the second pass signal.
4. The GOA circuit of claim 1, wherein the output module comprises a first output thin film transistor and a second output thin film transistor, a gate of the first output thin film transistor is electrically connected to the first node, one of a source and a drain of the first output thin film transistor is connected to the first clock signal, the other of the source and the drain of the first output thin film transistor is connected to the current-stage first scan signal, a gate of the second output thin film transistor is electrically connected to the first node, one of the source and the drain of the second output thin film transistor is connected to the second clock signal, and the other of the source and the drain of the second output thin film transistor is connected to the current-stage second scan signal.
5. The GOA circuit of claim 1, wherein the pull-down module comprises a first pull-down thin film transistor, a gate of the first pull-down thin film transistor is connected to the pull-down signal, one of a source and a drain of the first pull-down thin film transistor is connected to the reference low signal, and the other of the source and the drain of the first pull-down thin film transistor is electrically connected to the first node.
6. The GOA circuit of claim 1, wherein the pull-down module is further coupled to a next-stage first-stage signal, and wherein the pull-down module is further configured to pull down a potential of the first node to a potential of the reference low level under control of the next-stage first-stage signal.
7. The GOA circuit of claim 6, wherein the pull-down module further comprises a second pull-down thin film transistor, a gate of the second pull-down thin film transistor is connected to the next-stage first-stage signal, one of a source and a drain of the second pull-down thin film transistor is connected to the reference low-level signal, and the other of the source and the drain of the second pull-down thin film transistor is electrically connected to the first node.
8. The GOA circuit of claim 1, wherein the first inverter module comprises a first inverter thin film transistor, a second inverter thin film transistor, a third inverter thin film transistor and a fourth inverter thin film transistor, wherein a gate of the first inverter thin film transistor is connected to the first low frequency clock signal, one of a source and a drain of the first inverter thin film transistor is connected to the first low frequency clock signal, the other of the source and the drain of the first inverter thin film transistor is electrically connected to a third node, a gate of the second inverter thin film transistor is electrically connected to the first node, one of the source and the drain of the second inverter thin film transistor is connected to the reference low level signal, and the other of the source and the drain of the second inverter thin film transistor is electrically connected to the third node, the gate of the third inverted thin film transistor is electrically connected to the third node, one of the source and the drain of the third inverted thin film transistor is connected to the first low-frequency clock signal, the other of the source and the drain of the third inverted thin film transistor is electrically connected to the second node, the gate of the fourth inverted thin film transistor is connected to the first node, one of the source and the drain of the fourth inverted thin film transistor is electrically connected to the second node, and the other of the source and the drain of the fourth inverted thin film transistor is connected to the reference low-level signal.
9. The GOA circuit of claim 8, wherein the first pull-down maintaining module comprises a first pull-down maintaining thin film transistor, a second pull-down maintaining thin film transistor and a third pull-down maintaining thin film transistor, wherein a gate of the first pull-down maintaining thin film transistor is electrically connected to the second node, one of a source and a drain of the first pull-down maintaining thin film transistor is connected to the reference low signal, the other of the source and the drain of the first pull-down maintaining thin film transistor is electrically connected to the first node, a gate of the second pull-down maintaining thin film transistor is electrically connected to the second node, one of the source and the drain of the second pull-down maintaining thin film transistor is connected to the reference low signal, and the other of the source and the drain of the second pull-down maintaining thin film transistor is connected to the current-stage first scanning signal, the gate of the third pull-down maintaining thin film transistor is electrically connected to the second node, one of the source and the drain of the third pull-down maintaining thin film transistor is connected to the reference low level signal, and the other of the source and the drain of the third pull-down maintaining thin film transistor is connected to the present-stage second scanning signal.
10. The GOA circuit of claim 8, wherein the first pull-down maintaining module comprises a fourth pull-down maintaining thin film transistor, a gate of the fourth pull-down maintaining thin film transistor is electrically connected to the second node, one of a source and a drain of the fourth pull-down maintaining thin film transistor is connected to the reference low signal, and the other of the source and the drain of the fourth pull-down maintaining thin film transistor is electrically connected to the first node and connected to the current-stage first scanning signal and the current-stage second scanning signal.
11. The GOA circuit of claim 1, wherein the GOA circuit sharing unit further comprises a second inverter module and a second pull-down maintaining module, the second inverter module is connected to a second low frequency clock signal, and electrically connected to the first node and the fourth node, the second inverter module is used for maintaining the potential of the first node and the potential of the fourth node in opposite phases, the second pull-down maintaining module accesses the reference low level signal, the present-stage first scan signal and the present-stage second scan signal, and the second pull-down maintaining module is configured to maintain the potentials of the first node, the current-stage first scan signal, and the current-stage second scan signal at the potential of the reference low-level signal under the control of the potential of the fourth node.
12. The GOA circuit of claim 11, wherein the second inverter module comprises a fifth inverting thin film transistor, a sixth inverting thin film transistor, a seventh inverting thin film transistor and an eighth inverting thin film transistor, wherein the gate of the fifth inverting thin film transistor is connected to the second low-frequency clock signal, one of the source and the drain of the fifth inverting thin film transistor is connected to the second low-frequency clock signal, the other of the source and the drain of the fifth inverting thin film transistor is electrically connected to a fifth node, the gate of the sixth inverting thin film transistor is electrically connected to the first node, one of the source and the drain of the sixth inverting thin film transistor is connected to the reference low-level signal, and the other of the source and the drain of the sixth inverting thin film transistor is electrically connected to the fifth node, the gate of the seventh inverted thin film transistor is electrically connected to the fifth node, one of the source and the drain of the seventh inverted thin film transistor is connected to the second low-frequency clock signal, the other of the source and the drain of the seventh inverted thin film transistor is electrically connected to the fourth node, the gate of the eighth inverted thin film transistor is connected to the first node, one of the source and the drain of the eighth inverted thin film transistor is electrically connected to the fourth node, and the other of the source and the drain of the eighth inverted thin film transistor is connected to the reference low-level signal.
13. The GOA circuit of claim 12, wherein the second pull-down maintaining module comprises a fifth pull-down maintaining thin film transistor, a sixth pull-down maintaining thin film transistor and a seventh pull-down maintaining thin film transistor, wherein a gate of the fifth pull-down maintaining thin film transistor is electrically connected to the fourth node, one of a source and a drain of the fifth pull-down maintaining thin film transistor is connected to the reference low level signal, the other of the source and the drain of the fifth pull-down maintaining thin film transistor is electrically connected to the first node, a gate of the sixth pull-down maintaining thin film transistor is electrically connected to the fourth node, one of the source and the drain of the sixth pull-down maintaining thin film transistor is connected to the reference low level signal, and the other of the source and the drain of the sixth pull-down maintaining thin film transistor is connected to the present-stage first scanning signal, a gate of the seventh pull-down sustain thin film transistor is electrically connected to the fourth node, one of a source and a drain of the seventh pull-down sustain thin film transistor is connected to the reference low level signal, and the other of the source and the drain of the seventh pull-down sustain thin film transistor is connected to the present-stage second scan signal.
14. The GOA circuit of claim 12, wherein the second pull-down sustain module comprises an eighth pull-down sustain thin film transistor, a gate of the eighth pull-down sustain thin film transistor is electrically connected to the fourth node, one of a source and a drain of the eighth pull-down sustain thin film transistor is connected to the reference low signal, and the other of the source and the drain of the eighth pull-down sustain thin film transistor is electrically connected to the first node and connected to the present-stage first scan signal and the present-stage second scan signal.
15. A display panel comprising a display area and a non-display area disposed around the display area, wherein the non-display area is integrated with the GOA circuit of any one of claims 1 to 14.
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