CN115019712A

CN115019712A - Drive chip and terminal equipment

Info

Publication number: CN115019712A
Application number: CN202111444893.5A
Authority: CN
Inventors: 安亚斌; 苏懿; 贺海明
Original assignee: Honor Device Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2021-11-30
Filing date: 2021-11-30
Publication date: 2022-09-06
Anticipated expiration: 2041-11-30
Also published as: CN115019712B

Abstract

The embodiment of the application provides a driving chip and terminal equipment, and is applied to the technical field of terminals. The output pins of the driving chip are divided into a first class of output pins and a second class of output pins, when the driving chip is applied to a first display panel, a first output pin of the first class of output pins and a second output pin of the second class of output pins are both connected with a fan-out lead of the first display panel, when the driving chip is applied to a second display panel, the first output pin of the first class of output pins is connected with the fan-out lead of the second display panel, and at least part of the second output pins of the second class of output pins are disconnected from the fan-out lead of the second display panel. Therefore, the driving chip can be applied to both the first display panel with high resolution and the second display panel with low resolution, thereby improving the utilization rate of the driving chip and reducing the design cost of the driving chip.

Description

Drive chip and terminal equipment

Technical Field

The application relates to the technical field of terminals, in particular to a driving chip and terminal equipment.

Background

With the continuous development of the information era, terminal devices such as mobile phones and tablet computers become common tools in life and work of people, the terminal devices comprise devices such as a display panel and a driving chip, and the driving chip is used for transmitting corresponding display data to a data line in the display panel.

However, the required driving chips are different for the display panels with different resolutions, which results in a lower utilization rate of the same type of driving chip and an increase in the design cost of the driving chip.

Disclosure of Invention

The embodiment of the application provides a driving chip and a terminal device, so that the utilization rate of the same type of driving chip is improved, and the design cost of the driving chip is reduced.

In a first aspect, an embodiment of the present application provides a driving chip, including: the first-class output pins comprise a plurality of first output pin groups, each first output pin group comprises at least one first output pin, the second-class output pins comprise at least one second output pin group, and each second output pin group comprises at least one second output pin; the first output pin is used for being connected with a fan-out lead of the first display panel or connected with a fan-out lead of the second display panel; the second type output pins are used for being connected with the fan-out leads of the first display panel or being disconnected from at least part of the fan-out leads of the second display panel; the fan-out lead wire in the first display panel is arranged in a serial number which is different from the serial number of the data wire connected with the fan-out lead wire, and the fan-out lead wire in the second display panel is arranged in a serial number which is the same as the serial number of the data wire connected with the fan-out lead wire.

When the driving chip is applied to the second display panel, in one case, all first output pins in the first type of output pins are connected with the fan-out lead of the second display panel, and all second output pins in the second type of output pins are disconnected with the fan-out lead of the second display panel; in another case, all of the first output pins in the first class of output pins are connected to the fan-out lead of the second display panel, a part of the second output pins in the second class of output pins are disconnected from the fan-out lead of the second display panel, and another part of the second output pins in the second class of output pins are connected to the fan-out lead of the second display panel. When the driving chip is applied to the first display panel, a first output pin of the first type of output pins and a second output pin of the second type of output pins are both connected with the fan-out lead of the first display panel.

Therefore, the driving chip can be applied to the first display panel with high resolution and the second display panel with low resolution, so that the display panels with different resolutions can share the same driving chip, the utilization rate of the driving chip is improved, and the design cost of the driving chip is reduced.

In an alternative embodiment, the first type output pins and the second type output pins are arranged side by side on the same side of the driving chip; in the direction pointing to the second type output pins along the first type output pins, the driving chip is provided with a central area, a first edge area and a second edge area, wherein the first edge area and the second edge area are positioned on two sides of the central area; the central area, the first edge area and the second edge area are distributed with a first output pin group, and the second output pin group is positioned in the central area. Therefore, the second output pin is arranged in the central area of the driving chip, so that the driving chip in the embodiment of the application can be applied to the first display panel with the arrangement serial number of the fan-out lead wire different from the arrangement serial number of the data line connected with the fan-out lead wire, the frame width of the first display panel where the binding area is located is reduced, and the driving chip in the embodiment of the application can also be applied to the second display panel with the arrangement serial number of the fan-out lead wire same as the arrangement serial number of the data line connected with the fan-out lead wire.

In an alternative embodiment, the second type of output pin includes a plurality of second output pin groups, and each second output pin group is located between two adjacent first output pin groups. Therefore, when the driving chip is connected with the data line through the fan-out lead, the lengths of the fan-out leads are uniform, the uniformity of the wiring impedance of the fan-out leads can be improved, and the brightness uniformity of the display panel is improved.

In an alternative embodiment, the number of the second output pins included in each of the second output pin groups is equal. Therefore, the uniformity of the lengths of the fan-out leads connected with the output pins of the driving chip can be further improved, and the routing impedance uniformity of each fan-out lead can be further improved.

In an alternative embodiment, a plurality of first output pin groups are disposed in the central region, and the number of the first output pins included in each first output pin group in the central region is equal. Therefore, the length uniformity of the fan-out lead wires connected with the output pins of the driving chip can be further improved, and the routing impedance uniformity of the fan-out lead wires is further improved.

In an alternative embodiment, the number of the first output pins included in the first output pin group in the first edge region and the second edge region is greater than the number of the first output pins included in the first output pin group in the central region. In this way, the number of the first output pins included in the first output pin group in the central area is set to be smaller, so that the uniformity of the length of the fan-out leads connected with the output pins of the driving chip can be further improved, and the uniformity of the routing impedance of each fan-out lead is further improved.

In an alternative embodiment, the number of the second output pin groups is equal to the number of the first output pin groups in the central region; the number of the first output pin groups in the first edge region and the second edge region is 1. In this way, by only providing the second output pin group in the central region, the complexity of sequentially changing the display data by the sequence changing module provided in the driver chip can be reduced.

In an alternative embodiment, the total number of the second output pins in the second class of output pins is smaller than the total number of the first output pins in the first class of output pins. Therefore, when the total number of the second output pins in the second type of output pins is less, and the number of the data lines in the first edge display area and the second edge display area is less, the number of the corresponding first connecting lines and the second connecting lines is less, so that the complexity of manufacturing the first connecting lines and the second connecting lines is simplified.

In an alternative embodiment, the central region comprises a first central sub-region and a second central sub-region, the first central sub-region being located between the second central sub-region and the first edge region, the second central sub-region being located between the first central sub-region and the second edge region; the number of the second output pin groups in the first center subregion is equal to the number of the second output pin groups in the second center subregion; the number of first output pin groups in the first center sub-area is equal to the number of first output pin groups in the second center sub-area. Therefore, the length uniformity of the fan-out lead wires connected with the output pins of the driving chip can be further improved, and the routing impedance uniformity of the fan-out lead wires is further improved.

In an alternative embodiment, in the first central sub-area, the arrangement serial number of the data lines connected by the second output pins through the fan-out leads of the first display panel is smaller than the arrangement serial number of the data lines connected by the first output pins through the fan-out leads of the first display panel; in the second central sub-area, the arrangement serial number of the data lines connected with the second output pins through the fan-out lead wires of the first display panel is greater than that of the data lines connected with the first output pins through the fan-out lead wires of the first display panel; the arrangement serial numbers of the second output pins in the first central subarea are smaller than the arrangement serial numbers of the second output pins in the second central subarea. In this way, by changing the arrangement serial number of the data lines connected with the fan-out lead wires, the data lines in the first edge display area are connected with the fan-out lead wires through the first connecting wires, and the data lines in the second edge display area are connected with the fan-out lead wires through the second connecting wires, so that the frame width of the side of the binding area of the first display panel is reduced, and the driving chip can be suitable for the first display panel with the smaller frame width of the side of the binding area.

In an optional implementation manner, a sequence changing module and an output pin selecting module are arranged in the driving chip; the sequence changing module is used for sequentially changing first display data in an input first display data sequence according to a first corresponding relation between the arrangement serial number of each fan-out lead and the arrangement serial number of a data line connected with the fan-out lead when the driving chip is connected with the fan-out leads of the first display panel to obtain a second display data sequence so as to output the second display data in the second display data sequence to each fan-out lead; a second corresponding relation exists between the arrangement serial number of the data line corresponding to the first display data at the same position serial number and the arrangement serial number of the data line corresponding to the second display data, and the first corresponding relation is the same as the second corresponding relation; and the output pin selection module is used for setting the second output pin disconnected from the fan-out lead wire to be in an invalid state when the driving chip is connected with the fan-out lead wire of the second display panel. In this way, the sequence changing module is arranged in the driving chip, so that when the driving chip is applied to the first display panel, the driving chip can transmit the display data to the correct data line; and, through set up output pin selection module in driver chip for driver chip is when being applied to second display panel, driver chip can be with the transmission of display data to correct data line.

In an optional implementation manner, a first enabling module is further disposed in the driving chip, and the first enabling module is configured to enable the sequence changing module and disable the output pin selecting module when the driving chip is connected to the fan-out lead of the first display panel; or the driving chip is also internally provided with a second enabling module, and the second enabling module is used for enabling the output pin selection module and disabling the sequence changing module when the driving chip is connected with the fan-out lead of the second display panel. Therefore, the driving chip in the embodiment of the present application can normally drive the first display panel to work through the first starting module, and the driving chip in the embodiment of the present application can normally drive the second display panel to work through the second starting module.

In a second aspect, an embodiment of the present application provides a terminal device, which includes a display panel and the above-mentioned driver chip, where a data line in the display panel is connected to the driver chip through a fan-out lead, and the display panel is a first display panel or a second display panel.

It should be understood that the second aspect of the present application corresponds to the technical solution of the first aspect of the present application, and the beneficial effects achieved by the aspects and the corresponding possible implementation are similar and will not be described again.

Drawings

Fig. 1 is a schematic structural diagram of a terminal device according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a display panel and a driving chip connected to the display panel according to an embodiment of the present disclosure;

FIG. 3 is a partial enlarged view of a region A of the display panel shown in FIG. 2;

FIG. 4 is a schematic diagram of the connection between the data lines and the output pins of the driving chip in the display panel shown in FIG. 2;

FIG. 5 is a diagram illustrating a driving chip shown in FIG. 4 sequentially changing the input display data;

fig. 6 is a schematic structural diagram of another display panel and a driving chip connected thereto according to an embodiment of the present disclosure;

fig. 7 is a schematic diagram illustrating connection between data lines and output pins of a driving chip in the display panel shown in fig. 6.

Detailed Description

In the embodiments of the present application, terms such as "first" and "second" are used to distinguish the same or similar items having substantially the same function and action. For example, the first chip and the second chip are only used for distinguishing different chips, and the sequence order thereof is not limited. Those skilled in the art will appreciate that the terms "first," "second," etc. do not denote any order or quantity, nor do the terms "first," "second," etc. denote any order or importance.

It should be noted that in the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

In the embodiments of the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or multiple.

With the continuous development of the information era, terminal devices such as mobile phones and tablet computers have become common tools in life and work of people. In order to realize contents such as images and videos, a terminal device is provided with a display panel in which data lines are provided; in addition, in order to input corresponding display data to the data lines in the display panel, a driver chip needs to be disposed in the binding region of the display panel, and the display data is transmitted to the data lines through the driver chip.

To the display panel that the resolution ratio is different, the number of the data line that sets up in it is inequality to need to have the different driver chip of output pin quantity to transmit and show data, that is to say, the required driver chip of the display panel that the resolution ratio is different, thereby it is suitable for the driver chip of different resolution ratios to make driver chip manufacturer need make, thereby cause the waste of resource, make the increase of driver chip's design cost, and also lead to the lower problem of rate of utilization of the driver chip of same type.

Based on this, an embodiment of the present application provides a driving chip, where output pins in the driving chip are divided into a first type of output pins and a second type of output pins, when the driving chip is applied to a first display panel, both a first output pin in the first type of output pins and a second output pin in the second type of output pins are connected to a fan-out lead of the first display panel, and when the driving chip is applied to a second display panel, a first output pin in the first type of output pins is connected to a fan-out lead of the second display panel, and at least a part of the second output pins in the second type of output pins is disconnected from the fan-out lead of the second display panel. Because the fan-out leads correspond to the data lines one by one, the resolution of the second display panel is smaller than that of the first display panel, and the driving chip can be applied to the first display panel with high resolution and the second display panel with low resolution, so that the display panels with different resolutions can share the same driving chip, the utilization rate of the driving chip is improved, and the design cost of the driving chip is reduced.

The driving chip provided by the embodiment of the application can be applied to terminal equipment with a display panel, and the terminal equipment can be mobile phones, tablet computers, electronic readers, notebook computers, vehicle-mounted equipment, wearable equipment, televisions and other equipment.

The embodiment of the present application takes a terminal device as an example for explanation. As shown in fig. 1, the terminal device 100 includes a display panel 10 and a housing 20. The display panel 10 is mounted on the housing 20, and is used for displaying images, videos, and the like; the display panel 10 and the housing 20 together enclose a receiving cavity of the terminal device 100, so that electronic devices and the like of the terminal device 100 can be placed through the receiving cavity, and meanwhile, the electronic devices in the receiving cavity are sealed and protected. For example, a circuit board and a battery of the terminal device 100 are located within the accommodation cavity.

The following describes an application scenario of the driving chip in the embodiment of the present application with two display panels with different resolutions.

For one of the display panels, the display panel may be referred to as a first display panel, and as shown in fig. 2 and 3, the first display panel 101 has a display area AA and a frame area NA surrounding the display area AA. The display area AA includes a first edge display area a2, a center display area a1, and a second edge display area A3 sequentially distributed along the first direction X, and the center display area a1 is located between the first edge display area a2 and the second edge display area A3.

A data line 11 extending along the second direction Y and a plurality of sub-pixels 12 distributed in an array are disposed in the display area AA, each sub-pixel 12 includes a pixel driving circuit and a light emitting device connected to the pixel driving circuit, and the same row of pixel driving circuits is connected to the same data line 11.

Actually, in the first edge display area a2, the center display area a1, and the second edge display area A3 included in the display area AA, the data line 11 extending in the second direction Y is disposed, and the second direction Y intersects with the first direction X. In some embodiments, the first direction X and the second direction Y are perpendicular to each other, the first direction X is a row direction of the first display panel 101, and the second direction Y is a column direction of the first display panel 101.

A first connection line 13a and a second connection line 13b are also provided in the display area AA of the first display panel 101. One end of the first connection line 13a extends to the first edge display area a2 and is connected to the data line 11 located in the first edge display area a2, and the other end of the first connection line 13a extends to the boundary of the central display area a1 on the side facing the binding area N2; one end of the second connection line 13b extends to the second edge display region A3 and is connected to the data line 11 located in the second edge display region A3, and the other end of the second connection line 13b extends to the boundary of the central display region a1 on the side facing the bonding region N2.

The frame area NA includes a fan-out area N1 and a binding area N2 located at one side of the display area AA, and the fan-out area N1 is located between the binding area N2 and the display area AA. A plurality of fan-out leads 31 are arranged in the fan-out region N1, a driver chip 32 is arranged in the bonding region N2, the driver chip 32 is bonded in the bonding region N2 through a Chip On Film (COF) 33, a connection trace is arranged on the COF 33, one end of the connection trace is connected with an output pin of the driver chip 32, and the other end of the connection trace is connected with a bonding terminal (not shown) of the COF 33. The fan-out leads 31 are actually connected to bonding terminals of the chip-on-film 33, so that the connection of the fan-out leads 31 to the output pins of the driving chip 32 is realized based on the chip-on-film 33.

Of course, it can be understood that the driving chip 32 is not limited to be bonded to the bonding region N2 of the first display panel 101 by COF, but COG (chip on glass) or COP (chip on plastic) may also be used, where COG refers to directly bonding the driving chip 32 to the first display panel 101 by using an anisotropic conductive adhesive, a substrate of the first display panel is a glass substrate, and COP refers to directly fixing the driving chip 32 to the first display panel 101 using a plastic substrate, and is applicable to a flexible display panel.

In the embodiment of the present application, the other end of the first connection line 13a extends to the boundary of the central display area a1 on the side facing the bonding area N2 and is connected to the fan-out lead 31 located in the fan-out area N1 on the boundary of the central display area a1 on the side facing the bonding area N2, that is, the data line 11 in the first edge display area a2 is connected to the fan-out lead 31 through the first connection line 13 a; the other end of the second connection line 13b extends to the boundary of the central display area a1 towards the side of the bonding area N2 and is connected with the fan-out lead 31 positioned in the fan-out area N1 at the boundary of the central display area a1 towards the side of the bonding area N2, namely, the data line 11 in the second edge display area A3 is connected with the fan-out lead 31 through the second connection line 13 b; and the data lines 11 in the central display area a1 are directly connected to the fan-out leads 31.

Therefore, the display data provided by the driver chip 32 is output from the output pins of the driver chip 32, transmitted to the fan-out lead 31 through the connection traces of the flip-chip film 33 and the bonding terminals of the flip-chip film 33, and transmitted to the data lines 11 through the fan-out lead 31, so that the data lines 11 can transmit the display data to the pixel driving circuits in the same row.

As can be seen from fig. 2, the fan-out leads 31 may be only distributed in the overlapping area between the central display area a1 and the fan-out area N1 after extending along the second direction Y, and the fan-out leads 31 do not need to wrap around from the first corner CNT1 and the second corner CNT2 of the display area AA to the position of the flip-chip film 33, so as to reduce the frame width of the first display panel 101 at the side where the bonding area N2 is located, thereby improving the screen coverage of the terminal device 100.

The first connection line 13a and the second connection line 13b may each include a first sub-line segment, a second sub-line segment pole, and a third sub-line segment, which are connected in sequence, where the first sub-line segment extends along the second direction Y and is connected to the data line 11, the second sub-line segment extends along the first direction X, and the third sub-line segment extends along the second direction Y and is connected to the fan-out lead 31.

It is understood that the specific structure of the first connection line 13a and the second connection line 13b is not limited to the structure shown in fig. 2, as long as one end of the first connection line 13a may extend to the first edge display area a2 and be connected to the data line 11 located within the first edge display area a2, while the other end of the first connection line 13a extends to the boundary of the central display area a1 toward the side of the binding area N2, and one end of the second connection line 13b may extend to the second edge display area A3 and be connected to the data line 11 located within the second edge display area A3, while the other end of the second connection line 13b extends to the boundary of the central display area a1 toward the side of the binding area N2.

For example, the first and

second connection lines

13a and 13b may include only the second and third sub-line segments connected to each other. The second sub-line segment of the first connecting line 13a extends along the first direction X and is directly connected to the data line 11 in the first edge display area a2, and the third sub-line segment of the first connecting line 13a extends along the second direction Y to the boundary of the central display area a1 on the side facing the binding area N2; the second sub-line segment of the second connection line 13b extends along the first direction X and is directly connected to the data line 11 in the second edge display area A3, and the third sub-line segment of the second connection line 13b extends along the second direction Y to the boundary of the central display area a1 facing the side of the bonding area N2.

Alternatively, the first connection line 13a and the second connection line 13b may include a fourth sub-line segment and a fifth sub-line segment connected to each other, the fourth sub-line segment in the first connection line 13a is connected to the data line 11 in the first edge display area a2, the fifth sub-line segment in the first connection line 13a extends to a boundary of the central display area a1 on the side facing the binding area N2, and in the first connection line 13a, the fourth sub-line segment and the fifth sub-line segment respectively have an included angle different from 0 with respect to both the first direction X and the second direction Y, that is, the fourth sub-line segment in the first connection line 13a intersects both the first direction X and the second direction Y, and the fifth sub-line segment in the first connection line 13a also intersects both the first direction X and the second direction Y. Accordingly, the fourth sub-line segment in the second connection line 13b is connected to the data line 11 in the second edge display area A3, the fifth sub-line segment in the second connection line 13b extends to the boundary of the central display area a1 on the side facing the binding area N2, and in the second connection line 13b, the fourth sub-line segment and the fifth sub-line segment respectively have an included angle different from 0 with respect to both the first direction X and the second direction Y, that is, the fourth sub-line segment in the second connection line 13b intersects both the first direction X and the second direction Y, and the fifth sub-line segment in the second connection line 13b also intersects both the first direction X and the second direction Y.

In addition, in the display area AA, the first connecting line 13a and the second connecting line 13b are arranged on the same layer, and the film layer where the data line 11 is located is different from the film layer where the first connecting line 13a and the second connecting line 13b are located, that is, the data line 11 and the first connecting line 13a are located on different film layers, and the data line 11 and the second connecting line 13b are also located on different film layers; moreover, the film layers of the first connecting lines 13a and the second connecting lines 13b and the film layers of the data lines 11 are separated by at least one insulating layer, that is, at least one insulating layer is arranged between the film layers of the first connecting lines 13a and the second connecting lines 13b and the film layers of the data lines 11, and the first connecting lines 13a and the second connecting lines 13b are respectively connected with the data lines 11 through via holes penetrating through the insulating layers.

For example, in some embodiments, the first sub-line segment of the first connection line 13a is connected to the data line 11 located within the first edge display area a2 through a via hole penetrating the insulating layer, and the first sub-line segment of the second connection line 13b is connected to the data line 11 located within the second edge display area A3 through a via hole penetrating the insulating layer; in other implementations, the fourth sub-line segment in the first connection line 13a is connected to the data line 11 located in the first edge display area a2 through a via hole passing through the insulating layer, and the fourth sub-line segment in the second connection line 13b is connected to the data line 11 located in the second edge display area A3 through a via hole passing through the insulating layer.

In the first display panel 101, when the data lines 11 in the first edge display area a2 are connected to the fan-out lead 31 through the first connection lines 13a and the data lines 11 in the second edge display area A3 are connected to the fan-out lead 31 through the second connection lines 13b, the arrangement number of the fan-out lead 31 is different from the arrangement number of the data lines 11 connected thereto along the first direction X.

The arrangement serial number of the fan-out lead 31 refers to the sorting serial number of each fan-out lead 31 along the first direction X when the fan-out leads 31 are distributed, for example, for the fan-out lead 31 in the ith column, the corresponding arrangement serial number is i, and i is a positive integer; the arrangement number of the data lines 11 refers to a sorting number of each data line 11 along the first direction X when the data lines are distributed, for example, for the j-th column of data lines 11, the corresponding arrangement number is j, and j is a positive integer.

Since the data lines 11 in the first edge display area a2 are connected to the fan-out lead 31 through the first connection line 13a, the data lines 11 in the second edge display area A3 are connected to the fan-out lead 31 through the second connection line 13b, and the data lines 11 in the center display area a1 are directly connected to the fan-out lead 31 in the first display panel 101, in order to distinguish the output pins corresponding to the fan-out leads 31 connected to the data lines 11 through different connection methods, the output pins of the driving chip 32 may be divided into the first type of output pins and the second type of output pins. The first type of output pins refer to output pins connected with first type of fan-out leads, and the first type of fan-out leads are directly connected with the data lines 11, that is, the data lines 11 corresponding to the first output pins in the first type of output pins refer to the data lines 11 in the central display area a1 in the first display panel 101; the second type output pin refers to an output pin connected to a second type fan-out lead, which is connected to the data line 11 through the first connection line 13a or the second connection line 13b, that is, the data line 11 corresponding to the second output pin in the second type output pin refers to: the data line 11 within the first edge display area a2 and the data line 11 within the second edge display area A3 in the first display panel 101.

Next, the connection relationship between the output pins of the driver chip 32 in the embodiment of the present application and the fan-out leads 31 and the data lines 11 in the first display panel 101 will be described by taking the driver chip 32 shown in fig. 4 as an example.

As shown in fig. 4, the first type output pins in the driver chip 32 include a plurality of first output pin groups 321, and each first output pin group 321 includes at least one first output pin; the second type output pins in the driver chip 32 include a plurality of second output pin groups 322, and each second output pin group 322 includes at least one second output pin.

For example, the first output pins included in the first output pin group 321 are pins 1 to 2217, the first output pin included in the second first output pin group 321 is pin2218, the first output pin included in the third first output pin group 321 is pin2223, the first output pin included in the fourth first output pin group 321 is pin2228, and so on, the first output pin included in the 76 th first output pin group 321 is pin2588, the first output pin included in the 77 th first output pin group 321 is pin2593, the first output pin included in the 78 th first output pin group 321 is pin2598, and so on, the first output pin included in the 150 th first output pin group 321 is pin2958, the first output pin included in the 151 th first output pin group 321 is pin2963, and the first output pin included in the 152 th first output pin group 321 is pin2968 to 5184.

And the second output pins included in the first second output pin group 322 are respectively pin2219 to pin2222, the second output pins included in the second output pin group 322 are respectively pin2224 to pin2227, and so on, the second output pins included in the 75 th second output pin group 322 are respectively pin2589 to pin2592, the second output pins included in the 76 th second output pin group 322 are respectively pin2594 to pin2597, and so on, the second output pins included in the 149 th second output pin group 322 are respectively pin2959 to pin2962, and the second output pins included in the 150 th second output pin group 322 are respectively pin2964 to pin 2967.

When the driving chip 32 is applied to the first display panel 101, each first output pin of the first class of output pins is connected to the fan-out lead 31 of the first display panel 101, and each second output pin of the second class of output pins is also connected to the fan-out lead 31 of the first display panel 101. At this time, the output pins in the driver chip 32 correspond to the fan-out leads 31 one to one, that is, the number of the output pins in the driver chip 32 is equal to the number of the fan-out leads 31.

Since the fan-out leads 31 are also in one-to-one correspondence with the data lines 11, when both the first output pins of the first type of output pins and the second output pins of the second type of output pins are connected to the fan-out leads 31 of the first display panel 101, it can be known that the number of the data lines 11 in the first display panel 101 is equal to the total number of the first output pins and the second output pins in the driving chip 32.

Taking fig. 4 as an example, the number of the data lines 11 in the first display panel 101 and the number of the fan-out leads 31 in the first display panel 101 are 5184, and the total number of the first output pins and the second output pins in the driving chip 32 is 5184, that is, the driving chip 32 may be applied to the first display panel 101 in which the number of the data lines 11 is 5184, and the serial number of the fan-out leads 31 in the first display panel 101 is different from the serial number of the data lines 11 connected thereto. The number of the first output pins in the driver chip 32 is 4584, and the number of the second output pins in the driver chip 32 is 600.

The serial numbers of the output pins in the driver chip 32 along the first direction X are sequentially increased, for example, the output pins in the driver chip 32 along the first direction X are pin1, pin2 to pin 5184; the arrangement serial number of the output pins in the driver chip 32 refers to a sequence serial number of the output pins in the driver chip 32 when the output pins are distributed along the first direction X, for example, for the ith output pin, the corresponding arrangement serial number is i, and i is a positive integer.

The arrangement numbers of the fan-out leads 31 in the first direction X are also sequentially increased, for example, the 1 st fan-out lead 31, the 2 nd fan-out lead 31 to the 5184 th fan-out lead 31 are sequentially arranged in the first direction X.

And the arrangement number of the data lines 11 connected to each of the fan-out leads 31 distributed along the first direction X is not sequentially incremented. Specifically, along the first direction X, the data lines 11 to which the first output pins of the first class of output pins are connected through the fan-out lead 31 are sequentially arranged, and the data lines 11 to which the second output pins of the second class of output pins are connected through the fan-out lead 31 are not sequentially arranged with respect to the data lines 11 corresponding to the first class of output pins.

For example, along the first direction X, the first output pins in the first class of output pins are pins 1 to 2218, 2223, 2228 and 2233, and so on to pin2963, and pins 2968 to 5184, and the corresponding data lines 11 are L301 to L4884, and it can be seen that the data lines 11 connected to the first output pins in the first class of output pins through the fan-out lead 31 are arranged in sequence; and the second output pins in the second class of output pins are respectively pin2219 to pin2222, pin2224 to pin2227, and so on until pin2964 to pin2967, and the corresponding data lines 11 thereof are respectively L300 to L297, L296 to L293, and so on until L4888 to L4885, it can be seen that the data lines 11 connected by the second output pins in the second class of output pins through the fan-out lead 31 are not in sequential arrangement with respect to the data lines 11 corresponding to the first class of output pins.

It should be noted that, a part of the data lines 11 in the first display panel 101 are connected to the fan-out leads 31 through the first connection lines 13a or the second connection lines 13b, fig. 4 is only to illustrate the relationship between the arrangement numbers of the fan-out leads 31 and the arrangement numbers of the data lines 11 connected thereto clearly, the fan-out leads 31 are drawn to be directly connected to the data lines 11, and the actual connection relationship between the fan-out leads 31 and the data lines 11 can refer to the first display panel 101 shown in fig. 2 and 3.

At this time, in order to ensure that the driver chip 32 can transmit the display data to the correct data lines 11, a sequence change module is arranged in the driver chip 32, and the sequence change module performs sequence change on the first display data in the input first display data sequence according to a first corresponding relationship between the arrangement serial number of each fan-out lead 31 and the arrangement serial number of the data line 11 connected to the fan-out lead 31 to obtain a second display data sequence, so as to output the second display data in the second display data sequence to each fan-out lead 31; a second corresponding relationship exists between the arrangement serial number of the data line 11 corresponding to the first display data at the same position serial number and the arrangement serial number of the data line 11 corresponding to the second display data, and the first corresponding relationship is the same as the second corresponding relationship. The position number refers to the position number of the display data within its corresponding display data sequence.

For example, after the sequence of the data line 11 corresponding to the ith first display data Di in the first display data sequence is changed through the driving chip 32, the sequence of the data line 11 corresponding to the ith second display data Di in the second display data sequence is j, that is, the ith second display data is Dj, and at this time, the second corresponding relationship is i-j; the ith second display data Dj in the second display data sequence is output from the ith pin of the driving chip 32 and then transmitted to the fan-out lead 31 with the arrangement serial number i, that is, to the ith fan-out lead 31, and the fan-out lead 31 with the arrangement serial number i is connected with the data line 11 with the arrangement serial number j, that is, the first corresponding relationship is i-j; the first corresponding relationship is the same as the second corresponding relationship, so that the ith second display data Dj in the second display data sequence obtained after the sequence change can be correctly transmitted to the jth column data line 11.

Therefore, the driver chip 32 shown in fig. 4 sequentially changes the first display data in the input first display data sequence, and the distribution of the second display data in the second display data sequence is as shown in fig. 5, where the first display data in the first display data sequence input to the driver chip 32 sequentially is: d1, D2 to D5184, and the driving chip 32 sequentially changes the first display data in the first display data sequence, and the obtained second display data in the second display data sequence sequentially are: d301 to D2518, D300 to D297, D2519, D296 to D293, and so on, through D2667, D4888 to D4885, and D2668 to D4884.

For another display panel, the display panel may be referred to as a second display panel, as shown in fig. 6, the second display panel 102 also has a display area AA and a frame area NA surrounding the display area AA. A data line 11 extending along the second direction Y and a plurality of sub-pixels (not shown in fig. 6) distributed in an array are disposed in the display area AA; the frame area NA includes a fan-out area N1 and a binding area N2 located at one side of the display area AA, and the fan-out area N1 is located between the binding area N2 and the display area AA.

A plurality of fan-out leads 31 are disposed in the fan-out region N1, and the data line 11 is directly connected to the fan-out leads 31 at a boundary of the display area AA on a side facing the bonding region N2. The driver chip 32 is disposed in the bonding region N2, the driver chip 32 is bonded in the bonding region N2 through the flip-chip film 33, and the fan-out lead 31 is connected to an output pin of the driver chip 32 through the flip-chip film 33. Of course, in some embodiments, the driving chip 32 may also be bonded in the bonding region N2 of the second display panel 102 by COG or COP.

Therefore, the display data provided by the driving chip 32 is output from the output pin of the driving chip 32, transmitted to the fan-out lead 31 through the connection trace of the flip chip 33 and the bonding terminal of the flip chip 33, and then transmitted to the data line 11 through the fan-out lead 31, so that the data line 11 can transmit the display data to the pixel driving circuit in the same row.

The second display panel 102 shown in fig. 6 is different from the first display panel 101 shown in fig. 2 in that, in the first display panel 101 shown in fig. 2, the data lines 11 in the first edge display area a2 are connected to the fan-out leads 31 through the first connection lines 13a, and the data lines 11 in the second edge display area A3 are connected to the fan-out leads 31 through the second connection lines 13b, whereas in the second display panel 102 shown in fig. 6, the first connection lines 13a and the second connection lines 13b are not provided in the display area AA, but the data lines 11 in the display area AA are directly connected to the fan-out leads 31. Therefore, in the second display panel 102, the fan-out lead 31 has the same arrangement number as the data line 11 connected thereto in the first direction X.

Next, the connection relationship between the output pins of the driver chip 32 in the embodiment of the present application and the fan-out leads 31 and the data lines 11 in the second display panel 102 will be described by taking the driver chip 32 shown in fig. 7 as an example.

When the driving chip 32 is applied to the second display panel 102, each first output pin of the first type of output pins is connected to the fan-out lead 31 of the second display panel 102, and each second output pin of the second type of output pins is disconnected from the fan-out lead 31 of the second display panel 102. At this time, the output pins in the driver chip 32 do not correspond to the fan-out leads 31 one by one, that is, the number of output pins (including the first output pin and the second output pin) in the driver chip 32 is greater than the number of fan-out leads 31.

Since the fan-out leads 31 correspond to the data lines 11 one to one, when all the first output pins in the first type of output pins are connected to the fan-out leads 31 of the second display panel 102, and all the second output pins in the second type of output pins are disconnected from the fan-out leads 31 of the second display panel 102, it can be known that the number of the data lines 11 in the second display panel 102 is equal to the total number of the first output pins in the driving chip 32.

For example, for the driver chip 32 shown in fig. 7, the number of the first output pins in the driver chip 32 is 4584, the number of the second output pins in the driver chip 32 is 600, the driver chip 32 can be applied to the second display panel 102 having 4584 data lines 11, and the arrangement number of the fan-out leads 31 in the second display panel 102 is the same as the arrangement number of the data lines 11 connected thereto.

Further, the arrangement numbers of the output pins in the driver chip 32 along the first direction X are sequentially increased, for example, the output pins in the driver chip 32 along the first direction X are pin1, pin2 to pin 5184. The arrangement numbers of the fan-out leads 31 along the first direction X are also sequentially increased, for example, the 1 st fan-out lead 31, the 2 nd fan-out lead 31 to the 4584 nd fan-out lead 31 along the first direction X. The arrangement numbers of the data lines 11 connected to each fan-out lead 31 distributed along the first direction X are also sequentially increased, for example, along the first direction X, the data line 11 connected to the ith fan-out lead 31 is the ith data line 11.

Therefore, in the embodiment of the present application, all the second output pins in the second type of output pins in the driving chip 32 are used as dynamic pins, which are connected to the fan-out lead 31 when the driving chip 32 is applied to the first display panel 101, and are disconnected from the fan-out lead 31 when the driving chip 32 is applied to the second display panel 102, so that the same driving chip 32 can be used in both the first display panel 101 with high resolution and the second display panel 102 with low resolution, that is, the resolution of the second display panel 102 is smaller than that of the first display panel 101, and the first display panel 101 and the second display panel 102 can share the same driving chip 32, thereby increasing the utilization rate of the driving chip 32 of the same type, and reducing the design cost of the driving chip 32.

It should be noted that the resolution of the display panel in the embodiment of the present application mainly refers to the resolution parameter of the display panel along the second direction Y, and the number of the data lines 11 is equal to the resolution parameter of the display panel along the second direction Y.

The above description is made in a manner that all the second output pins in the second type of output pins are disconnected from the fan-out lead 31 of the second display panel 102, and of course, when the driving chip 32 in the embodiment of the present application is applied to the second display panel 102 having the same arrangement number of the fan-out lead 31 as that of the data line 11 connected thereto, some of the second output pins included in the second type of output pins may be disconnected from the fan-out lead 31 of the second display panel 102, and the other remaining second output pins in the second type of output pins may be connected to the fan-out lead 31 of the second display panel 102.

At this time, the number of the data lines 11 in the second display panel 102 is equal to the sum of the total number of the first output pins in the driving chip 32 and the number of the second output pins connected to the fan-out lead 31 in the second type of output pins.

For example, for the driving chip 32 shown in fig. 7, two of the second output pins in each second output pin group 322 may be disconnected from the fan-out lead 31, and the other two second output pins in each second output pin group 322 may be connected to the fan-out lead 31, so that the driving chip 32 may be applied to the 4884 second display panels 102 with data lines 11.

At this time, in order to ensure that the driver chip 32 can transmit the display data from the correct output pin, an output pin selection module is provided in the driver chip 32, and the output pin selection module sets the second output pin disconnected from the fan-out lead 31 to an invalid state, so that the display data that the driver chip 32 needs to output is not output from the second output pin set to the invalid state.

When all the second output pins in the second type of output pins are disconnected from the fan-out lead 31 of the second display panel 102, all the second output pins in the second type of output pins are set to be in an invalid state through the output pin selection module, and at this time, the display data output by the driving chip 32 is only output to the fan-out lead 31 from the first output pins in the first type of output pins, but not output from the second output pins in the second type of output pins.

For example, the second output pins set to the inactive state in the driving chip 32 shown in fig. 7 are: the display data output by the driving chip 32 cannot be output from the second output pin set to be in an invalid state, and the display data output by the driving chip 32 can be sequentially input into the corresponding fan-out leads 31.

When a part of the second output pins of the second type of output pins are disconnected from the fan-out lead 31 of the second display panel 102 and another part of the second output pins of the second type of output pins are connected to the fan-out lead 31 of the second display panel 102, the second output pins disconnected from the fan-out lead 31 are set to be in an invalid state by the output pin selection module, and at this time, the display data output by the driving chip 32 is output to the fan-out lead 31 only from the first output pins of the first type of output pins and the second output pins connected to the fan-out lead 31 of the second display panel 102 among the second type of output pins, and is not output from the second output pins disconnected from the fan-out lead 31 of the second display panel 102 among the second type of output pins.

As shown in fig. 4 and 7, in the embodiment of the present application, the first type output pins and the second type output pins are arranged side by side on the same side of the driving chip 32. For example, the first output pins and the second output pins are arranged side by side on the side of the driving chip 32 close to the display area AA, which can shorten the distance from the driving chip 32 to the display area AA along the second direction Y, thereby reducing the frame width of the display panel on the side of the driving chip 32.

In a direction pointing to the second type output pins along the first type output pins, that is, along the first direction X, the driving chip 32 has a central region B1 and first and second edge regions B2 and B3 located at both sides of the central region B1; the first output pin group 321 is distributed in the central region B1, the first edge region B2 and the second edge region B3, and the second output pin group 322 is located in the central region B1.

For example, the first edge region B2 includes only 1 first output pin group 321, that is, a first output pin group 321, the first output pins included in the first output pin group 321 are pin1 to pin2217, respectively, and at this time, the number of the first output pins in the first edge region B2 is 2217; the central region B1 includes 150 first output pin groups 321, i.e., the second first output pin group 321 to the 151 th first output pin group 321, at this time, the number of the first output pin groups 321 in the central region B1 is 150, and each first output pin group 321 includes only 1 first output pin; the second edge area B3 includes only 1 first output pin group 321, that is, the 152 th first output pin group 321, and the first output pins included in the 152 th first output pin group 321 are pin2968 to pin5184, and at this time, the number of the first output pins in the second edge area B3 is 2217.

The central region B1 is provided with 150 second output pin groups 322, that is, the first second output pin group 322 to the 150 th second output pin group 322, at this time, the number of the second output pins in the central region B1 is 600, and each second output pin group 322 includes 4 second output pins.

By arranging the second output pin in the central region B1 of the driver chip 32, the driver chip 32 in the embodiment of the present application can be applied to the first display panel 101 where the arrangement serial number of the fan-out lead 31 is different from the arrangement serial number of the data line 11 connected thereto, so as to reduce the frame width where the bonding region N2 of the first display panel 101 is located, and the driver chip 32 in the embodiment of the present application can also be applied to the second display panel 102 where the arrangement serial number of the fan-out lead 31 is the same as the arrangement serial number of the data line 11 connected thereto.

In the embodiment of the present application, the second class of output pins includes a plurality of second output pin groups 322, and each second output pin group 322 is located between two adjacent first output pin groups 321.

For example, as shown in fig. 4 and 7, the second class of output pins includes 150 second output pin groups 322, and the mth second output pin group 322 is located between the (m + 1) th first output pin group 321 and the (m + 2) th first output pin group 321, where m is a positive integer.

It should be noted that, in the driver chip 32 shown in fig. 4 and fig. 7, the second type output pins in the driver chip 32 include 150 second output pin groups 322. In some embodiments, the second type of output pins in the driver chip 32 may also include other numbers of second output pin groups 322, for example, the second type of output pins in the driver chip 32 may also include one second output pin group 322, or the number of second output pin groups 322 included in the second type of output pins in the driver chip 32 may also be equal to the total number of second output pins in the driver chip 32, that is, each second output pin group 322 includes only 1 second output pin.

By dividing the second type of output pins into a plurality of second output pin groups 322, and each second output pin group 322 is disposed between two adjacent first output pin groups 321, the lengths of the fan-out leads 31 of the driving chip 32 are uniform when the fan-out leads 31 are connected with the data lines 11. If the second output pin groups 322 are collected together, that is, if the first output pin group 321 is not disposed between the second output pin groups 322, the lengths of the fan-out leads 31 are greatly different when some of the first output pins are connected to the data lines 11 through the fan-out leads 31. When the lengths of the fan-out leads 31 are uniform, the routing impedance uniformity of the fan-out leads 31 can be improved, and the brightness uniformity of the display panel is improved.

In the embodiment of the present application, each of the second output pin groups 322 includes the same number of second output pins.

For example, in fig. 4 and 7, each of the second output pin groups 322 includes 4 second output pins. Of course, in some embodiments, the number of the second output pins included in the second output pin group 322 is not limited to 4 shown in fig. 4 and 7, and the number of the second output pins included in the second output pin group 322 may also be 1, 2, 3, 5, and the like. Specifically, the number of the second output pins included in the second output pin group 322 is greater than or equal to 1, and is less than or equal to a positive integer of the total number of the second output pins in the driving chip 32.

By setting the number of second output pins included in each second output pin group 322 to be equal, the uniformity of the length of the fan-out leads 31 connected to the output pins of the driver chip 32 can be further improved, thereby further improving the uniformity of the routing impedance of each fan-out lead 31.

In addition, a plurality of first output pin groups 321 are disposed in the central region B1, and the number of first output pins included in each first output pin group 321 in the central region B1 is equal.

For example, in fig. 4 and 7, 150 first output pin groups 321 are disposed in the central region B1, and the number of first output pins included in each first output pin group 321 in the central region B1 is 1.

Of course, in some embodiments, the number of the first output pin groups 321 disposed in the central region B1 is not limited to 150, but may be other numbers; the number of the first output pins included in each first output pin group 321 in the central region B1 is not limited to 1 shown in fig. 4 and 7, and the number of the first output pins included in each first output pin group 321 in the central region B1 may also be 2 or 3.

By setting the number of the first output pins included in each of the first output pin groups 321 in the central region B1 to be equal, it is also possible to further improve the uniformity of the lengths of the fan-out leads 31 connected to the output pins of the driving chip 32, thereby further improving the uniformity of the routing impedance of each of the fan-out leads 31.

In the embodiment of the present application, the number of first output pins included in the first output pin group 321 in the first edge region B2 and the second edge region B3 is greater than the number of first output pins included in the first output pin group 321 in the central region B1.

For example, in fig. 4 and 7, the first output pins included in the first output pin group 321 in the first edge region B2 and the second edge region B3 each include 2217 first output pins, and the first output pins included in the first output pin group 321 in the central region B1 each include 1 first output pin.

In fact, the number of the first output pins 321 included in the first output pin group 321 in the first edge region B2 and the second edge region B3 is 1, and the number of the first output pins included in the first output pin group 321 in the first edge region B2 is equal to the number of the first output pins in the first edge region B2, and the number of the first output pins included in the first output pin group 321 in the second edge region B3 is equal to the number of the first output pins in the second edge region B3.

By setting the number of the first output pins included in the first output pin group 321 in the central region B1 to be small, it is possible to further improve the uniformity of the lengths of the fan-out leads 31 connected to the output pins of the driving chip 32, thereby further improving the uniformity of the wiring impedance of the respective fan-out leads 31.

Optionally, the number of the first output pins in the first edge region B2 and the second edge region B3 is greater than the number of the first output pins in the central region B1. For example, in fig. 4 and 7, the number of first output pins in the first edge region B2 and the second edge region B3 is 2217 each, and the number of first output pins in the central region B1 is 150.

In the present embodiment, the number of the second output pin groups 322 is equal to the number of the first output pin groups 321 in the center region B1; the number of the first output pin groups 321 in the first edge region B2 and the second edge region B3 is 1.

For example, in fig. 4 and 7, the number of the second output pin groups 322 and the number of the first output pin groups 321 in the central region B1 are 150.

In the embodiment of the present application, the total number of the second output pins in the second class of output pins is smaller than the total number of the first output pins in the first class of output pins.

For example, in fig. 4 and 7, the total number of the second output pins in the second class of output pins is 600, and the total number of the first output pins in the first class of output pins is 4584.

In the first display panel 101, the number of the data lines 11 in the first edge display area a2 and the second edge display area A3 is small, and when the data lines 11 in the first edge display area a2 are connected to the fan-out lead 31 through the first connection line 13a and the data lines 11 in the second edge display area A3 are connected to the fan-out lead 31 through the second connection line 13b, the total number of the second output pins in the second type of output pins is smaller than the total number of the first output pins in the first type of output pins. When the number of the data lines 11 in the first and second edge display areas a2 and A3 is small, the number of the first and

second connection lines

13a and 13b is also small, thereby simplifying the complexity in manufacturing the first and

second connection lines

13a and 13 b.

In an actual product, the output pins in the driving chip 32 are distributed at equal intervals, that is, along the first direction X, the distance between any two adjacent output pins is equal.

In the embodiment of the present application, the center region B1 may be further divided into a first center sub-region B11 and a second center sub-region B12, the first center sub-region B11 is located between the second center sub-region B12 and the first edge region B2, and the second center sub-region B12 is located between the first center sub-region B11 and the second edge region B3.

Wherein the number of the second group of output pins 322 in the first center sub-area B11 is equal to the number of the second group of output pins 322 in the second center sub-area B12; the number of first groups of output pins 321 in the first center sub-area B11 is equal to the number of first groups of output pins 321 in the second center sub-area B12.

For example, as shown in fig. 4 and 7, the number of the second output pin groups 322 in the first center sub-area B11 and the number of the second output pin groups 322 in the second center sub-area B12 are each 75; the number of the first output pin groups 321 in the first center sub-area B11 and the number of the first output pin groups 321 in the second center sub-area B12 are each 75.

It should be noted that, when the driver chip 32 is applied to the first display panel 101, the second output pin in the first center sub-area B11 actually refers to: the output pin to which the fan-out lead 31 connected to the first connection line 13a is connected, the second output pin in the second center sub-area B12 actually means: and an output pin to which the fan-out lead 31 connected to the second connection line 13b is connected.

By setting the number of the second output pin groups 322 in the first center sub-area B11 equal to the number of the second output pin groups 322 in the second center sub-area B12, and setting the number of the first output pin groups 321 in the first center sub-area B11 equal to the number of the first output pin groups 321 in the second center sub-area B12, the uniformity of the lengths of the fan-out leads 31 connected to the output pins of the driver chip 32 can be further improved, thereby further improving the uniformity of the track impedance of each fan-out lead 31.

When the driving chip 32 is applied to the first display panel 101, in the first center sub-area B11, the arrangement number of the data lines 11 to which the second output pins are connected through the fan-out lead 31 is smaller than the arrangement number of the data lines 11 to which the first output pins are connected through the fan-out lead 31; in the second center subregion B12, the arrangement number of the data line 11 to which the second output pin is connected through the fan-out lead 31 is greater than the arrangement number of the data line 11 to which the first output pin is connected through the fan-out lead 31; the serial numbers of the second output pins in the first center sub-area B11 are all smaller than the serial numbers of the second output pins in the second center sub-area B12.

For example, as shown in fig. 4, in the first center subregion B11, the data lines 11 to which the second output pins are connected through the fan-out lead 31 are L1 to L300, respectively, and the data lines 11 to which the first output pins are connected through the fan-out lead 31 are L2518 to L2592, respectively; in the second center sub-area B12, the data lines 11 to which the second output pins are connected through the fan-out lead 31 are L4885 to L5184, respectively, and the data lines 11 to which the first output pins are connected through the fan-out lead 31 are L2593 to L2667, respectively.

When the driving chip 32 is applied to the second display panel 102, along the first direction X, the arrangement numbers of the data lines 11 connected to the output pins through the fan-out leads 31 are sequentially arranged, and the arrangement numbers of the data lines 11 connected to the output pins through the fan-out leads 31 are sequentially increased.

Because the driving chip 32 in the embodiment of the present application can be applied to the first display panel 101 with high resolution and the same arrangement number of the fan-out lead 31 and the data line 11 connected thereto, and can also be applied to the second display panel 102 with low resolution and the same arrangement number of the fan-out lead 31 and the data line 11 connected thereto, in order to ensure that the driving chip 32 can transmit the display data to the correct fan-out lead 31, the sequence changing module and the output pin selecting module need to be simultaneously arranged in the driving chip 32. Therefore, when manufacturing the driving chip 32, the sequence changing module and the output pin selecting module need to be burned in advance.

If the driver chip 32 is bound in the binding region N2 of the first display panel 101, the driver chip 32 needs to be burned again, and a first enabling module is burned inside the driver chip 32, and the first enabling module is used for enabling the sequence changing module and disabling the output pin selecting module when the driver chip 32 is connected with the fan-out lead 31 of the first display panel 101.

That is to say, when the driving chip 32 is connected to the fan-out leads 31 of the first display panel 101, the first enabling module may control the sequence changing module to operate, so that the sequence changing module sequentially changes the first display data in the input first display data sequence according to the first corresponding relationship between the arrangement serial number of each fan-out lead 31 and the arrangement serial number of the data line 11 connected thereto, to obtain a second display data sequence, so as to output the second display data in the second display data sequence to each fan-out lead 31, and at this time, the output pin selecting module is in a stop operating state.

If the driver chip 32 needs to be burned again after being bound in the binding region N2 of the second display panel 102, a second enabling module is burned inside the driver chip 32, and the second enabling module is used for enabling the output pin selection module and disabling the sequence changing module when the driver chip 32 is connected to the fan-out lead 31 of the second display panel 102.

That is, when the driver ic 32 is connected to the fan-out lead 31 of the second display panel 102, the second enabling module may control the output pin selecting module to operate, so that the output pin selecting module sets the second output pin disconnected from the fan-out lead 31 to be in an invalid state, so that the display data output by the driver ic 32 is output from the output pin connected to the fan-out lead 31, and at this time, the sequence changing module is also in a state of stopping operation.

The first start module enables the driving chip 32 in the embodiment of the present application to normally drive the first display panel 101 to operate, and the second start module enables the driving chip 32 in the embodiment of the present application to normally drive the second display panel 102 to operate.

The above embodiments are provided to explain the purpose, technical solutions and advantages of the present application in further detail, and it should be understood that the above embodiments are merely illustrative of the present application and are not intended to limit the scope of the present application, and any modifications, equivalent substitutions, improvements and the like made on the basis of the technical solutions of the present application should be included in the scope of the present application.

Claims

1. A driving chip is characterized by comprising a first class of output pins and a second class of output pins, wherein the first class of output pins comprises a plurality of first output pin groups, each first output pin group comprises at least one first output pin, the second class of output pins comprises at least one second output pin group, and each second output pin group comprises at least one second output pin;

the first output pin is used for being connected with a fan-out lead of the first display panel or connected with a fan-out lead of the second display panel;

the second type output pin is used for being connected with the fan-out lead of the first display panel or disconnected with at least part of the fan-out lead of the second display panel;

the fan-out lead wire in the first display panel is arranged in a serial number which is different from the serial number of the data wire connected with the fan-out lead wire, and the fan-out lead wire in the second display panel is arranged in a serial number which is the same as the serial number of the data wire connected with the fan-out lead wire.

2. The driver chip according to claim 1, wherein the first type output pins and the second type output pins are arranged side by side on a same side of the driver chip;

in the direction pointing to the second type output pins along the first type output pins, the driving chip is provided with a central area and a first edge area and a second edge area which are positioned at two sides of the central area; the central area, the first edge area and the second edge area are distributed with the first output pin group, and the second output pin group is positioned in the central area.

3. The driver chip according to claim 1, wherein the second type of output pins includes a plurality of second output pin groups, and each second output pin group is located between two adjacent first output pin groups.

4. The driving chip according to claim 3, wherein the number of the second output pins included in each of the second output pin groups is equal.

5. The driver chip according to claim 2, wherein a plurality of the first output pin groups are disposed in the central region, and the number of the first output pins included in each of the first output pin groups in the central region is equal.

6. The driver chip according to claim 2, wherein the first output pin groups in the first edge region and the second edge region each include a greater number of first output pins than the first output pin groups in the central region.

7. The driver chip of claim 2, wherein the number of the second output pin groups is equal to the number of the first output pin groups in the central region; the number of the first output pin groups in the first edge region and the second edge region is 1.

8. The driver chip according to claim 1, wherein the total number of the second output pins in the second class of output pins is smaller than the total number of the first output pins in the first class of output pins.

9. The driver chip of claim 2, wherein the central region comprises a first central sub-region and a second central sub-region, the first central sub-region being located between the second central sub-region and the first edge region, the second central sub-region being located between the first central sub-region and the second edge region;

the number of the second set of output pins in the first hub subregion is equal to the number of the second set of output pins in the second hub subregion; the number of the first set of output pins in the first center sub-region is equal to the number of the first set of output pins in the second center sub-region.

10. The driver chip according to claim 9, wherein in the first center sub-region, an arrangement number of data lines to which the second output pins are connected through fan-out leads of the first display panel is smaller than an arrangement number of data lines to which the first output pins are connected through fan-out leads of the first display panel;

in the second central subregion, the arrangement serial number of the data lines connected by the second output pins through the fan-out leads of the first display panel is greater than the arrangement serial number of the data lines connected by the first output pins through the fan-out leads of the first display panel;

the arrangement serial numbers of the second output pins in the first central subarea are smaller than the arrangement serial numbers of the second output pins in the second central subarea.

11. The driver chip according to any one of claims 1 to 10, wherein a sequence change module and an output pin selection module are disposed in the driver chip;

the sequence changing module is used for sequentially changing first display data in an input first display data sequence according to a first corresponding relation between an arrangement serial number of each fan-out lead and an arrangement serial number of a data line connected with the fan-out lead when the driving chip is connected with the fan-out lead of the first display panel to obtain a second display data sequence so as to output the second display data in the second display data sequence to each fan-out lead; a second corresponding relationship exists between the arrangement serial numbers of the data lines corresponding to the first display data at the same position serial number and the arrangement serial numbers of the data lines corresponding to the second display data, and the first corresponding relationship is the same as the second corresponding relationship;

the output pin selection module is used for setting a second output pin disconnected from the fan-out lead wire to be in an invalid state when the driving chip is connected with the fan-out lead wire of the second display panel.

12. The driving chip according to claim 11, wherein a first enabling module is further disposed in the driving chip; the first enabling module is used for enabling the sequence changing module and disabling the output pin selecting module when the driving chip is connected with the fan-out lead of the first display panel;

or a second enabling module is further arranged in the driving chip; the second enabling module is used for enabling the output pin selection module and disabling the sequence changing module when the driving chip is connected with the fan-out lead of the second display panel.

13. A terminal device, comprising a display panel and the driving chip as claimed in any one of claims 1 to 12, wherein the data lines in the display panel are connected to the driving chip through fan-out leads, and the display panel is the first display panel or the second display panel.