CN115016583B - Low-voltage band-gap reference circuit - Google Patents
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Abstract
The invention discloses a low-voltage band gap reference circuit, which comprises a first-order band gap reference circuit, a first-order zero-temperature current circuit and a high-order band gap reference circuit, wherein the first-order zero-temperature current circuit is connected with the first-order zero-temperature current circuit; the first-order zero-temperature current circuit comprises: PMOS tube P5, resistor R2, amplifier U1 and OP circuit; the high-order bandgap reference circuit includes: PMOS tube P1, PMOS tube P2, PMOS tube P3, PMOS tube P4, NMOS tube NZ1, NMOS tube NZ2, NMOS tube NZ3, NMOS tube NZ4, NMOS tube N1, NMOS tube N2, NMOS tube N3, resistor R3, resistor Rc, triode Q3 and triode Q4; the invention provides a brand-new band-gap reference circuit architecture, and the integral minimum working voltage of the band-gap reference circuit can be 1.35V through verification, so that the lower power supply voltage requirement is effectively met.
Description
Technical Field
The invention relates to the technical field of band gap reference circuits, in particular to a low-voltage band gap reference circuit.
Background
The band gap reference circuit plays an extremely important role in a digital circuit or an analog circuit, the range of the working voltage of the band gap reference circuit is a key part which needs to be considered seriously when the band gap reference circuit is designed at present, and the range of the working voltage of the classical band gap reference circuit needs to be more than 4V to realize stable operation, so the range of the working voltage of the band gap reference circuit is gradually improved at present;
for example, patent No. 202111644099.5, entitled a band gap reference circuit, is provided with: the current bias module, the operational amplifier module, the current mirror structure and the resistor string can work under low power supply voltage;
through research on the current band-gap reference circuit, the band-gap reference circuit comprising the patent realizes a slightly lower working voltage than a typical band-gap reference circuit, but cannot meet the requirement of the market on the lower working voltage of the band-gap reference circuit; based on the current situation, there is an urgent need to reform the prior art.
Disclosure of Invention
The present invention is directed to a low-voltage bandgap reference circuit for solving the above-mentioned problems.
The invention provides a low-voltage band gap reference circuit, which comprises the following technical scheme: a first-order band gap reference circuit, a first-order zero-temperature current circuit and a high-order band gap reference circuit;
the first-order band-gap reference circuit is used for outputting currents IPTAT1, IPTAT2 and VBE (voltage biased by PTAT current) and VREF (first-order compensated band-gap reference voltage) which are proportional to absolute temperature;
the first-order zero-temperature current circuit comprises: PMOS tube P5, resistor R2, amplifier U1 and OP circuit;
the high-order bandgap reference circuit includes: PMOS tube P1, PMOS tube P2, PMOS tube P3, PMOS tube P4, NMOS tube NZ1, NMOS tube NZ2, NMOS tube NZ3, NMOS tube NZ4, NMOS tube N1, NMOS tube N2, NMOS tube N3, resistor R3, resistor Rc, triode Q3 and triode Q4;
as a preferred option of the invention, one path of IPTAT1 is loaded to the grid electrode of the NMOS tube NZ1, the other path of IPTAT1 is loaded to the emitter electrode of the triode Q4 through a resistor R3, and the IPTAT2 is loaded to the drain electrode of the NMOS tube N1; the VBE is loaded to the grid electrode of the NMOS tube NZ 3; the VREF is coupled to one input end of the amplifier U1;
as a preferred option of the invention, the sources of the PMOS tube P1, the PMOS tube P2, the PMOS tube P3, the PMOS tube P4, the PMOS tube P5 and the drain of the NMOS tube NZ1 are coupled to the power supply end VDD;
as a preferred option of the invention, the grid electrode of the PMOS tube P1 is coupled with the grid electrode of the PMOS tube P2, and the drain electrode of the PMOS tube P1 is coupled with the drain electrode of the NMOS tube NZ2;
as a preferred option of the invention, the grid electrode and the drain electrode of the PMOS tube P2 are in short circuit, and the drain electrode of the PMOS tube P2 is coupled with the drain electrode of the NMOS tube NZ 3;
as a preferred option of the invention, the grid electrode and the drain electrode of the PMOS tube P3 are in short circuit, and the drain electrode of the PMOS tube P3 is coupled with the drain electrode of the NMOS tube NZ 4;
as a preferred option of the invention, the grid electrode of the PMOS tube P4 is coupled with the grid electrode of the PMOS tube P5, one path of the drain electrode of the PMOS tube P4 is coupled with the grid electrode of the NMOS tube NZ4, and the other path of the drain electrode of the PMOS tube P4 is coupled with the emitter electrode of the triode Q3 through a resistor Rc;
as a preferred option of the invention, the sources of the NMOS tube NZ1 and the NMOS tube NZ2 are both coupled with the drain of the NMOS tube N2, and the drain and the grid of the NMOS tube NZ2 are in short circuit to output the band-gap reference voltage HPREF with high-order compensation;
as a preferred option of the invention, the sources of the NMOS tube NZ3 and the NMOS tube NZ4 are both coupled with the drain electrode of the NMOS tube N3, and the grid electrode of the NMOS tube NZ4 is coupled with the emitter electrode of the triode Q3 through a resistor Rc;
as a preferred option of the invention, the drain electrode of the NMOS tube N1 is coupled with the grid electrode of the NMOS tube N2 after being in short circuit, and the drain electrode of the NMOS tube N1 is also coupled with the grid electrode of the NMOS tube N3.
The invention has the following beneficial effects:
the invention provides a brand-new band gap reference circuit architecture, wherein a first-order band gap reference circuit loads output IPTAT1, IPTAT2, VBE and VREF into a first-order zero-temperature current circuit and a high-order band gap reference circuit, and the high-order band gap reference circuit outputs a high-order compensated band gap reference HPREF, and the integral minimum working voltage of the band gap reference circuit can be 1.35V through verification, so that the lower power supply voltage requirement is effectively met.
Drawings
FIG. 1 is a schematic diagram of the overall circuit structure of the present invention;
FIG. 2 is a schematic diagram of a first-order bandgap reference circuit according to an embodiment of the invention;
fig. 3 is a circuit schematic of an embodiment of the OP circuit of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the present invention without making any inventive effort fall within the scope of the present invention.
Referring to fig. 1, in a preferred embodiment, the low voltage bandgap reference circuit of the present embodiment comprises: a first-order band gap reference circuit, a first-order zero-temperature current circuit and a high-order band gap reference circuit;
the first-order bandgap reference circuit outputs currents IPTAT1, IPTAT2, VBE (voltage biased at PTAT current) and VREF (first-order compensated bandgap reference voltage) proportional to absolute temperature;
the first-order zero-temperature current circuit comprises: PMOS tube P5, resistor R2, amplifier U1 and OP circuit;
the high-order bandgap reference circuit includes: PMOS tube P1, PMOS tube P2, PMOS tube P3, PMOS tube P4, NMOS tube NZ1, NMOS tube NZ2, NMOS tube NZ3, NMOS tube NZ4, NMOS tube N1, NMOS tube N2, NMOS tube N3, resistor R3, resistor Rc, triode Q3 and triode Q4;
in an embodiment, one path of IPTAT1 is loaded to the gate of the NMOS tube NZ1, the other path is loaded to the emitter of the triode Q4 through the resistor R3, and the IPTAT2 is loaded to the drain of the NMOS tube N1; the VBE is loaded to the grid electrode of the NMOS tube NZ 3; the VREF is coupled to one input end of the amplifier U1;
in an embodiment, the sources of the PMOS transistors P1, P2, P3, P4, P5 and the drain of the NMOS transistor NZ1 are all coupled to the power supply terminal VDD, the gate of the PMOS transistor P1 is coupled to the gate of the PMOS transistor P2, the drain of the PMOS transistor P1 is coupled to the drain of the NMOS transistor NZ2, the gate and the drain of the PMOS transistor P2 are shorted, the drain of the PMOS transistor P2 is coupled to the drain of the NMOS transistor NZ3, the gate and the drain of the PMOS transistor P3 are shorted, and the drain of the PMOS transistor P3 is coupled to the drain of the NMOS transistor NZ 4; the grid electrode of the PMOS tube P4 is coupled with the grid electrode of the PMOS tube P5, one path of the drain electrode of the PMOS tube P4 is coupled with the grid electrode of the NMOS tube NZ4, and the other path of the drain electrode of the PMOS tube P4 is coupled with the emitter electrode of the triode Q3 through a resistor Rc;
in an embodiment, sources of the NMOS tube NZ1 and the NMOS tube NZ2 are coupled to a drain of the NMOS tube N2, and the drain and the gate of the NMOS tube NZ2 are shorted to output a band gap reference voltage HPREF with high-order compensation; the sources of the NMOS tube NZ3 and the NMOS tube NZ4 are both coupled with the drain electrode of the NMOS tube N3, and the grid electrode of the NMOS tube NZ4 is coupled with the emitter electrode of the triode Q3 through a resistor Rc; the drain electrode of the NMOS tube N1 is coupled with the grid electrode of the NMOS tube N2 after being in short circuit with the grid electrode, and the drain electrode of the NMOS tube N1 is also coupled with the grid electrode of the NMOS tube N3;
in an embodiment, the collector of the triode Q4, the source of the NMOS transistor N1, the source of the NMOS transistor N2, the source of the NMOS transistor N3, the base of the triode Q3, and the collector are all coupled to the power supply terminal VSS;
in the embodiment, one path of the drain electrode of the PMOS transistor P5 is coupled to the resistor R2, and the other path is loaded to one path of input end of the amplifier U1; the grid electrode of the PMOS tube P5 is coupled with the output end of the amplifier U1;
in an embodiment, the indexes of all MOS transistors are based on common parameters of 5V MOSFETs, and specifically vary according to the selected process.
Referring to fig. 2 and 3, the present invention provides another embodiment for illustrating the inference that the present invention achieves an operating voltage below 1.5V, wherein in embodiments, the present invention may employ various first-order bandgap reference circuits and OP circuits, the embodiment providing a first-order bandgap reference circuit as shown in fig. 2 and an OP circuit as shown in fig. 3;
in an embodiment, the first-order bandgap reference circuit outputs currents IPTAT1 and IPTAT2, VBE (voltages biased at PTAT currents), VREF (first-order compensated bandgap reference voltage) proportional to absolute temperature, wherein the width-to-length ratio N2 of MOS transistors N2 and N3: n3=a: 1, wherein a is a variable;
the width-to-length ratio of the MOS tube NZ1 to the NZ2 is 1:1, namely NZ1=NZ2; the width-to-length ratio of the MOS tube NZ3 to the NZ4 is 1:1, namely NZ3=NZ4, and the width-to-length ratio of the MOS tube NZ4 to the NZ1 NZ1=B1, wherein B is a variable; the width-to-length ratio P1 of the MOS tubes P1 and P2 is that P2 = A ':1, wherein A ' is a variable identical to A in the width-to-length ratio of the MOS tubes N2 and N3, namely A = A ', and the subsequent formulas uniformly use A; wherein, NZ1, NZ2, NZ3 and NZ4 are NMOS tubes with zero threshold;
the saturation current formula of the MOS tube is known:
I D ＝S*K′*(V GS -V TH ) 2
wherein K' is a fixed technological parameter, S is the width-to-length ratio of the MOS tube, V GS Is MOS tube gate source voltage, V TH Is the threshold voltage of the MOS tube;
so that:
S NZ1 *K′*(V GS_NZ1 -V TH ) 2 +S NZ2 *K′*(V GS_NZ2 -V TH ) 2 ＝I N2 (N2 paths of current) formula (1);
S NZ3 *K′*(V GS_NZ3 -V TH ) 2 +S NZ4 *K′*(V GS_NZ4 -V TH ) 2 ＝I N3 (N3 paths of current) formula (2);
from the above known, the width-to-length ratio nz4:nz1=b:1 of the MOS tube NZ4 to NZ1 is represented by formula (3);
therefore, B is S NZ1 ＝B*S NZ2 ＝S NZ3 ＝S Nz4 Formula (4);
it is known that: the width-to-length ratio P1:P2=A':1=A:1 of the MOS tubes P1 and P2 is uniformly used as A;
therefore S NZ2 *K′*(V GS_NZ2 -V TH ) 2 ＝A*S NZ3 *K′*(V GS_NZ3 -V TH ) 2 Formula (5);
namely: a.b. (V GS_NZ3 -V TH ) 2 ＝(V GS_NZ2 -V TH ) 2 Formula (6);
substituting to obtain: s is S NZ1 *K′*(V GS_NZ1 -V TH ) 2 +A*S NZ3 *K′*(V GS_NZ3 -V TH ) 2 ＝I N2 Formula (7);
known I N2 ∶I N3 =a:1, and will be substituted to:
A*B*(V GS_NZ4 -V TH ) 2 ＝(V GS_NZ1 -V TH ) 2 formula (8);
the method can obtain:
namely:
V G_NZ2 ＝HPREF
V G_NZ1 ＝V BE_Q4 +I PTAT *R3
the basic formula of the triode can be known as follows:
wherein V is G0 Is the bandgap voltage of silicon in the triode at zero K temperature; η is a process related constant; t is the working temperature; t (T) r Is the reference temperature, α is the temperature order of the temperature dependent collector current; />K is boltzmann constant and q is electron charge.
IN fig. 1, an OP circuit and a PMOS transistor P5 form a negative feedback loop, VREF is input to a negative input terminal IN of the OP circuit, a positive input terminal IP of the OP is connected with a drain electrode of the PMOS transistor P5, when IP increases, an output terminal of the OP circuit increases, a drain electrode of the PMOS transistor P5 becomes low, IP is returned, the IP is turned down, negative feedback is realized, and by a virtual short principle of the OP circuit, ip=in, a current flowing through the PMOS transistor P5 is VREF/R2, because gates and sources of the PMOS transistor P4 and the PMOS transistor P5 are the same, and the sizes are the same, a current flowing through the PMOS transistor P4, that is, a current flowing through the Q3 is VREF/R2, is approximately zero temperature current, and α is equal to or greater than 0.
Because the current through transistor Q1 in FIG. 2 is PTAT current, α is 1, and therefore,
then there is
So that the number of the parts to be processed,
in an embodiment, I PTAT1 * R3 can compensate V BE_Q4 The first-order temperature coefficient (i.e)；
In the case of an embodiment of the present invention,can compensate V BE_Q4 Middle-high order temperature coefficient (i.e.)>)；
Thus, a high order compensated bandgap reference HPREF can be obtained by formulaic calculation.
In the embodiment, it should be emphasized that the typical reference voltage is similar to the Bandgap voltage of silicon, and the typical Bandgap reference is obtained by using the sum of a voltage with a positive temperature coefficient and a voltage with a negative temperature coefficient, where the temperature coefficients cancel each other to realize a voltage reference independent of temperature, VREF is greater than or equal to 1.2V, and in fact, some Bandgap structure output voltages can be adjusted, so that the Bandgap reference is not limited to 1.2V; vdsat=vgs-VTH, basically a fixed value selected during design, and VDAST generally takes a voltage depending on the current and the size of the tube, and generally 0.15-0.2V is selected during design of the amplifier to achieve a better effect;
in this embodiment, if vdsat=0.15v is taken, and the first-order bandgap reference circuit of fig. 2 and the OP example circuit of fig. 3 are combined, the lowest operating voltage of the first-order bandgap reference circuit is:
VREF+VDSAT_PM1≥1.35V
therefore, the lowest operating voltage of the first-order zero-temperature current circuit is:
VREF+VDSAT_P5≥1.35V
therefore, the lowest operating voltage of the higher order bandgap reference circuit is:
HPREF+VDSAT_P1≥1.35V
in this embodiment, if vdsat=0.2v is taken, and the first-order bandgap reference circuit of fig. 2 and the OP example circuit of fig. 3 are combined, the lowest operating voltage of the first-order bandgap reference circuit is:
VREF+VDSAT_PM1≥1.4V
therefore, the lowest operating voltage of the first-order zero-temperature current circuit is:
VREF+VDSAT_P5≥1.4V
therefore, the lowest operating voltage of the higher order bandgap reference circuit is:
HPREF+VDSAT_P1≥1.4V
where VREF is a first-order compensated bandgap reference voltage, VDSAT_PM1 is the saturation voltage of PM1, VDSAT_P5 is the saturation voltage of P5, VDSAT_P1 is the saturation voltage of P1, and HPREF is a high-order compensated bandgap reference voltage. The saturation voltage (drain saturation voltage, vdsat) is Vds corresponding to the fact that the leakage current of the transistor is not affected by the change of Vds, and Vdsat is not an actual voltage value of the transistor, but is used to determine how much margin is left from the saturation region.
Therefore, the lowest working voltage of the whole framework is the reference voltage plus the drain-source voltage of a PMOS, and the lower power supply voltage requirement is realized under the conventional band-gap reference voltage, namely, the whole voltage is more than or equal to 1.35V.
Although the present invention has been described with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described, or equivalents may be substituted for elements thereof, and any modifications, equivalents, improvements and changes may be made without departing from the spirit and principles of the present invention.
Claims (10)
1. A low-voltage bandgap reference circuit comprises a first-order bandgap reference circuit; the first-order band gap reference circuit outputs currents IPTAT1 and IPTAT2 which are proportional to absolute temperature; the first-order bandgap reference circuit also outputs a voltage VBE biased at the PTAT current; the first-order band-gap reference circuit also outputs a first-order compensated band-gap reference voltage VREF;
the method is characterized in that the lowest working voltage of the whole circuit for realizing the band gap reference circuit is more than or equal to 1.35V;
the bandgap reference circuit further includes: a first order zero temperature current circuit, a high order bandgap reference circuit;
the first-order zero-temperature current circuit comprises: PMOS tube P5, resistor R2, amplifier U1 and OP circuit;
the high-order bandgap reference circuit includes: PMOS tube P1, PMOS tube P2, PMOS tube P3, PMOS tube P4, NMOS tube NZ1, NMOS tube NZ2, NMOS tube NZ3, NMOS tube NZ4, NMOS tube N1, NMOS tube N2, NMOS tube N3, resistor R3, resistor Rc, triode Q3 and triode Q4;
one path of IPTAT1 is loaded to the grid electrode of the NMOS tube NZ1, the other path of IPTAT1 is loaded to the emitter electrode of the triode Q4 through a resistor R3, and the IPTAT2 is loaded to the drain electrode of the NMOS tube N1; the VBE is loaded to the grid electrode of the NMOS tube NZ 3; the VREF is coupled to one input end of the amplifier U1;
the grid electrode of the PMOS tube P1 is coupled with the grid electrode of the PMOS tube P2, and the drain electrode of the PMOS tube P1 is coupled with the drain electrode of the NMOS tube NZ2; the grid electrode and the drain electrode of the PMOS tube P2 are in short circuit, and the drain electrode of the PMOS tube P2 is coupled with the drain electrode of the NMOS tube NZ 3; the grid electrode and the drain electrode of the PMOS tube P3 are in short circuit, and the drain electrode of the PMOS tube P3 is coupled with the drain electrode of the NMOS tube NZ 4; the grid electrode of the PMOS tube P4 is coupled with the grid electrode of the PMOS tube P5, one path of the drain electrode of the PMOS tube P4 is coupled with the grid electrode of the NMOS tube NZ4, and the other path of the drain electrode of the PMOS tube P4 is coupled with the emitter electrode of the triode Q3 through a resistor Rc;
the sources of the NMOS tube NZ1 and the NMOS tube NZ2 are both coupled with the drain electrode of the NMOS tube N2, and the drain electrode and the grid electrode of the NMOS tube NZ2 are in short circuit to output high-order compensated band gap reference voltage HPREF; the sources of the NMOS tube NZ3 and the NMOS tube NZ4 are both coupled with the drain electrode of the NMOS tube N3, and the grid electrode of the NMOS tube NZ4 is coupled with the emitter electrode of the triode Q3 through a resistor Rc; the drain electrode of the NMOS tube N1 is coupled with the grid electrode of the NMOS tube N2 after being in short circuit with the grid electrode, and the drain electrode of the NMOS tube N1 is also coupled with the grid electrode of the NMOS tube N3;
one path of the drain electrode of the PMOS tube P5 is coupled with the resistor R2, and the other path of the drain electrode is loaded to one path of input end of the amplifier U1; and the grid electrode of the PMOS tube P5 is coupled with the output end of the amplifier U1.
2. The low voltage bandgap reference circuit of claim 1, wherein: the sources of the PMOS tube P1, the PMOS tube P2, the PMOS tube P3, the PMOS tube P4 and the PMOS tube P5 and the drain of the NMOS tube NZ1 are coupled to the power supply end VDD.
3. The low voltage bandgap reference circuit of claim 1, wherein: the collector of the triode Q4, the source of the NMOS tube N1, the source of the NMOS tube N2, the source of the NMOS tube N3, the base of the triode Q3 and the collector are all coupled with the power supply end VSS.
4. The low voltage bandgap reference circuit of claim 1, wherein: the width-to-length ratios of the NMOS tube NZ1, the NMOS tube NZ2, the NMOS tube NZ3 and the NMOS tube NZ4 are as follows: b is 1:1, wherein B is a variable.
5. The low voltage bandgap reference circuit of claim 1, wherein: the width-to-length ratio N2 of the NMOS transistors N2 and N3 is as follows: n3=a: 1, wherein a is a variable.
6. The low voltage bandgap reference circuit of claim 5, wherein: the width-to-length ratio p1:p2=a ':1 of the PMOS transistors P1 and P2, wherein a ' is a variable having the same value as a in the width-to-length ratio of the NMOS transistors N2 and N3, i.e., a ' =a.
7. The low voltage bandgap reference circuit of claim 1, wherein: the NMOS transistors NZ1, NZ2, NZ3 and NZ4 are NMOS transistors with zero threshold.
8. The low voltage bandgap reference circuit of claim 1, wherein: the calculation formula of the band gap reference voltage HPREF for high order compensation is:
I PTAT * R3 is used for compensating V BE_Q4 A first-order temperature coefficient;
for compensating V BE_Q4 Medium and high order temperature coefficients;
wherein V is BE_Q4 Base emitter voltage for transistor Q4 biased at PTAT current, I PTAT For a current proportional to absolute temperature,k is Boltzmann constant, q is electron charge, T is working temperature; t (T) r Is the reference temperature.
9. The low voltage bandgap reference circuit of claim 1, wherein: the saturation current formula of the NMOS tube N2 is: i N2 ＝S NZ1 *K′*V GS_NZ1 -V TH ) 2 +S Nz2 *K′*V GS_NZ2 -V TH ) 2 ；
The saturation current formula of the NMOS tube N3 is: i N3 ＝S NZ3 *K′*V GS_NZ3 -V TH ) 2 +S NZ4 *K′*(V GS_NZ4 -V TH ) 2 ；
Wherein K' is a fixed technological parameter, S is the width-to-length ratio of the MOS tube, V GS Is MOS tube gate source voltage, V TH Is the threshold voltage of the MOS tube.
10. The low voltage bandgap reference circuit of claim 1, wherein: the lowest working voltage of the first-order band gap reference circuit is as follows:
VREF+VDSAT_PM1≥1.35V；
the lowest working voltage of the first-order zero-temperature current circuit is as follows:
VREF+VDSAT_P5≥1.35V；
the lowest working voltage of the high-order band gap reference circuit is as follows:
HPREF+VDSAT_P1≥1.35V；
wherein VREF is a first-order compensated bandgap reference voltage, VDSAT_PM1 is a saturation voltage of a PM1 MOS tube in the first-order bandgap reference circuit, VDSAT_P5 is a saturation voltage of P5, VDSAT_P1 is a saturation voltage of P1, and HPREF is a high-order compensated bandgap reference voltage.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102981545A (en) * | 2012-12-03 | 2013-03-20 | 东南大学 | Band gap reference voltage circuit with high-order curvature compensation |
| CN104714588A (en) * | 2015-01-05 | 2015-06-17 | 江苏芯力特电子科技有限公司 | Low temperature drift band-gap reference voltage source based on VBE linearization |
| CN107066006A (en) * | 2017-05-05 | 2017-08-18 | 中国科学院微电子研究所 | Novel band gap reference circuit structure |
| CN107861557A (en) * | 2017-11-01 | 2018-03-30 | 重庆邮电大学 | A kind of metal-oxide-semiconductor realizes the high-order temperature compensation bandgap reference circuit of diode |
| CN112034921A (en) * | 2020-09-02 | 2020-12-04 | 重庆邮电大学 | High-order band-gap reference circuit based on transconductance linear loop technology |
| DE102020214185A1 (en) * | 2019-12-12 | 2021-06-17 | Robert Bosch Gesellschaft mit beschränkter Haftung | Temperature compensated band gap reference circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8149047B2 (en) * | 2008-03-20 | 2012-04-03 | Mediatek Inc. | Bandgap reference circuit with low operating voltage |
| CN109725672B (en) * | 2018-09-05 | 2023-09-08 | 南京浣轩半导体有限公司 | Band gap reference circuit and high-order temperature compensation method |
-
2022
- 2022-06-16 CN CN202210683541.3A patent/CN115016583B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102981545A (en) * | 2012-12-03 | 2013-03-20 | 东南大学 | Band gap reference voltage circuit with high-order curvature compensation |
| CN104714588A (en) * | 2015-01-05 | 2015-06-17 | 江苏芯力特电子科技有限公司 | Low temperature drift band-gap reference voltage source based on VBE linearization |
| CN107066006A (en) * | 2017-05-05 | 2017-08-18 | 中国科学院微电子研究所 | Novel band gap reference circuit structure |
| CN107861557A (en) * | 2017-11-01 | 2018-03-30 | 重庆邮电大学 | A kind of metal-oxide-semiconductor realizes the high-order temperature compensation bandgap reference circuit of diode |
| DE102020214185A1 (en) * | 2019-12-12 | 2021-06-17 | Robert Bosch Gesellschaft mit beschränkter Haftung | Temperature compensated band gap reference circuit |
| CN112034921A (en) * | 2020-09-02 | 2020-12-04 | 重庆邮电大学 | High-order band-gap reference circuit based on transconductance linear loop technology |
Non-Patent Citations (1)
| Title |
|---|
| 一种高精度高阶曲率补偿型带隙基准电压源;张兵峰;魏廷存;郑然;陈升;;液晶与显示;20081015(第05期);全文 * |
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