CN115015733A - Circuit for chip to enter test mode and method for judging chip to enter test mode - Google Patents
Circuit for chip to enter test mode and method for judging chip to enter test mode Download PDFInfo
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- CN115015733A CN115015733A CN202210599265.2A CN202210599265A CN115015733A CN 115015733 A CN115015733 A CN 115015733A CN 202210599265 A CN202210599265 A CN 202210599265A CN 115015733 A CN115015733 A CN 115015733A
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- G01R31/2851—Testing of integrated circuits [IC]
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Abstract
The application provides a circuit for a chip to enter a test mode and a method for judging the chip to enter the test mode, wherein the circuit comprises: the switch, the signal adjusting unit and the transmission unit are connected with an input pin and a preset pin of the chip; the signal adjusting unit and the transmission unit are respectively connected with an input pin of the chip; the signal adjusting unit is used for adjusting the signal of the input pin according to the received preset pulse signal; the transmission unit is used for transmitting the signal of the input pin to the output end when receiving the enabling signal, so that the chip enters a test mode, namely, the bare chip after the packaging and routing are added can enter the test mode to test, and the problem that the chip cannot be normally used due to the fact that the chip parameter is deviated due to the fact that parasitic capacitance, inductance and resistance are introduced after the packaging and routing are added is avoided.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a circuit for a chip to enter a test mode and a method for judging the chip to enter the test mode.
Background
Along with the development of society, chips are more and more common in people's lives, and mobile phones, computers, smart sound boxes and other terminal devices utilizing the chips to support corresponding functions are more and more diversified, and the chips are more and more valued by people due to the advantages of small size, large-scale integration, high processing performance and the like.
Before the chip is delivered to a client, the chip needs to pass a Final Test (Final Test) before delivery, and the coverage rate of the Test is the guarantee that the chip can not be used at the client side without problems. Currently, it is common to add a wafer test (CP), i.e. before the wafer is unpackaged, to ensure that each die (die) after wafer dicing can meet the characteristics or design specifications of the device.
Although wafer testing can cover almost all chip test items, in practical applications, additional packaging and wire bonding are required for the die after wafer testing, which introduces parasitic capacitance, inductance and resistance at the chip pins. For a chip sensitive to parasitic, the deviation of the chip parameters tested by the wafer may occur, and the normal function may be affected.
Disclosure of Invention
Therefore, the circuit for the chip to enter the test mode and the method for judging the chip to enter the test mode can enable the bare chip added with the package and the routing to enter the test mode for testing, so that the problem that the chip cannot be normally used due to deviation of chip parameters caused by parasitic capacitance, inductance and resistance introduced after the package and the routing are added is solved.
In order to achieve the above object, the embodiments of the present invention provide the following technical solutions:
the application discloses in a first aspect, a circuit for a chip to enter a test mode, comprising: the switch, the signal adjusting unit and the transmission unit are connected with an input pin and a preset pin of the chip;
the signal adjusting unit and the transmission unit are respectively connected with an input pin of the chip;
the signal adjusting unit is used for adjusting the signal of the input pin according to the received preset pulse signal;
the transmission unit is used for transmitting the signal of the input pin to an output end when receiving an enabling signal, so that the chip enters a test mode.
Optionally, in the above circuit in which the chip enters the test mode, if the preset pin is a power pin of the chip, the signal adjusting unit includes: a first resistor and a first switch tube;
one end of the first resistor is used as an input end of the signal adjusting unit and is connected with an input pin of the chip;
the other end of the first resistor is connected with the second end of the first switch tube, the control end of the first switch tube receives the preset pulse signal, and the first end of the first switch tube is grounded.
Optionally, in the above circuit for entering the test mode of the chip, the first switch tube is an NMOS tube.
Optionally, in the above circuit in which the chip enters the test mode, if the preset pin is a ground pin of the chip, the signal adjusting unit includes: the second resistor, the first inverter and the second switch tube;
one end of the second resistor is used as an input end of the signal adjusting unit and is connected with an input pin of the chip;
the input end of the first phase inverter receives the preset pulse signal, and the output end of the first phase inverter is connected with the control end of the second switching tube;
the second end of the second switch tube is connected with the other end of the second resistor, and the first end of the second switch tube is connected with an input power supply.
Optionally, in the circuit in which the chip enters the test mode, the second preset pin is a ground pin of the chip, and the PMOS transistor of the second switch transistor is provided.
Optionally, in the above circuit for entering the test mode of the chip, the transmission unit includes: one end of the transmission gate is used as the input end of the transmission unit and is connected with the input pin of the chip; the other end of the transmission gate is used as the output end of the transmission unit, and the control end of the transmission gate receives the enabling signal.
A second aspect of the present application discloses a method for determining that a chip enters a test mode, which is applied to a circuit of any one of the first aspect, where the chip enters the test mode, and the method includes:
determining a preset pin which needs to be connected with an input pin of the chip;
judging whether the output of a transmission unit in a circuit of the chip entering a test mode meets a preset judgment condition corresponding to the preset pin;
if the judgment result is yes, judging that the chip enters a test mode;
if the judgment result is negative, the chip is judged to enter the test mode.
Optionally, in the method for determining that a chip enters a test mode, if the preset pin is a power pin of the chip, an output of a transmission unit in a circuit where the chip enters the test mode meets a preset determination condition corresponding to the preset pin, where the preset determination condition includes:
if a signal adjusting unit in a circuit of the chip entering a test mode receives a preset pulse signal as a single pulse signal, the output of the transmission unit is a high level;
if the preset pulse signal received by the signal adjusting unit in the circuit of the chip entering the test mode is a multi-pulse signal, the output of the transmission unit is high level in each pulse signal period.
Optionally, in the method for determining that the chip enters the test mode, if the preset pin is a ground pin of the chip, an output of a transmission unit in a circuit where the chip enters the test mode meets a preset determination condition corresponding to the preset pin, where the preset determination condition includes:
if a signal adjusting unit in a circuit of the chip entering a test mode receives a preset pulse signal as a single pulse signal, the output of the transmission unit is a low level;
if the preset pulse signal received by the signal adjusting unit in the circuit of the chip entering the test mode is a multi-pulse signal, the output of the transmission unit is low level in each pulse signal period.
Optionally, in the method for determining that a chip enters a test mode, after determining a preset pin that needs to be connected to an input pin of the chip, the method further includes:
inputting a preset judgment signal to an input pin of the chip;
judging whether the output of a transmission unit in a circuit of the chip entering a test mode is the same as the pulse width of the preset judgment signal or not;
if the judgment result is yes, judging that the chip enters a test mode;
if the judgment result is negative, the chip is judged not to enter the test mode.
Based on the circuit that the chip provided by the invention enters the test mode, the circuit comprises: the switch, the signal adjusting unit and the transmission unit are connected with an input pin and a preset pin of the chip; the signal adjusting unit and the transmission unit are respectively connected with an input pin of the chip; the signal adjusting unit is used for adjusting the signal of the input pin according to the received preset pulse signal; the transmission unit is used for transmitting the signal of the input pin to the output end when receiving the enabling signal, so that the chip enters a test mode, namely, the bare chip after the package and the routing are added can enter the test mode to be tested, and the problem that the parasitic capacitance, the inductance and the resistance introduced after the package and the routing are added cause the deviation of the chip parameters, so that the chip cannot be normally used is avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a peripheral circuit diagram of a circuit for a chip to enter a test mode according to an embodiment of the present application;
fig. 2 is an internal circuit diagram of a circuit for entering a test mode of a chip according to an embodiment of the present application;
FIG. 3 is a circuit diagram illustrating the periphery of another circuit for entering a test mode of a chip according to an embodiment of the present disclosure;
FIG. 4 is a circuit diagram illustrating an internal circuit of another circuit for entering a test mode of a chip according to an embodiment of the present disclosure;
fig. 5 is a flowchart of a method for determining that a chip enters a test mode according to an embodiment of the present disclosure;
fig. 6 is a flowchart of another method for determining that a chip enters a test mode according to an embodiment of the present disclosure;
fig. 7 is a schematic pin diagram of a chip according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the application provides a circuit for a chip to enter a test mode, so that a bare chip after packaging and routing are added can enter the test mode to be tested, and the problem that the chip cannot be normally used due to deviation of chip parameters caused by parasitic capacitance, inductance and resistance introduced after packaging and routing are added is solved.
Referring to fig. 1 and 2, or fig. 3 and 4, the circuit for entering the test mode of the chip may include: a switch (S1 in fig. 1, S2 in fig. 2) connecting the input pin of the chip and the predetermined pin, a signal adjusting unit and a transmission unit.
It should be noted that the switch connecting the input pin of the chip and the preset pin may be disposed on the periphery of the chip, that is, in the case shown in fig. 1 or fig. 3.
The signal adjusting unit and the transmission unit are respectively connected with an input pin of the chip.
It should be noted that the signal adjusting unit and the transmitting unit may be disposed in an internal circuit of the chip, that is, in the case shown in fig. 2 or fig. 4.
The signal adjusting unit is used for adjusting the signal of the input pin according to the received preset pulse signal.
In practical applications, as shown in fig. 1, if the predetermined pin is the power pin VDD of the chip, as shown in fig. 2, the signal adjusting unit may include: a first resistor R1 and a first switch MN 1. One end of the first resistor R1 is used as an input end of the signal adjusting unit and is connected with an input pin IN of the chip; the other end of the first resistor R1 is connected to the second end of the first switch tube MN1, the control end of the first switch tube MN1 receives the preset PULSE signal INIT _ PULSE, and the first end of the first switch tube MN1 is grounded.
Specifically, the first switch MN1 may be an NMOS transistor; the first end of the first switch tube MN1 is a source, i.e. the end with an arrow in the figure; the second end of the first switch tube MN1 is a drain, i.e. the end without an arrow in the figure; the control terminal of the first switch tube MN1 is a gate.
However, as shown in fig. 3, if the predetermined pin is the ground pin GND of the chip, as shown in fig. 4, the signal adjusting unit may include: a second resistor R2, a first inverter QI and a second switch MP 1. One end of the second resistor R2 is used as the input end of the signal adjusting unit and is connected with the input pin IN of the chip; the input end of the first phase inverter QI receives a preset PULSE signal INIT _ PULSE, and the output end of the first phase inverter QI is connected with the control end of the second switching tube MP 1; a second terminal of the second switch MP1 is connected to the other terminal of the second resistor R2, and a first terminal of the second switch MP1 is connected to the input power VDD.
Specifically, the second switch MP1 can be a PMOS transistor; the first end of the second switch MP1 is a source, i.e. the end with an arrow in the figure; the second terminal of the second switch MP1 is the drain, i.e. the terminal without arrow in the figure; the control terminal of the second switch MP1 is a gate.
It should be noted that the preset pulse signal may be a single pulse signal for power-on initialization of the chip, or may be a set of multiple single pulse signals, which is determined according to a specific application environment and a user requirement, and both belong to the protection scope of the present application.
The transmission unit is used for transmitting the signal of the input pin to the output end when receiving the enabling signal so as to enable the chip to enter a test mode.
In practical applications, as also shown in fig. 2 or fig. 4, the transmission unit may include: one end of the transmission gate buffer is used as the input end of the transmission unit and is connected with an input pin IN of the chip; the other end of the transmission gate buffer is used as the output end of the transmission unit, and the control end of the transmission gate receives the enable signal EN.
When the control end of the transmission gate buffer receives the enable signal EN at high level, that is, EN is 1, the transmission gate buffer transmits the signal at the input end to the output end.
Based on the above principle, the circuit for the chip to enter the test mode provided by this embodiment includes: the switch, the signal adjusting unit and the transmission unit are connected with an input pin and a preset pin of the chip; the signal adjusting unit and the transmission unit are respectively connected with an input pin of the chip; the signal adjusting unit is used for adjusting the signal of the input pin according to the received preset pulse signal; the transmission unit is used for transmitting the signal of the input pin to the output end when receiving the enabling signal, so that the chip enters a test mode, namely, the bare chip after the package and the routing are added can enter the test mode to be tested, and the problem that the parasitic capacitance, the inductance and the resistance introduced after the package and the routing are added cause the deviation of the chip parameters, so that the chip cannot be normally used is avoided.
It should be noted that, with the circuit for entering the test mode by the chip provided in the embodiment of the present application, it is not necessary to separately set a test pin on the chip, and the chip can enter the test mode by multiplexing the pin carried by the chip itself through the circuit to execute the subsequent test on the chip, so as to avoid the problem of increased circuit scale and increased cost of the chip caused by specially setting the test pin. IN addition, the circuit for the chip to enter the test mode can also enter the test mode under fewer pins, for example, the chip shown IN fig. 7 only has the input pin IN, the output pin OUT, the power pin VDD and the ground pin GND, and compared with the wafer test, the coverage rate of the chip test can be improved.
Based on the circuit for entering the test mode of the chip provided in the foregoing embodiment, another embodiment of the present application further provides a method for determining that the chip enters the test mode, where the method is applicable to the circuit for entering the test mode of the chip described in any of the foregoing embodiments, please refer to fig. 5, and the method may include the following steps:
s100, determining a preset pin which needs to be connected with an input pin of the chip.
Wherein, predetermine the pin and include: a power pin and a ground pin of the chip; of course, the present invention is not limited to this, and may be determined according to the specific application environment and the user's requirement, and the present application does not specifically limit the present invention, and all of them belong to the protection scope of the present application.
S102, judging whether the output of a transmission unit in a circuit of the chip entering the test mode meets a preset judgment condition corresponding to a preset pin.
In practical applications, if the preset pin is a power pin of the chip, the output of the transmission unit in the circuit in the test mode of the chip meets, and the preset determination condition corresponding to the preset pin may be as follows:
a1, if the signal adjustment unit in the circuit of the chip entering the test mode receives the preset pulse signal as a single pulse signal, the output of the transmission unit is high level.
a2, if the preset pulse signal received by the signal adjusting unit in the circuit of the chip entering the test mode is a multi-pulse signal, the output of the transmission unit is high level in each pulse signal period.
However, if the preset pin is a ground pin of the chip, the output of the transmission unit in the circuit in which the chip enters the test mode satisfies the preset determination condition corresponding to the preset pin, which may be as follows:
b1, if the signal adjusting unit in the circuit of the chip entering the test mode receives the preset pulse signal as a single pulse signal, the output of the transmission unit is low level.
b2, if the preset pulse signal received by the signal adjusting unit in the circuit of the chip entering the test mode is a multi-pulse signal, the output of the transmission unit is low level in each pulse signal period.
If the determination result is yes, that is, the output of the transmission unit in the circuit in which the chip enters the test mode is determined to meet the preset determination condition corresponding to the preset pin, then step S104 is executed; if the determination result is negative, that is, the output of the transmission unit in the circuit where the chip enters the test mode is determined not to satisfy the preset determination condition corresponding to the preset pin, step S106 is executed.
S104, judging that the chip enters a test mode.
In practical application, if it is determined that the output of the transmission unit in the circuit in which the chip enters the test mode satisfies the preset determination condition corresponding to the preset pin, that is, when the preset pin is the power pin of the chip, the signal adjustment unit in the circuit in which the chip enters the test mode receives the preset pulse signal as a single pulse signal, and the output of the transmission unit is at a high level; or, if the signal adjusting unit in the circuit that the chip enters the test mode receives the preset pulse signal as a multi-pulse signal, the output of the transmission unit is high level during each pulse signal period, and the chip can be judged to enter the test mode.
However, when the preset pin is the ground pin of the chip, the signal adjusting unit in the circuit in which the chip enters the test mode receives the preset pulse signal as a single pulse signal, and the output of the transmission unit is a low level; or, the signal adjusting unit in the circuit that the chip enters the test mode receives the preset pulse signal as a multi-pulse signal, and the output of the transmission unit is low level during each pulse signal period, so that the chip can be judged to enter the test mode.
S106, judging that the chip does not enter the test mode.
In practical application, if it is determined that the output of the transmission unit in the circuit in which the chip enters the test mode does not satisfy the preset determination condition corresponding to the preset pin, that is, when the preset pin is the power pin of the chip, the signal adjustment unit in the circuit in which the chip enters the test mode receives the preset pulse signal as a single pulse signal, and the output of the transmission unit is a low level; or, the signal adjusting unit in the circuit that the chip enters the test mode receives the preset pulse signal as a multi-pulse signal, and the output of the transmission unit is low level during each pulse signal period, so that the chip can be judged not to enter the test mode.
When the preset pin is the grounding pin of the chip, the signal adjusting unit in the circuit of the chip entering the test mode receives the preset pulse signal as a single pulse signal, and the output of the transmission unit is high level; or, the signal adjusting unit in the circuit that the chip enters the test mode receives the preset pulse signal as a multi-pulse signal, and the output of the transmission unit is high level during each pulse signal period, so that the chip is judged not to enter the test mode.
Based on the above principle, the method for determining that a chip enters a test mode provided in this embodiment can determine whether the output of a transmission unit in a circuit in which the chip enters the test mode satisfies a preset determination condition corresponding to a preset pin after determining the preset pin to be connected to an input pin of the chip; if the judgment result is yes, judging that the chip enters a test mode; if the judgment result is negative, the chip is judged not to enter the test mode, namely, whether the circuit of the chip entering the test mode can send the chip into the test mode in the power-on initialization stage or not can be judged through the judgment method.
Optionally, in another embodiment provided by the present application, after step S100 is executed to determine a preset pin required to be connected to an input pin of a chip, please refer to fig. 6, where the method for determining that the chip enters the test mode may further include the following steps:
s200, inputting a preset judgment signal to an input pin of the chip.
In practical application, during the period of presetting the pulse signal, a strong square wave signal with a period far smaller than the pulse width of the preset pulse signal can be input to an input pin of the chip from the outside; or, in the starting test stage, a strong square wave signal with a period far smaller than the pulse width of the preset pulse signal is always input to the input pin of the chip from the outside.
It should be noted that, the specific value of the pulse width of the preset determination signal may be determined according to the specific application environment and the user requirement, and the present application is not limited specifically, and all belong to the protection scope of the present application.
S202, judging whether the output of a transmission unit in the circuit of the chip entering the test mode is the same as the pulse width of a preset judgment signal or not.
In practical application, when the pulse signal is preset, the transmission unit transmits the signal of the chip input pin to the output end of the transmission unit, and whether the chip enters the test mode can be judged by judging whether the output of the transmission unit in the circuit for the chip entering the test mode is the same as the pulse width of the preset judgment signal.
If the determination result is yes, that is, the output of the transmission unit in the circuit where the chip enters the test mode is determined to be the same as the pulse width of the preset determination signal, then step S204 is executed; if the determination result is negative, that is, the output of the transmission unit in the circuit where the chip enters the test mode is determined to be different from the pulse width of the preset determination signal, step S206 is executed.
S204, judging that the chip enters a test mode.
In practical application, if it is determined that the output of the transmission unit in the circuit where the chip enters the test mode is the same as the pulse width of the preset determination signal, it can be said that the signal adjustment unit in the circuit where the chip enters the test mode cannot adjust the signal of the input pin of the chip, and it can be determined that the chip enters the test mode.
S206, judging that the chip does not enter the test mode.
In practical application, if it is determined that the pulse width of the transmission unit in the circuit where the chip enters the test mode is different from the pulse width of the preset determination signal, it can be said that the signal adjustment unit in the circuit where the chip enters the test mode can adjust the signal of the input pin of the chip, and it can be determined that the chip does not enter the test mode.
Based on the circuit for the chip to enter the test mode provided in the foregoing embodiment, assuming that the circuit for the chip to enter the test mode may be specifically as shown in fig. 1 and 2, the method for determining that the chip enters the test mode specifically includes the following implementation processes:
when the chip is IN normal operation mode, the signal at the input pin IN enters the internal circuit (Ana _ circuit IN fig. 2) through the path 2.
When the power-on initialization process is performed, the enable signal is high, at this time, the signal is output through the output end (OUT _ DIG) of the transmission gate buffer through the path 1 and enters the internal logic circuit, the path 2 is closed, and whether the test mode is performed after the power-on initialization is completed can be judged by collecting the signal level on the input pin IN.
During the power-on initialization process, a PULSE signal (INIT _ PULSE) with a certain width is generated inside the chip, and the purpose of the PULSE signal is to lock the level of the input pin IN. When the pulse signal is at a high level (during the latch period), the switch MN1 is turned on, and the signal at the input pin is pulled down through the resistor R1.
If the input pin IN is not pulled up by the periphery of the chip before initialization, that is, the switch connecting the input pin IN of the chip and the power supply pin VDD is disconnected, during latching, since the pulse signal pulls down the signal through the resistor R1, the signal output by the output terminal (OUT _ DIG) of the transmission gate buffer is low level "0", and at this time, the chip does not enter the test mode.
If the periphery of the chip pulls up the input pin IN before power-on initialization, that is, the switch connecting the input pin IN of the chip and the power supply pin VDD is closed, during latching, the pulse signal pulls down the signal through the resistor R1, and since the external pull-up is strong pull-up and the internal pull-down is weak pull-down through the resistor R1, the signal output by the output end (OUT _ DIG) of the transmission gate buffer is high level "1", and at this time, the chip enters a test mode.
It should be noted that after the chip enters the test mode, the chip may be further tested and verified by multiplexing other chip pins such as the input pin and the output pin. If the test mode is to be exited, the chip is powered on again and the pull-up action is not performed on the input pin IN before the power-on.
And after the chip enters the normal working mode after the power-on initialization is finished, the pulse signal is always low, the enable signal is low, at the moment, the path 1 is closed, the input pin IN is not pulled down, and the normal work of the chip cannot be influenced.
And the circuit for entering the test mode of the chip is assumed to be as shown in fig. 3 and 4. In this embodiment, the circuit of the chip entering the test mode is a modification of the above embodiment, and the method for determining that the chip enters the test mode specifically includes the following implementation processes:
when the chip is IN normal operation mode, the signal at the input pin IN enters the internal circuit (Ana _ circuit IN fig. 4) through the path 2.
When the power-on initialization process is performed, the enable signal is high, at this time, the signal is output through the output end (OUT _ DIG) of the transmission gate buffer through the path 1 and enters the internal logic circuit, and the path 2 is closed, so that whether the power-on initialization is completed or not enters the test mode can be judged by acquiring the signal level on the input pin IN.
During the power-on initialization process, a PULSE signal (INIT _ PULSE) with a certain width is generated inside the chip, and the purpose of the PULSE signal is to lock the level of the input pin IN. When the pulse signal is at a high level (during the latch period), the switch MP1 is turned on, and the signal at the input pin IN is pulled up through the resistor R1.
If the input pin IN is not pulled down by the periphery of the chip before initialization, that is, the switch connecting the input pin IN of the chip and the ground pin GND is disconnected, during latching, since the pulse signal pulls up the signal through the resistor R1, the signal output by the output terminal (OUT _ DIG) of the transmission gate buffer is high level "1", and at this time, the chip does not enter the test mode.
If the peripheral of the chip pulls down the input pin IN before power-on initialization, that is, the switch connecting the input pin IN of the chip and the ground pin GND is closed, during latching, the pulse signal pulls up the signal through the resistor R1, and since the external pull-down is strong pull-down and the internal pull-up is weak through the resistor R1, the signal output by the output end (OUT _ DIG) of the transmission gate buffer is low level "0", and at this time, the chip enters a test mode.
In addition to the above-mentioned mode of determining whether the chip enters the test mode, the high-low level output by the transmission gate buffer may be detected through a plurality of pulse signals, and when the output signals of the transmission gate buffer are all high or all low during the detection of the plurality of pulses, it may be determined that the chip enters the test mode.
IN addition, a strong square wave signal with a period far smaller than the pulse width of the pulse signal can be input outside the input pin IN during the pulse period, and when the output of the transmission gate is detected to be a section of square wave signal with uniform high and low, the chip is judged to enter the test mode.
Features described in the embodiments in the present specification may be replaced with or combined with each other, and the same and similar portions among the embodiments may be referred to each other, and each embodiment is described with emphasis on differences from other embodiments. In particular, the system or system embodiments, which are substantially similar to the method embodiments, are described in a relatively simple manner, and reference may be made to some descriptions of the method embodiments for relevant points. The above-described system and system embodiments are only illustrative, wherein the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement without inventive effort.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.
Claims (10)
1. A circuit for a chip to enter a test mode, comprising: the switch, the signal adjusting unit and the transmission unit are connected with an input pin and a preset pin of the chip;
the signal adjusting unit and the transmission unit are respectively connected with an input pin of the chip;
the signal adjusting unit is used for adjusting the signal of the input pin according to the received preset pulse signal;
the transmission unit is used for transmitting the signal of the input pin to an output end when receiving an enabling signal, so that the chip enters a test mode.
2. The circuit for entering the test mode of the chip according to claim 1, wherein if the predetermined pin is a power pin of the chip, the signal adjusting unit comprises: a first resistor and a first switch tube;
one end of the first resistor is used as an input end of the signal adjusting unit and is connected with an input pin of the chip;
the other end of the first resistor is connected with the second end of the first switch tube, the control end of the first switch tube receives the preset pulse signal, and the first end of the first switch tube is grounded.
3. The circuit for entering the test mode of the chip according to claim 2, wherein the first switch tube is an NMOS tube.
4. The circuit for entering the test mode of the chip according to claim 1, wherein if the predetermined pin is a ground pin of the chip, the signal adjusting unit comprises: the second resistor, the first inverter and the second switch tube;
one end of the second resistor is used as an input end of the signal adjusting unit and is connected with an input pin of the chip;
the input end of the first phase inverter receives the preset pulse signal, and the output end of the first phase inverter is connected with the control end of the second switching tube;
and the second end of the second switch tube is connected with the other end of the second resistor, and the first end of the second switch tube is connected with an input power supply.
5. The circuit for entering the test mode according to claim 4, wherein the second predetermined pin is a ground pin of the chip, and the PMOS transistor of the second switch transistor.
6. The circuit for chip to enter test mode according to claim 1, wherein the transmission unit comprises: one end of the transmission gate is used as the input end of the transmission unit and is connected with the input pin of the chip; the other end of the transmission gate is used as the output end of the transmission unit, and the control end of the transmission gate receives the enable signal.
7. A method for determining that a chip enters a test mode, applied to a circuit for entering a test mode of a chip according to any one of claims 1 to 6, the method comprising:
determining a preset pin which needs to be connected with an input pin of the chip;
judging whether the output of a transmission unit in a circuit of the chip entering a test mode meets a preset judgment condition corresponding to the preset pin;
if the judgment result is yes, judging that the chip enters a test mode;
if the judgment result is negative, the chip is judged to enter the test mode.
8. The method according to claim 7, wherein if the predetermined pin is a power pin of the chip, an output of a transmission unit in a circuit of the chip entering the test mode satisfies a predetermined determination condition corresponding to the predetermined pin, and the method comprises:
if a signal adjusting unit in a circuit of the chip entering a test mode receives a preset pulse signal as a single pulse signal, the output of the transmission unit is a high level;
if the preset pulse signal received by the signal adjusting unit in the circuit of the chip entering the test mode is a multi-pulse signal, the output of the transmission unit is high level in each pulse signal period.
9. The method according to claim 7, wherein if the predetermined pin is a ground pin of the chip, an output of a transmission unit in a circuit of the chip entering the test mode satisfies a predetermined determination condition corresponding to the predetermined pin, and the method comprises:
if a signal adjusting unit in a circuit of the chip entering a test mode receives a preset pulse signal as a single pulse signal, the output of the transmission unit is a low level;
if the preset pulse signal received by the signal adjusting unit in the circuit of the chip entering the test mode is a multi-pulse signal, the output of the transmission unit is low level in each pulse signal period.
10. The method as claimed in claim 7, further comprising, after determining the predetermined pin to be connected to the input pin of the chip:
inputting a preset judgment signal to an input pin of the chip;
judging whether the output of a transmission unit in a circuit of the chip entering a test mode is the same as the pulse width of the preset judgment signal or not;
if the judgment result is yes, judging that the chip enters a test mode;
if the judgment result is negative, the chip is judged not to enter the test mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210599265.2A CN115015733A (en) | 2022-05-30 | 2022-05-30 | Circuit for chip to enter test mode and method for judging chip to enter test mode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210599265.2A CN115015733A (en) | 2022-05-30 | 2022-05-30 | Circuit for chip to enter test mode and method for judging chip to enter test mode |
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| Publication Number | Publication Date |
|---|---|
| CN115015733A true CN115015733A (en) | 2022-09-06 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202210599265.2A Pending CN115015733A (en) | 2022-05-30 | 2022-05-30 | Circuit for chip to enter test mode and method for judging chip to enter test mode |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117434428A (en) * | 2023-12-18 | 2024-01-23 | 杭州晶华微电子股份有限公司 | Chip calibration system, chip calibration mode entering method and chip |
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2022
- 2022-05-30 CN CN202210599265.2A patent/CN115015733A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117434428A (en) * | 2023-12-18 | 2024-01-23 | 杭州晶华微电子股份有限公司 | Chip calibration system, chip calibration mode entering method and chip |
| CN117434428B (en) * | 2023-12-18 | 2024-03-26 | 杭州晶华微电子股份有限公司 | Chip calibration system, chip calibration mode entering method and chip |
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