CN115001457A

CN115001457A - Clock calibration circuit, device and method

Info

Publication number: CN115001457A
Application number: CN202210585231.8A
Authority: CN
Inventors: 不公告发明人
Original assignee: Shenzhen Xhorse Electronics Co Ltd
Current assignee: Shenzhen Xhorse Electronics Co Ltd
Priority date: 2022-05-26
Filing date: 2022-05-26
Publication date: 2022-09-02

Abstract

The present invention provides a clock calibration circuit, device and method, wherein the clock calibration circuit only needs to perform frequency division processing on the clock signal by using the detection period as the frequency division coefficient, so that the effective pulse of the resulting frequency-divided signal is generated at the detection termination time, and then in the vicinity of the detection termination time, namely, the effective edge of the reference clock signal is detected near the generation time of the effective pulse of the frequency division signal to obtain a detection result, and then the effective edge of the frequency division signal to be output is aligned to the effective edge of the reference clock signal according to the detection result, compared with the method that the standard reference signal is adopted to calibrate each clock cycle of the clock signal, the scheme only needs to calibrate the edge of the frequency division signal, thus improving the precision of the frequency division signal by eliminating the accumulated error, the mode has lower input requirements on an external standard time service system, and is suitable for long-time calibration or unattended scenes.

Description

Clock calibration circuit, device and method

Technical Field

The present application relates to the field of clock circuits, and in particular, to a clock calibration circuit, device and method.

Background

To ensure the proper operation of the electronic device, it is often necessary to provide a clock circuit internally to provide a clock signal.

A crystal oscillator or an oscillator is usually provided in the clock circuit, and due to its operating characteristics, the actual frequency of the output clock signal has some deviation from the nominal frequency, and therefore needs to be calibrated. In the conventional calibration method, each clock cycle of a clock signal is calibrated based on an external standard reference signal, and then a target clock signal is obtained after frequency division processing.

Disclosure of Invention

The application provides a clock calibration circuit, characterized in that, be applied to clock circuit, clock circuit is used for providing clock signal, clock calibration circuit includes:

the frequency division module is connected with the clock circuit and is used for carrying out frequency division processing on the clock signal by taking a detection period as a frequency division coefficient to obtain a frequency division signal;

the detection module is connected with the clock circuit, connected with the frequency division module and used for:

detecting the effective edge of the reference clock signal by the clock signal within a time range which has only one effective edge of the reference clock signal and is a first preset time length away from the detection period detection termination moment to obtain a detection result; determining the pulse calibration number, the detection starting time and the frequency division starting time of the next detection period according to the detection result, and correcting the frequency division signal of the next detection period;

and the calibration module is used for being connected with the clock circuit, the detection module and the clock signal in the calibration period to be output according to the detection period, the clock signal, the calibration period and the pulse calibration number.

In one embodiment, the detection module is further configured to:

generating a window detection signal according to the detection period and the first preset time length, wherein an effective pulse of the window detection signal corresponds to an effective edge of the reference clock signal, and two ends of the effective pulse of the window detection signal are respectively different from the detection termination time by the first preset time length;

and based on the window detection signal, detecting the effective edge of the reference clock signal by the clock signal to obtain the detection result.

In one embodiment, the detection result includes a condition that a valid edge of the reference clock signal is detected by the detection termination time, and duration information between the detection time when the valid edge is detected and the detection termination time; the duration information is characterized as a first number of clock cycles; the pulse calibration number comprises an applied pulse number; the detection module is further configured to, if the valid edge is detected before the detection termination time:

taking the first number as the pulse number;

taking the detection time as the detection starting time and the frequency division starting time;

adjusting the effective pulse of the frequency division signal to enable the effective pulse of the frequency division signal to be generated at the detection moment;

wherein the number of added pulses is used to indicate the number of added pulses.

In one embodiment, the first preset duration is a second number of clock cycles of the clock signal, and the detecting module is further configured to:

at the effective pulse generation time of the window detection signal, counting down the clock period of the clock signal with the second number as an initial value until the effective edge is detected before the detection termination time, and taking the second number at the end of counting as the first number.

In one embodiment, the pulse calibration number further includes a pulse number, and the detection module is further configured to, if the valid edge is not detected by the detection termination time:

taking the first number as the pulse reduction number; wherein the number of decreasing pulses is indicative of a number of decreasing pulses;

the divided signal is maintained.

In one embodiment, the detection module is further configured to:

and if the effective edge is not detected until the detection termination time, performing incremental counting of the clock period of the clock signal by taking 0 as an initial value to obtain a count value until the effective edge is detected, and taking the count value at the end of counting as the first number.

In one embodiment, the calibration module comprises:

the generation control unit is connected with the detection module and used for correcting the pulse adding quantity according to the detection period and the calibration period and generating a pulse adding enabling signal according to the calibration period and the corrected pulse adding quantity;

and the pulse compensation unit is respectively connected with the generation control unit and the clock circuit and used for increasing the pulse of the clock signal in the calibration period to be output according to the clock signal and the pulse adding enable signal.

In one embodiment, the generation control unit is further configured to:

if the detection period is equal to the calibration period, maintaining the pulse adding quantity unchanged;

if the detection period is larger than the calibration period, taking [ N (T1/T2) ] as the corrected pulse adding quantity;

if the detection period is less than the calibration period, taking N (T1/T2) as the corrected pulse adding quantity;

wherein [ ] denotes rounding down, N is the number of added pulses before correction, T1 is the calibration period, and T2 is the detection period.

In one embodiment, the calibration period is characterized as 2 ⁿ The corrected number of added pulses is characterized by:

wherein A is the corrected number of the applied pulses, A _i Has a value of 0 or 1, i, m and n are natural numbers, and m is smallAt n;

the generation control unit is further configured to:

if A is _i If the value of (1) is greater than or equal to 1, in each round of division, a division point is set to divide the interval formed by the division of the calibration period by the previous division point into two, and the time of the division point is used as a first trigger time until 2 is obtained ⁱ At each first trigger moment, the front segmentation point is a segmentation point set before the current wheel is segmented;

and generating a pulse with the width of one clock cycle of the clock signal based on the first trigger moment to obtain the pulse-adding enabling signal.

In one embodiment, the generation control unit is further configured to:

after delaying a second preset time at the first trigger time, generating a pulse with the width of one clock cycle of the clock signal to obtain the pulse adding enabling signal; and the second preset duration is integral multiple of the clock period.

In one embodiment, when the pulse calibration number further comprises a decreasing pulse number;

the generation control unit is further used for correcting the pulse reduction quantity according to the detection period and the calibration period, and generating a pulse reduction enabling signal according to the calibration period and the corrected pulse reduction quantity;

the pulse compensation unit is further used for reducing the pulse of the clock signal in the calibration period to be output according to the clock signal and the pulse reduction enabling signal.

In one embodiment, the generation control unit is further configured to:

if the detection period is equal to the calibration period, maintaining the pulse reduction quantity unchanged;

if the detection period is greater than the calibration period, taking [ M (T1/T2) ] as the corrected pulse reduction number;

if the detection period is less than the calibration period, taking M (T1/T2) as the corrected pulse reduction number;

where [ ] denotes a rounding-down, M is the number of subtracted pulses before correction, T1 is the calibration period, and T2 is the detection period.

In one embodiment, the calibration period is characterized as 2 ⁿ The corrected number of subtracted pulses is characterized by:

wherein D is the corrected number of subtraction pulses, D _j Is 0 or 1, j, p and n are natural numbers, and p is less than n;

the generation control unit is further configured to:

if D is _j If the value of (1) is 1, in each round of division, a division point is set to divide the interval formed by the division of the calibration period by the previous division point into two, and the time of the division point is taken as a second trigger time until 2 is obtained ^j The front segmentation point is a segmentation point set before the current wheel is segmented at the second trigger moment;

and generating a pulse with the width of one clock cycle of the clock signal at each second trigger moment to obtain the pulse reduction enable signal.

In one embodiment, the pulse compensation unit includes: the first NOT gate, the second NOT gate, the third NOT gate, the first trigger, the second trigger, the third trigger, the AND gate, the NAND gate, the OR gate, the buffer circuit and the two-way selector;

the input end of the first NOT gate is connected with the generation control unit, and the input end of the second NOT gate is used for being connected with the clock circuit;

the input end of the first trigger is connected with the output end of the first not gate, the clock end of the first trigger is connected with the output end of the second not gate, and the output end of the first trigger is connected with the first input end of the and gate;

the second input end of the AND gate is connected with the clock circuit, and the output end of the AND gate is connected with the first input end of the two-way selector;

the input end of the second trigger is connected with the generation control unit, and the output end of the second trigger is respectively connected with the input end of the third trigger and the first input end of the NAND gate;

the input end of the third not gate and the clock end of the third trigger are respectively connected with the clock circuit, and the output end of the third not gate is respectively connected with the first input end of the or gate and the clock end of the second trigger;

the output end of the third trigger is connected with the second input end of the NAND gate, and the output end of the NAND gate is respectively connected with the second input end of the OR gate and the input end of the buffer circuit;

the output end of the buffer circuit is connected with the control end of the two-way selector, and the output end of the OR gate is connected with the second input end of the two-way selector.

A clock calibration apparatus, the apparatus comprising:

a clock circuit;

and a clock calibration circuit as described in any of the above.

A clock calibration method applied to a clock circuit, the clock circuit being used for providing a clock signal, the clock calibration method comprising:

performing frequency division processing on the clock signal by taking the detection period as a frequency division coefficient to output a frequency division signal;

detecting the effective edge of the reference clock signal by the clock signal within a time range which has only one effective edge of the reference clock signal and is a first preset time length away from the detection period detection termination moment to obtain a detection result;

determining the pulse calibration number, the detection starting time and the frequency division starting time of the next detection period according to the detection result, and correcting the frequency division signal of the next detection period;

and performing pulse calibration on the clock signal in the calibration period to be output according to the detection period, the clock signal, the calibration period and the pulse calibration number.

The clock calibration circuit only needs to perform frequency division processing on a clock signal by taking a detection period as a frequency division coefficient, so that an effective pulse of an obtained frequency division signal is generated at the detection termination time, then an effective edge of a reference clock signal is detected near the detection termination time, namely near the effective pulse generation time of the frequency division signal, a detection result is obtained, further the pulse calibration number, the detection starting time and the frequency division starting time of the next detection period are determined according to the detection result, the frequency division signal of the next detection period is corrected, finally, the calibration module performs pulse calibration on the clock signal in the calibration period to be output according to the detection period, the clock signal, the calibration period and the pulse calibration number, and therefore the effective edge of the frequency division signal to be output is aligned to the effective edge of the reference clock signal, and compared with the standard reference signal, the calibration is performed on each clock period of the clock signal, the scheme only needs to carry out edge calibration on the frequency division signal, so that the precision of the frequency division signal is improved by eliminating accumulated errors, the mode has lower input requirements on an external standard time service system, and the method is suitable for long-time calibration or unattended scenes.

Drawings

Fig. 1 is a block diagram of a clock calibration circuit according to an embodiment of the present application;

FIG. 2 is a timing diagram of signals of a clock calibration circuit according to an embodiment of the present application;

FIG. 3 is a timing diagram of signals of a clock calibration circuit according to another embodiment of the present application;

FIG. 4 is a schematic diagram of a sampling result of the clock calibration circuit of the present application;

FIG. 5 is a timing diagram of signals of a clock calibration circuit according to another embodiment of the present application;

FIG. 6 is a block diagram of a clock calibration circuit according to another embodiment of the present application;

FIG. 7 is a circuit diagram of a pulse compensation unit according to an embodiment of the present application;

FIG. 8 is a timing diagram of signals of a clock calibration circuit according to another embodiment of the present application;

fig. 9 is a flowchart illustrating a clock calibration method according to an embodiment of the present application.

Detailed Description

It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without inventive step, are within the scope of the present disclosure.

It should be noted that all directional indicators (such as upper, lower, left, right, front and rear … …) in the embodiments of the present application are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is changed accordingly, and the connection may be a direct connection or an indirect connection.

In addition, descriptions in this application as to "first", "second", etc. are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present application.

Fig. 1 is a schematic structural diagram of a clock calibration circuit according to an embodiment, where the clock calibration circuit is applied to a clock circuit, and the clock circuit is used for providing a clock signal. As shown in fig. 1, the clock calibration circuit includes a frequency division block 101, a detection block 102, and a calibration block 103. The frequency division module 101 is connected to the clock circuit 100, and configured to perform frequency division processing on the clock signal with the detection period as a frequency division coefficient to obtain a frequency division signal; the detection module 102 is configured to be connected to the clock circuit 100, and connected to the frequency dividing module 101, and configured to detect an effective edge of a reference clock signal with the clock signal within a time range that is a first preset time from a detection termination time of the detection period and that only has the effective edge of the reference clock signal, so as to obtain a detection result; determining the pulse calibration number, the detection starting time and the frequency division starting time of the next detection period according to the detection result, and correcting the frequency division signal of the next detection period; the calibration module 103 is configured to be connected to the clock circuit 100, and connected to the detection module 102, and configured to perform pulse calibration on the clock signal within the calibration period to be output according to the detection period, the clock signal, the calibration period, and the pulse calibration number.

The frequency division module 101 performs frequency division processing on the clock signal by using the detection period as a frequency division coefficient, so that an effective pulse of the frequency-divided signal obtained after the frequency division processing is generated at the detection termination time of the detection period. The detection period may be preset artificially, and may be an integral multiple of a clock period of the clock signal, and is usually a calendar clock obtained after frequency division processing, and the detection period may be determined according to the calendar clock.

The reference clock signal may be provided to the detection module 102 by an external reference clock, and when the detection module 102 detects the valid edge of the reference clock signal, only one valid edge of the reference clock exists in the detection time range, and the distance from the detection termination time of the detection period is a first preset time length. The time range may be separated from the detection termination time of the detection period by a first preset time length, and the two boundary times forming the time range may be separated from the detection termination time of the detection period by the first preset time length, that is, the detection termination time of the detection period may be located at a midpoint of the time range. As shown in fig. 2, at t _f Detecting the end time as the detection period, time t ₁ And time t ₂ Forming a time rangeWith only one active edge of the reference clock signal present, at time t _x Time t ₁ And time t ₂ Respectively detecting the termination time t with the detection period _f Separated by a first preset duration L1. The first preset duration L1 can be set according to a frequency deviation between the clock signal and the reference clock signal, which does not exceed one detection period.

The effective edge of the reference clock signal is detected by the clock signal, which may be the effective edge of the reference clock signal detected by the effective pulse of the clock signal, and when the reference clock signal is detected to be changed from the first level to the second level, the detection of the effective edge of the reference clock signal is indicated. Referring to fig. 2, when the active pulse of the clock signal is at a high level and the active edge of the reference clock signal is an upper transition edge changed from a low level to a high level, the time when the active pulse of the clock signal detects the upper transition edge of the reference clock signal is t _a The time of day. It can be understood that the calibration is suitable for the calibration of the small-error clock signal because the detection of the valid edge of the reference clock signal by the clock signal is performed in a specific time interval, which only includes one valid edge of the reference clock signal.

The detection result can be used for representing the relation between the detection time when the effective edge is detected and the detection termination time. The detection module 102 may determine the pulse calibration number, the detection start time, and the frequency division start time of the next detection period based on the detection result, and modify the frequency division signal of the next detection period. The pulse calibration number may be used to indicate a pulse number of the calibration clock signal, and the calibration module 103 may affect the frequency division signal obtained by frequency division counting after performing pulse calibration on the clock signal in the calibration period to be output based on the detection period, the clock signal, the calibration period, and the pulse calibration number. The detection starting time is the starting time of the detection period, and under the condition that the detection period is fixed, the detection starting time determines the detection ending time of the detection period, so that the detection result is influenced, and further the frequency division signal obtained by frequency division based on the detection period is influenced. The division start time is the start time of the division counting in one division cycle, and determines the generation time of the effective pulse of the division signal. Therefore, the pulse calibration number, the detection start time, the frequency division start time and the correction frequency division signal all affect the output of the frequency division signal, and finally, the effective edge of the frequency division signal to be output is aligned with the effective edge of the reference clock signal.

The clock calibration circuit of the embodiment of the invention only needs to perform frequency division processing on a clock signal by taking a detection period as a frequency division coefficient, so that an effective pulse of an obtained frequency division signal is generated at the detection termination time, then an effective edge of a reference clock signal is detected near the detection termination time, namely near the generation time of the effective pulse of the frequency division signal, so as to obtain a detection result, further the pulse calibration number, the detection start time and the frequency division start time of the next detection period are determined according to the detection result, the frequency division signal of the next detection period is corrected, and finally the calibration module 103 is combined to perform pulse calibration on the clock signal in the calibration period to be output according to the detection period, the clock signal, the calibration period and the pulse calibration number, so that the effective edge of the frequency division signal to be output is aligned with the effective edge of the reference clock signal, compared with the method that a standard reference signal is adopted to calibrate each clock period of the clock signal, the scheme only needs to carry out edge calibration on the frequency division signal, so that the precision of the frequency division signal is improved by eliminating accumulated errors, the mode has low input requirement on an external standard time service system, and the method is suitable for long-time calibration or unattended scenes.

In an embodiment, the detection module 102 is further configured to generate a window detection signal according to a detection period and a first preset duration, where an effective pulse of the window detection signal corresponds to an effective edge of a reference clock signal, and two ends of the effective pulse of the window detection signal respectively differ from the detection termination time by the first preset duration; and based on the window detection signal, detecting the effective edge of the reference clock signal by using the clock signal to obtain a detection result.

It will be appreciated that the edge detection is performed at a time when only one valid edge of the reference clock signal is present and is a first predetermined time from the end of the detection cycleIn the time interval, a window detection signal is generated according to the detection period, the reference clock signal and the clock signal, and then based on the window detection signal, the effective edge of the reference clock signal is detected by the clock signal in the time interval of the effective pulse of the window detection signal, the waveform of the window detection signal can be referred to as shown in fig. 2, and the effective pulse is located at t ₁ To t ₂ In the time interval, the difference between the two ends of the effective pulse and the detection termination time is a first preset time length L1.

The detection termination time of the detection period can be obtained according to the detection period prediction, and then the window detection signal can be obtained by respectively pushing forward and backward for a first preset time length by taking the detection termination time as a reference. To ensure that the valid pulses of the window detection signal correspond to only the valid edges of a reference clock signal, the frequency f of the reference clock signal _ref Should satisfy 1<2L1f _ref <2, the effective pulse width of the window detection signal should be greater than one period of the reference clock signal and less than two periods of the reference clock signal. In addition, to ensure the accuracy of the detection of the effective edge of the clock signal with respect to the reference clock signal, the frequency f of the reference clock signal _ref With the frequency f of the clock signal _calr Should satisfy 2f _ref <f _calr To ensure that the reference clock signal is valid, the frequency deviation of the reference clock signal should be less than f _calr /2 ^k Wherein 2 is ^k Indicating a sensing period as clock period 2 ^k And (4) multiplying.

In the embodiment, the window detection signal is generated according to the detection period and the first preset time length, so that the time interval of detecting the effective edge of the reference clock signal by the clock signal is limited, and the principle is simple and effective.

In one embodiment, the detection result includes a case where the valid edge of the reference clock signal is detected by the detection termination time, and time length information between the detection time when the valid edge is detected and the detection termination time; the duration information is characterized by a first number of clock cycles of the clock signal, the calibrated number of pulses comprises a number of added pulses, the detection module 102 is further configured to, if a valid edge is detected before the end of detection time: taking the first number as the pulse number; taking the detection time as a detection starting time and a frequency division starting time; adjusting the effective pulse of the frequency division signal to enable the effective pulse of the frequency division signal to be generated at the detection time; wherein the number of added pulses is used to indicate the number of added pulses.

It will be appreciated that ideally the clock signal should be aligned with the active edge of the reference clock signal at the end of the test, and that a low clock signal frequency would result in the end of the test t not being reached _f A valid edge of the reference clock is detected, as shown in fig. 3, due to the detection termination time t _f It has been determined in advance that, after the detection time is obtained, the duration information can be determined based on the detection time and the detection termination time, wherein the duration information can be represented by a first number of clock cycles. When the valid edge is detected before the detection termination time, the detection module 102 uses the first number as the number of added pulses to instruct the calibration module 103 to subsequently increase the number of pulses, and at the same time, re-determines the detection time as the detection start time of the next detection period and the frequency division start time of the next frequency division period, and adjusts the valid pulses of the frequency division signal so that the valid pulses of the frequency division signal are generated at the detection time.

Specifically, referring to fig. 3, when the edge of the reference clock signal is detected by the clock signal, it is set at t _a Detecting the effective edge of the reference clock signal at the moment, wherein the detection moment is t under the theoretical condition _a However, considering that the reference clock signal and the clock signal are derived from different clocks, the signals crossing the clock domain usually need to be clock-synchronized, i.e. three times of sampling, when performing edge detection, as shown in fig. 4, the first sampling is to sample the effective edge of the reference clock signal, i.e. at t _a The time is sampled to the effective edge of the reference clock, the second sampling is the result of the first sampling by the clock signal, namely at t _b The sampling of the time being effective for the first time and the sampling for the third time being the result of the second sampling with a clock signal, i.e. at time t _c Sampling until the second sampling result is valid, and finally, the edge detection result is equal to the pairThe third sampling result is XOR-ed with the second sampling result, so that the detection time is actually the time t _b The final edge detection result is at time t _b To time t _c Valid, for example, the edge detection result may be represented by a detection pulse in the graph.

Before the detection starting time and the frequency division starting time are determined again, the original detection starting time of the next detection period is the detection ending time t of the current detection period _f The initial detection time after re-determination is time t _b (ii) a The frequency division starting time of the original next frequency division period is the detection termination time t _f Referring to the divided signal in fig. 3, the newly determined division start time should also be the time t _b . In fact, due to the synchronous clock, the redetermined detection start time and the frequency division start time are actually the next clock rising edge when the detection result is valid, namely the time t _c . The output of the frequency division signal can be obtained by counting the clock period of the clock signal by a counter, and setting the frequency division coefficient to be 2 ^k The starting time of the next frequency-dividing period is determined again as time t _c Then, at time t _c By 2 ^k -1 counts down, and when it counts to 0, one divide cycle count is completed as shown in fig. 3. Similarly, the effective pulse of the adjusted frequency-divided signal is actually generated at the time t _c The waveform can be referred to as the final output shown in fig. 3.

The first number indicates the number of clock cycles that the reference clock signal and the clock signal differ by one division cycle when the reference clock signal and the clock signal are output at the same initial timing. And adjusting the effective pulse of the frequency division signal under the condition that the effective edge is detected before the detection termination time, taking the detection time as the detection start time and the frequency division start time again, and taking the first number of clock cycles with the difference between the detection time of the effective edge and the detection termination time as the pulse adding number to perform pulse calibration on the clock signal of the next calibration period, so as to realize the pulse calibration on the clock signal of the next detection period.

In one embodiment, the first preset duration is a second number of clock cycles of the clock signal, and the detection module 102 is further configured to: at the effective pulse generation time of the window detection signal, down-counting of the clock period of the clock signal is performed with the second number as an initial value until the effective edge is detected before the detection termination time, with the second number at the end of the counting as the first number.

With reference to the detection count shown in FIG. 3, to obtain the detection time t _b And the detection end time t _f A first preset duration L1 may be characterized as a second number of clock cycles of the clock signal, for example 15 clock cycles, and then the clock cycle detection count is used to detect the valid pulse generation time t of the signal at the window ₁ Counting down the clock period of the clock signal with 15 as an initial value until the detection time t _b And detecting a valid edge, finishing counting, wherein the second number is counted to be 7, 7 is taken as the first number, and the added pulse number is also 7. Therefore, the first number is obtained by the clock period detection counting mode without intermediate calculation, and the method is simple and efficient.

In one embodiment, the pulse calibration number further includes a pulse number, and the detection module 102 is further configured to, if no valid edge is detected by the detection termination time: taking the first number as the pulse reduction number; wherein the number of decreasing pulses is used to indicate the number of decreasing pulses; taking the detection time as a detection starting time and a frequency division starting time; the frequency divided signal is maintained.

It will be appreciated that ideally the clock signal should be aligned with the valid edge of the reference clock signal at the end of the test, and that a higher frequency clock signal will result in the test end t being reached _f The valid edge of the reference clock has not yet been detected, as shown in fig. 5, due to the detection termination time t _f Has been determined in advance, and after obtaining the detection time, according to the detection time and detectionThe duration information may be determined by measuring the termination time, where the duration information may be represented in a first number of clock cycles. When the detection termination time t has been reached _f If the valid edge of the reference clock is not detected yet, the normal output of the frequency-divided signal is maintained, referring to the final output shown in fig. 5, while the detection module 102 uses the first number as the number of the decreasing pulses to instruct the calibration module 103 to decrease the number of the pulses subsequently, and further re-determines the detection time as the detection start time of the next detection period and the frequency-dividing start time of the next frequency-dividing period.

Specifically, referring to fig. 5, when the edge of the reference clock signal is detected by the clock signal, t is set _a Detecting the effective edge of the reference clock signal at the moment, wherein the detection moment is t under the theoretical condition _a However, considering that the reference clock signal and the clock signal are derived from different clocks, the signals crossing the clock domain usually need to be clock-synchronized, i.e. three times of sampling, when performing edge detection, as shown in fig. 4, the first sampling is to sample the effective edge of the reference clock signal, i.e. at t _a The time is sampled to the effective edge of the reference clock, the second sampling is the result of the first sampling by the clock signal, namely at t _b The sampling of the time instants is valid until the first sampling, and the third sampling is performed by sampling the result of the second sampling with a clock signal, i.e. at time instant t _c Sampling is carried out until the second sampling result is valid, and the final edge detection result is equal to the exclusive OR operation of the third sampling result and the second sampling result, so that the detection moment is actually the moment t _b The final edge detection result is at time t _b To time t _c Valid, for example, the edge detection result may be represented by a detection pulse in the graph.

Before the detection starting time and the frequency division starting time are re-determined, the original detection starting time of the next detection period is the detection ending time t of the current detection period _f The initial detection time is determined as t _b (ii) a The frequency division starting time of the original next frequency division period is the detection termination time t _f Referring to the divided signal in fig. 5, the frequency division after re-determinationThe starting time should also be time t _b . In fact, due to the synchronous clock, the redetermined detection start time and the division start time are actually the next clock rising edge when the detection result is valid, i.e. the time t _c . The output of the frequency division signal can be obtained by counting the clock period of the clock signal by a counter, and setting the frequency division coefficient to be 2 ^k The starting time of the next frequency-dividing period is determined as time t again _c Then, at time t _c By 2 ^k The-1 counts down and completes one divide cycle count when the count reaches 0, as shown in fig. 5.

Under the condition that the effective edge is not detected when the detection termination time is up, normally outputting a frequency division signal, taking the detection time as the detection start time and the frequency division start time again, and taking the first number of clock cycles with the difference between the detection time of the effective edge and the detection termination time as the pulse reduction number to perform pulse calibration on the clock signal of the next calibration period, so as to perform pulse calibration on the clock signal of the next detection period, thus gradually aligning the effective edge of the frequency division signal to be output with the effective edge of the reference clock signal, and finally aligning the frequency division signal to the reference clock signal. Due to the synchronous clock, the actually redetermined detection starting time and the frequency division starting time have 2-3 clock period deviation with the theoretically redetermined detection starting time and frequency division starting time, so that the finally output frequency division signal also has 2-3 clock period deviation.

In one embodiment, the detection module 102 is further configured to: if the effective edge is not detected when the detection is ended, the clock period of the clock signal is counted up by taking 0 as an initial value to obtain a count value until the effective edge is detected, and the count value at the end of counting is taken as a first number.

With reference to the detection count shown in FIG. 5, to obtain the detection time t _b And detection termination time t _f A first predetermined duration L1 may be characterized as a second number of clock cycles of the clock signal, e.g., 15 clock cycles in the figureTaking the period as an example, then detecting the count by using the clock period, and at the detection termination time t _f The clock signal is counted up with 0 as initial value to obtain count value until time t _b And detecting a valid edge, finishing counting, wherein the counting value is 8, 8 is taken as a first number, and the number of the obtained minus pulses is also 8. Therefore, the first number is obtained by the clock period detection counting mode without intermediate calculation, and the method is simple and efficient.

In one embodiment, the calibration module 103 comprises a generation control unit 1032 and a pulse compensation unit 1031, as shown in fig. 6. The generation control unit 1032 is connected to the detection module 102, and configured to correct the number of added pulses according to the detection period and the calibration period, and generate an added pulse enable signal according to the calibration period and the corrected number of added pulses; the pulse compensation unit 1031 is connected to the generation control unit 1032 and the clock circuit 100, respectively, and is configured to increase the pulse of the clock signal in the calibration period to be output according to the clock signal and the pulse enable signal.

It will be appreciated that the calibration period may be artificially preset, indicating a minimum time unit for which calibration is to be performed. The number of applied pulses indicates the number of pulses to be added in the detection period, and the pulse compensation unit 1031 adds the number of pulses in the calibration period, and the detection period and the calibration period are not necessarily equal to each other, so that the number of applied pulses needs to be corrected according to the detection period and the calibration period.

The generation control unit 1032 may be provided with a signal generator, which generates an enable signal after obtaining the corrected number of added pulses. The additional pulse enable signal generated based on the calibration period information and the number of additional pulses may carry time information and number information of the additional pulses, which may be used to indicate an increase of the preset number of pulses at a preset time within the calibration period of the clock signal.

In one embodiment, the generation control unit 1032 is further configured to: if the detection period is equal to the calibration period, maintaining the pulse adding quantity unchanged; if the detection period is larger than the calibration period, taking [ N (T1/T2) ] as the corrected pulse adding quantity; if the detection period is less than the calibration period, taking N (T1/T2) as the corrected pulse number; where [ ] indicates rounding down, N is the number of pulses added before correction, T1 is the calibration period, and T2 is the detection period.

Wherein both the detection period and the calibration period can be characterized as being an exponential power of 2, e.g. let the detection period be characterized as 2 ^k The calibration period is characterized as 2 ⁿ When the pulse number is corrected according to the detection period and the calibration period, if the detection period is equal to the calibration period, the pulse number is not corrected, and the value is still N; if the detection period is greater than the calibration period, the ratio of the calibration period to the detection period can be calculated to obtain 2 ^n-k Then, the product of the number of added pulses and the ratio is calculated, and the product is rounded down to obtain the corrected number of added pulses [ N2 ] ^n-k ](ii) a If the detection period is less than the calibration period, the product of the number of added pulses and the ratio can be calculated after the ratio is calculated, and the corrected number of added pulses N2 can be obtained ^n-k 。

In one embodiment, the calibration period is characterized as 2 ⁿ The corrected number of added pulses per clock cycle of the clock signal is characterized as:

wherein A is the corrected number of added pulses, A _i Is 0 or 1, i, m and n are natural numbers, and m is less than n.

The generation control unit 1032 is further configured to: if A _i If the value of (1) is 1, in each round of division, a division point is set to divide an interval formed by dividing the previous division point into two parts in the calibration period, and the time of the division point is taken as a first trigger time until 2 is obtained ⁱ At a first trigger moment, the front division point is a division point set before the current round division; and generating a pulse with the width of one clock cycle of the clock signal based on the first trigger time to obtain a pulse adding enabling signal.

It is understood that, in presetting the calibration period, the calibration period should satisfy the clock periods of the clock signal whose value is equal to the power of 2. The number of the added pulses is an integer,which may be characterized as a sum of a plurality of different exponentiations of 2, at least one round of division may be performed for any one of the exponentiations of 2 in generating the pulse enable signal, wherein in each round of division, a division point is set to divide a section formed by dividing the previous division point into the calibration period into two and a time at which the division point is located is taken as a first trigger time until a number of first trigger times equal to the exponentiation of 2 are obtained, and then a pulse having a width of one clock period of the clock signal is generated based on each of the first trigger times. For example, if the calibration period is 2 ⁵ 32, a equals 12, i.e. a is characterized as equal to 2 ² And 2 ³ Sum, on the one hand, against 2 ² 4, namely obtaining 4 division points as a first trigger time; performing at least one round of division, wherein when the first round of division is performed, since only one interval of the calibration period exists at the time, the number of division points set by the round of division is 1, the division points are located in the 16 th clock period, and since the number of the division points of the round of division does not reach 4, the division is continuously performed; when the second round of division is carried out, because two intervals of 0-16 clock cycles and 16-32 clock cycles exist after the first round of division, the number of division points set by the round of division is 2, the division points are respectively positioned in the 8 th clock cycle and the 24 th clock cycle, and because the number of the division points of the round is not more than 4, the division is continuously carried out; in the third round of division, four intervals of 0-8 clock cycles, 8-16 clock cycles, 16-24 clock cycles and 24-32 clock cycles exist after the first round of division and the second round of division, so that the number of division points set in the round of division is 4, the division points are respectively positioned in the 4 th, 12 th, 20 th and 28 clock cycles, at the moment, the 4 first trigger moments are respectively 4, 12, 20 and 28 clock cycles, and the 2 nd round of division is performed for the four intervals ² The division of (2) is finished; on the other hand, for 2 ³ As can be seen from the above description, the third round of division obtains only 4 first trigger times and does not reach 8, and therefore the fourth round of division is continued. In the fourth division, the first, second and third divisions have 0-4 clock periods, 4-8 clock periods and 8-Eight intervals of 12 clock cycles, 12-16 clock cycles, 16-20 clock cycles, 20-24 clock cycles, 24-28 clock cycles and 28-32 clock cycles, therefore, the number of the division points divided by the wheel is 8, which are respectively located at the 2 nd, 6 th, 10 th, 14 th, 18 th, 22 th, 26 th and 30 clock cycles, at this time, the 8 first trigger times are respectively the 2 nd, 6 th, 10 th, 14 th, 18 th, 22 th, 26 th and 30 clock cycles, and thus, 2 nd clock cycle, the 16 th to 16 th clock cycle, the 16 th to 20 th clock cycle, the 20 th to 24 th clock cycle, the 24 th to 28 th clock cycle and the 28-32 th clock cycle are aimed at ³ The division of (2) is finished.

After the first trigger time is obtained, a pulse is further generated based on each first trigger time, so that a pulse reduction enabling signal is obtained. The first trigger time can be used for enabling the excitation pulse to be generated at the current time immediately, namely the pulse is generated at the first trigger time; furthermore, the first triggering time may also be used for excitation pulses being generated at a specific time, i.e. pulses not being generated at the first triggering time.

In one embodiment, the clock cycles may be counted by a counter to determine the first trigger time, and the counter may start counting from 0 in a two-level system. For example, let n be 20 and m be 8, i.e. the calibration period is 2 ²⁰ ，

ADD[8:0]Effective bit ADD [ i]The corresponding relationship with the clock cycle count of the clock signal can be referred to table 1.

TABLE 1

Clock cycle counting	ADD[i]	Number of generated pulses
			1000_0000_0000_0000_0000	ADD[0]	1
？100_0000_0000_0000_0000	ADD[1]	2
			？？10_0000_0000_0000_0000	ADD[2]	4
？？？1_0000_0000_0000_0000	ADD[3]	8
			？？？？_1000_0000_0000_0000	ADD[4]	16
？？？？_？100_0000_0000_0000	ADD[5]	32
			？？？？_？？10_0000_0000_0000	ADD[6]	64
？？？？_？？？1_0000_0000_0000	ADD[7]	128
			？？？？_？？？？_1000_0000_0000	ADD[8]	256

Wherein, the symbol "? "0" or "1" indicates that the bit, whether "0" or "1", generates a pulse.

The pulse adding quantity is characterized as the sum of a plurality of 2 different exponential powers, then at least one round of division is carried out for any 2 exponential powers, wherein in each round of division, division points are set to divide a section formed by dividing a previous division point into a calibration period into two, the time of the division point is taken as a first trigger time, until the first trigger time with the quantity equal to the 2 exponential power is obtained, and then pulses with the width of one clock signal clock period are generated based on the first trigger time corresponding to each 2 exponential power, so that the pulse uniformity of the pulse adding enabling signal can be realized, and further the pulses in the clock signals are uniformly increased, so that the calibrated clock signals are uniform in pulse.

In one embodiment, the generation control unit 1032 is further configured to: after delaying a second preset time at the first trigger time, generating a pulse with the width of one clock period of the clock signal to obtain a pulse adding enabling signal; and the second preset duration is integral multiple of the clock period.

It will be appreciated that after at least one division to any one of the 2 exponentiations to obtain an equal number of first trigger times to each 2 exponentiations, the pulses may be generated after a delay of a second predetermined duration on a per first trigger time basis, thus still achieving pulse uniformity of the pulse enable signal. The second preset duration is an integer multiple of the clock period, and may be, for example, 1 clock period or 2 clock periods, and the specific value is not limited thereto.

In one embodiment, when the pulse calibration number further comprises a decrement pulse number; the generation control unit 1032 is further configured to correct the number of minus pulses according to the detection period and the calibration period, and generate a minus pulse enable signal according to the calibration period and the corrected number of minus pulses; the pulse compensation unit 1031 is further configured to reduce the pulse of the clock signal in the calibration period to be output according to the clock signal and the pulse reduction enable signal.

It is to be understood that the pulse reduction number indicates the number of pulses to be reduced in the detection period, and the pulse compensation unit 1031 reduces the number of pulses in the calibration period, and the detection period and the calibration period are not necessarily equal, so that the pulse reduction number needs to be corrected according to the detection period and the calibration period.

The generation control unit 1032 may be provided with a signal generator, which generates an enable signal after the corrected number of minus pulses is obtained. The decrement pulse enable signal generated from the calibration period information and the decrement pulse number may carry time information and number information of the increment and decrement pulses, which may be used to indicate that the preset time within the clock signal calibration period is decremented by the preset number of pulses.

In one embodiment, the generation control unit 1032 is further configured to: if the detection period is equal to the calibration period, maintaining the pulse reduction quantity unchanged; if the detection period is larger than the calibration period, taking [ M (T1/T2) ] as the corrected pulse reduction number; if the detection period is less than the calibration period, taking M (T1/T2) as the corrected pulse reduction number; where [ ] denotes rounding down, M is the number of subtracted pulses before correction, T1 is the calibration period, and T2 is the detection period.

Wherein both the detection period and the calibration period can be characterized as being an exponential power of 2, e.g. let the detection period be characterized as 2 ^k The calibration period is characterized as 2 ⁿ When the pulse reduction number is corrected according to the detection period and the calibration period, if the detection period is equal to the calibration period, the pulse reduction number is not corrected, and the value is still M; if the detection period is greater than the calibration period, the ratio of the calibration period to the detection period can be calculated to obtain 2 ^n-k Then, the product of the number of pulses subtracted and the ratio is calculated, and the product is rounded down to obtain the corrected number of pulses subtracted [ M2 ] ^n-k ](ii) a If the detection period is less than the calibration period, the product of the subtraction pulse number and the ratio can be calculated after the ratio is calculated to obtain the corrected addition pulse number M2 ^n-k 。

wherein D is the corrected number of subtracted pulses, D _j Is 0 or 1, j, p and n are natural numbers, and p is less than n.

The generation control unit 1032 is further configured to: if D is _j If the value of (1) is 1, in each round of division, a division point is set to divide an interval formed by dividing the calibration period by the previous division point into two, and the time of the division point is taken as a second trigger time until 2 is obtained ^j At a second trigger moment, the front segmentation point is a segmentation point set before the current wheel is segmented; and generating a pulse with the width of one clock cycle of the clock signal at each second trigger moment to obtain a pulse reduction enable signal.

It is understood that, in presetting the calibration period, the calibration period should satisfy the clock periods of the clock signal whose value is equal to the power of 2. The number of subtractive pulses is an integer that can be characterized as a sum of a number of different powers of 2. In generating the decreasing pulse enable signal, at least one round of division may be performed for any one of the exponentiation powers of 2, wherein in each round of division, a division point is set to divide a section formed by dividing the previous division point into the calibration period into two, and a time at which the division point is located is taken as a second trigger time until a second trigger time equal in number to the exponentiation power of 2 is obtained. For the specific dividing operation performed in the process of generating the pulse-decreasing enable signal, reference may be made to the dividing operation performed in the foregoing embodiment for generating the pulse-increasing enable signal, and details thereof are not described herein.

Then, a pulse having a width of one clock cycle of the clock signal is generated at each second trigger timing. Therefore, the pulse uniformity of the pulse reduction enabling signal can be realized, and further the pulses in the clock signal are uniformly reduced, so that the calibrated clock signal has uniform pulses.

Wherein at most one of the number of added pulses and the number of subtracted pulses may be greater than 0. When the pulse adding number and the pulse subtracting number are both 0, the generated pulse adding enable signal and pulse subtracting enable signal indicate that the increased and decreased pulse number is 0, and the pulse compensation unit 1031 does not perform pulse increasing and decreasing operations on the clock signal; when the number of addition pulses is 0 and the number of subtraction pulses is not 0, the number of addition pulses indicated by the addition pulse enable signal is 0 and the number of subtraction pulses indicated by the subtraction pulse enable signal is not 0, and at this time, in conjunction with the clock signal, the pulse compensation unit 1031 performs only the pulse subtraction operation on the clock signal; when the number of addition pulses is not 0 and the number of subtraction pulses is 0, the number of addition pulses indicated by the addition pulse enable signal is not 0 and the number of subtraction pulses indicated by the subtraction pulse enable signal is 0, and at this time, the pulse compensation unit 1031 pulses only the clock signal in conjunction with the clock signal.

In summary, the increase/decrease operation is performed in 2 ⁿ The clock period of the clock signal can be increased by 20+2 at most ¹ +2 ² +……+2 ^m ＝2 ^m+1 1 pulse, and similarly, up to 2 ^p+1 1 pulse, calibration range of the system is (-2) ^p+1 -1，2 ^m+1 -1) clock cycles with a calibration resolution of 1/2 ⁿ . The clock signal is directly calibrated according to the pulse adding quantity and the pulse subtracting quantity, sampling of the clock signal is not needed, and the method is simple to realize, so that the system structure is simplified.

In one embodiment, as shown in fig. 7, the pulse compensation unit 1031 includes: the first not gate 311, the second not gate 312, the third not gate 313, the first flip-flop 321, the second flip-flop 322, the third flip-flop 323, the and gate 331, the nand gate 332, the or gate 341, the buffer circuit 351, and the router 361. Wherein an input terminal of the first not gate 311 is connected to the generation control unit 1032 (not shown in fig. 7), and an input terminal of the second not gate 312 is connected to the clock circuit 100 (not shown in fig. 7); the input end of the first flip-flop 321 is connected with the output end of the first not gate 311, the clock end of the first flip-flop 321 is connected with the output end of the second not gate 312, and the output end of the first flip-flop 321 is connected with the first input end of the and gate 331; a second input end of the and gate 331 is connected to the clock circuit 100, and an output end of the and gate 331 is connected to a first input end of the two-way selector 361; the input end of the second flip-flop 322 is connected to the generation control unit 1032, and the output end of the second flip-flop 322 is connected to the input end of the third flip-flop 323 and the first input end of the nand gate 332, respectively; an input end of the third not gate 313 and a clock end of the third flip-flop 323 are respectively connected with the clock circuit 100, and an output end of the third not gate 313 is respectively connected with a first input end of the or gate 341 and a clock end of the second flip-flop 322; the output end of the third flip-flop 323 is connected to the second input end of the nand gate 332, and the output ends of the nand gate 332 are respectively connected to the second input end of the or gate 341 and the input end of the buffer circuit 351; an output terminal of the buffer circuit 351 is connected to a control terminal of the two-way selector 361, and an output terminal of the or gate 341 is connected to a second input terminal of the two-way selector 361.

Specifically, as shown in fig. 8, on one hand, an input end of the first not gate 311 receives the decrement pulse enable signal del _ en (including one pulse in the figure) output by the generation control unit 1032, and after being inverted, the decrement pulse enable signal del _ en _ n is obtained and then sent to an input end of the first flip-flop 321, and an input end of the second not gate 312 receives the clock signal src _ clk provided by the clock circuit 100, and after being inverted, the clock signal src _ clk is sent to a clock end of the first flip-flop 321, so that falling edge synchronization of the decrement pulse enable signal del _ en _ n by using a falling edge of the clock signal src _ clk is implemented, and a decrement pulse falling edge synchronization signal del _ en _ neg is obtained. The first input terminal of the and gate 331 receives the inverted decreasing pulse falling edge synchronization signal del _ en _ neg, the second input terminal of the and gate 331 receives the clock signal src _ clk, and the and gate 331 performs an and operation on the inverted decreasing pulse falling edge synchronization signal del _ en _ neg and the clock signal src _ clk to obtain the decreasing pulse output signal clk _ del _ calr, and outputs the decreasing pulse output signal clk _ del _ calr to the first input terminal of the two-way selector 361. It should be understood that there may be a delay between the falling pulse enable signal del _ en and the clock signal src _ clk, and between the falling inverted pulse edge synchronizing signal del _ en _ neg and the clock signal src _ clk due to the influence of the system configuration (for example, in fig. 4, there is a delay between the pulse generation time of the falling pulse enable signal del _ en and the rising edge of the corresponding clock signal src _ clk, and there is a delay between the falling edge of the falling inverted pulse edge synchronizing signal del _ en _ neg and the falling edge of the corresponding clock signal src _ clk).

On the other hand, the input terminal of the second flip-flop 322 receives the pulse enable signal add _ en (including a pulse as an example in the figure) output by the generation control unit 1032, and the input terminal of the third not gate 313 receives the clock signal src _ clk, inverts the clock signal src _ clk to obtain an inverted clock signal src _ clk _ n, and then respectively sends the inverted clock signal src _ clk to the clock terminal of the second flip-flop 322 and the first input terminal of the or gate 341. The second flip-flop 322 implements falling edge synchronization of the clock signal to the pulse enable signal according to the reverse clock signals src _ clk _ n and add _ en, and obtains a pulse falling edge synchronization signal add _ en _ neg. The input end of the third flip-flop 323 receives the pulse adding falling edge synchronization signal add _ en _ neg, the clock end of the third flip-flop 323 receives the clock signal src _ clk, so that rising edge synchronization of the pulse adding falling edge synchronization signal add _ en _ neg is achieved by using a rising edge of the clock signal src _ clk, a pulse adding rising edge synchronization add _ en _ pos is obtained, and the nand gate 332 performs nand operation on the pulse adding falling edge synchronization signal add _ en _ neg and the pulse adding rising edge synchronization add _ en _ pos, and a pre-pulse selection signal add _ en _ sel _ pre is obtained. The buffer circuit 351 delays the pre-pulse selection signal add _ en _ sel _ pre to obtain a pulse-added selection signal add _ en _ sel, and provides the pulse-added selection signal add _ en _ sel to the control terminal of the two-way selector 361, the or gate 341 performs or operation on the pre-pulse selection signal add _ en _ sel _ pre and the reverse clock signal src _ clk _ n to obtain an additional clock signal ext _ clk, and sends the additional clock signal ext _ clk to the second input terminal of the two-way selector 361, the first input terminal of the two-way selector 361 may be a high-level terminal 1, the second input terminal of the two-way selector 361 may be a low-level terminal 0, and the calibration output signal clk _ calr is finally output under the driving of the pulse-added selection signal add _ en _ sel. Similarly, it should be understood that due to the influence of the system structure, there may be a delay between the pulse enable signal add _ en and the clock signal src _ clk, between the pulse falling edge synchronization signal add _ en _ neg and the clock signal src _ clk, and between the pulse rising edge synchronization add _ en _ pos and the clock signal src _ clk.

In one embodiment, the buffer circuit 351 may include a plurality of buffers connected in series.

As shown in fig. 8, taking 3 buffers as an example, buffer 01, buffer 02, and buffer 03 are connected in series in order to delay the pre-pulse selection signal add _ en _ sel _ pre. Wherein the number of buffers can be set as desired to adjust the delay time to finally achieve the desired width of the added pulses.

The embodiment of the invention also provides a clock calibration device, which comprises a clock circuit and the clock calibration circuit in any embodiment.

The working principle and the beneficial effects of the clock calibration apparatus of this embodiment can refer to the clock calibration circuit embodiment, which is not described herein again.

The embodiment of the invention also provides a clock calibration method, which is applied to a clock circuit, wherein the clock circuit is used for providing clock signals. As shown in fig. 9, the clock calibration method includes steps S110 to S140.

Step S110, frequency division processing is performed on the clock signal by using the detection period as a frequency division coefficient to obtain a frequency division signal.

And step S120, detecting the effective edge of the reference clock signal by the clock signal within the time range which is only provided with one effective edge of the reference clock signal and is a first preset time length away from the detection termination moment of the detection period to obtain a detection result.

Step S130, determining the pulse calibration number, the detection start time, and the frequency division start time of the next detection period according to the detection result, and correcting the frequency division signal of the next detection period.

Step S140, performing pulse calibration on the clock signal in the calibration period to be output according to the detection period, the clock signal, the calibration period, and the pulse calibration number.

The working principle and the beneficial effect of the clock calibration method according to the embodiment of the present invention have been specifically described in the clock calibration circuit, and are not described herein again.

In one embodiment, in a time range where only one valid edge of the reference clock signal exists and is a first preset time from the detection termination time of the detection period, the step of detecting the valid edge of the reference clock signal by the clock signal to obtain a detection result includes: generating a window detection signal according to the detection period and a first preset time length, wherein an effective pulse of the window detection signal corresponds to an effective edge of a reference clock signal, and two ends of the effective pulse of the window detection signal respectively differ from the detection termination time by the first preset time length; and based on the window detection signal, detecting the effective edge of the reference clock signal by the clock signal to obtain a detection result.

In one embodiment, the detection result includes a condition that the valid edge of the reference clock signal is detected until the detection termination time, and time length information between the detection time when the valid edge is detected and the detection termination time; the duration information is characterized by a first number of clock cycles, the pulse alignment number comprising an add pulse number; the steps of determining the pulse calibration number, the detection starting time and the frequency division starting time of the next detection period according to the detection result, and correcting the frequency division signal of the next detection period comprise: if the effective edge is detected before the detection termination time, taking the first number as the pulse adding number; taking the detection time as a detection starting time and a frequency division starting time; adjusting the effective pulse of the frequency division signal to enable the effective pulse of the frequency division signal to be generated at the detection time; wherein the number of added pulses is used to indicate the number of added pulses.

In one embodiment, the first preset duration is a second number of clock cycles of the clock signal, and before the step of adding the number of pulses by the first number, the clock calibration method further includes: at the effective pulse generation time of the window detection signal, down-counting of the clock period of the clock signal is performed with the second number as an initial value until the effective edge is detected before the detection termination time, with the second number at the end of the counting as the first number.

In one embodiment, the pulse calibration number further includes a pulse number, the pulse calibration number, the detection start time, and the frequency division start time of the next detection period are determined according to the detection result, and the step of correcting the frequency division signal of the next detection period includes: if the effective edge is not detected yet by the moment of ending the detection, taking the first number as the pulse reduction number; wherein the number of decreasing pulses is used to indicate the number of decreasing pulses; taking the detection time as a detection starting time and a frequency division starting time; the frequency divided signal is maintained.

In one embodiment, before the step of subtracting the number of pulses from the first number, the clock calibration method further comprises: and carrying out incremental counting on the clock period of the clock signal by taking 0 as an initial value to obtain a count value until an effective edge is detected, and taking the count value at the end of counting as a first number.

In one embodiment, the step of performing pulse calibration on the clock signal in the calibration period to be output according to the detection period, the clock signal, the calibration period and the pulse calibration number includes: correcting the pulse adding quantity according to the detection period and the calibration period, and generating a pulse adding enabling signal according to the calibration period and the corrected pulse adding quantity; and increasing the pulse of the clock signal in the calibration period to be output according to the clock signal and the pulse enable signal.

In one embodiment, the step of correcting the number of applied pulses based on the detection period and the calibration period comprises: if the detection period is equal to the calibration period, maintaining the number of the added pulses unchanged; if the detection period is larger than the calibration period, taking [ N (T1/T2) ] as the corrected added pulse number; if the detection period is less than the calibration period, taking N (T1/T2) as the corrected added pulse number; where [ ] indicates rounding down, N is the number of pulses added before correction, T1 is the calibration period, and T2 is the detection period.

wherein A is the corrected number of added pulses, A _i Is 0 or 1, i, m and n are natural numbers, and m is less than n; the generating of the pulse enable signal according to the calibration period and the corrected number of pulses includes: if A is _i Is 1, in each round of division, a division point is set to pair the previous division pointsThe interval formed by dividing the calibration period is divided into two parts, and the time of the division point is taken as the first trigger time until 2 is obtained ⁱ At a first trigger moment, the front division point is a division point set before the current round division; and generating a pulse with the width of one clock cycle of the clock signal based on the first trigger time to obtain a pulse adding enabling signal.

In one embodiment, generating a pulse having a width of one clock cycle of the clock signal based on the first trigger time, and obtaining the pulse enable signal includes: after delaying a second preset time at the first trigger time, generating a pulse with the width of one clock period of the clock signal to obtain a pulse adding enabling signal; and the second preset duration is integral multiple of the clock period.

In one embodiment, when the pulse calibration number further comprises a decrement pulse number; the step of performing pulse calibration on the clock signal within the calibration period to be output according to the detection period, the clock signal, the calibration period and the pulse calibration number further includes: correcting the pulse reduction number according to the detection period and the calibration period, and generating a pulse reduction enabling signal according to the calibration period and the corrected pulse reduction number; and reducing the pulse of the clock signal in the calibration period to be output according to the clock signal and the pulse reduction enabling signal.

In one embodiment, the step of correcting the number of subtracted pulses based on the detection period and the calibration period comprises: if the detection period is equal to the calibration period, maintaining the pulse reduction quantity unchanged; if the detection period is larger than the calibration period, taking [ M (T1/T2) ] as the corrected pulse reduction number; if the detection period is less than the calibration period, taking M (T1/T2) as the corrected pulse reduction number; where [ ] denotes a rounding-down, M is the number of subtracted pulses before correction, T1 is a calibration period, and T2 is a detection period.

wherein D is the corrected number of subtracted pulses, D _j Is 0 or 1, j, p and n are natural numbers, and p is less than n; the step of generating the minus pulse enable signal according to the calibration period and the corrected number of the minus pulses further comprises: if D is _j If the value of (1) is 1, in each round of division, a division point is set to divide an interval formed by dividing the calibration period by the previous division point into two, and the time of the division point is taken as a second trigger time until 2 is obtained ^j At a second trigger moment, the front division point is a division point set before the current wheel division; and generating a pulse with the width of one clock cycle of the clock signal at each second trigger moment to obtain a pulse reduction enable signal.

Another embodiment of the present invention further provides a clock calibration method, including steps (a1) to (a 12).

And (a1) performing frequency division processing on the clock signal by taking the detection period as a frequency division coefficient to obtain a frequency division signal.

Step (a2), generating a window detection signal according to the detection period and the first preset duration, wherein an effective pulse of the window detection signal corresponds to an effective edge of the reference clock signal, and two ends of the effective pulse of the window detection signal are respectively different from the detection termination time by the first preset duration; and based on the window detection signal, detecting the effective edge of the reference clock signal by the clock signal to obtain the detection result.

A step (a3) of detecting the detection result including the condition that the effective edge of the reference clock signal is detected by the detection termination time, and the time length information between the detection time when the effective edge is detected and the detection termination time; the duration information is characterized by a first number of clock cycles, and the pulse alignment number comprises an applied pulse number. If the effective edge is detected before the detection termination time, counting down the clock period of the clock signals by taking the second number as an initial value at the effective pulse generation time of the window detection signal until the effective edge is detected before the detection termination time, and taking the second number when the counting is finished as the first number; taking the first number as the number of added pulses; taking the detection time as a detection starting time and a frequency division starting time; adjusting the effective pulse of the frequency division signal to enable the effective pulse of the frequency division signal to be generated at the detection time; wherein the number of added pulses is used to indicate the number of added pulses.

Step (a4), if the detection period is equal to the calibration period, keeping the pulse number unchanged; if the detection period is larger than the calibration period, taking [ N (T1/T2) ] as the corrected added pulse number; if the detection period is less than the calibration period, taking N (T1/T2) as the corrected added pulse number; where [ ] indicates rounding down, N is the number of pulses added before correction, T1 is the calibration period, and T2 is the detection period.

Step (a5), the calibration period is characterized as 2 ⁿ The corrected number of added pulses per clock cycle of the clock signal is characterized as:

wherein A is the corrected number of added pulses, A _i Is 0 or 1, i, m and n are natural numbers, and m is less than n; if A _i If the value of (1) is 1, in each round of division, a division point is set to divide an interval formed by dividing the previous division point into two parts in the calibration period, and the time of the division point is taken as a first trigger time until 2 is obtained ⁱ At a first trigger moment, the front division point is a division point set before the current round division; after delaying a second preset time at the first trigger time, generating a pulse with the width of one clock period of the clock signal to obtain a pulse adding enabling signal; and the second preset duration is integral multiple of the clock period.

And a step (a6) of increasing the pulse of the clock signal in the calibration period to be output according to the clock signal and the pulse enable signal.

Step (a7), the pulse calibration quantity further includes a pulse quantity reduction, if no effective edge is detected when the detection is terminated, the clock period of the clock signal is counted up by taking 0 as an initial value to obtain a count value until the effective edge is detected, and the count value at the end of counting is taken as a first quantity; taking the first number as the pulse reduction number; taking the detection time as a detection starting time and a frequency division starting time; maintaining the frequency division signal; wherein the number of reduction pulses is used to indicate the number of reduction pulses.

Step (a8), if the detection period is equal to the calibration period, maintaining the pulse number; if the detection period is larger than the calibration period, taking [ M (T1/T2) ] as the corrected pulse reduction number; if the detection period is less than the calibration period, taking M (T1/T2) as the corrected pulse reduction number; where [ ] denotes a rounding-down, M is the number of subtracted pulses before correction, T1 is a calibration period, and T2 is a detection period.

Step (a9), the calibration period is characterized as 2 ⁿ The corrected number of subtracted pulses is characterized by:

wherein D is the corrected number of subtracted pulses, D _j Is 0 or 1, j, p and n are natural numbers, and p is less than n; the step of generating a decrement pulse enable signal according to the calibration period and the corrected decrement pulse number further comprises: if D is _j If the value of (1) is 1, in each round of division, a division point is set to divide an interval formed by dividing the calibration period by the previous division point into two, and the time of the division point is taken as a second trigger time until 2 is obtained ^j At a second trigger moment, the front segmentation point is a segmentation point set before the current wheel is segmented; and generating a pulse with the width of one clock cycle of the clock signal at each second trigger moment to obtain a pulse reduction enable signal.

And a step (a10) of reducing the pulse of the clock signal in the calibration period to be output according to the clock signal and the pulse reduction enable signal.

It should be understood that, although the steps in the flowchart of fig. 9 described above are sequentially displayed as indicated by arrows and the steps (a1) through (a10) are sequentially displayed as indicated by reference numerals, the steps are not necessarily sequentially performed in the order indicated by the arrows or numerals. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in fig. 9 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily sequential, but may be performed alternately or in alternation with other steps or at least a portion of the other steps or stages.

The above description is only a preferred embodiment of the present application, and not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application, or which are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.

Claims

1. A clock calibration circuit for use in a clock circuit, the clock circuit configured to provide a clock signal, the clock calibration circuit comprising:

detecting the effective edge of the reference clock signal by the clock signal within a time range which has only one effective edge of the reference clock signal and is a first preset time from the detection termination moment of the detection period to obtain a detection result;

2. The clock calibration circuit of claim 1, wherein the detection module is further configured to:

3. The clock calibration circuit according to claim 2, wherein the detection result includes a case where a valid edge of the reference clock signal is detected by the detection termination time, and time length information between the detection time when the valid edge is detected and the detection termination time; the duration information is characterized as a first number of clock cycles of the clock signal; the pulse calibration number comprises a plus pulse number; the detection module is further configured to, if the valid edge is detected before the detection termination time:

taking the first number as the pulse number;

4. The clock calibration circuit of claim 3, wherein the first predetermined duration is a second number of clock cycles of the clock signal, and wherein the detection module is further configured to:

5. The clock calibration circuit of claim 3, wherein the pulse calibration number further comprises a reduced pulse number, and the detection module is further configured to, if the valid edge is not detected by the detection termination time:

the divided signal is maintained.

6. The clock calibration circuit of claim 5, wherein the detection module is further configured to:

7. The clock calibration circuit of claim 3 or 5, wherein the calibration module comprises:

8. The clock calibration circuit of claim 7, wherein the generation control unit is further configured to:

9. The clock calibration circuit of claim 7, wherein the calibration period is characterized as 2 ⁿ The corrected number of added pulses is characterized by:

wherein A is the corrected number of the applied pulses, A _i Is 0 or 1, i, m and n are natural numbers, and m is less than n;

the generation control unit is further configured to:

if A is _i If the value of (1) is 1, in each round of division, a division point is set to divide the interval formed by the division of the calibration period by the previous division point into two, and the time of the division point is taken as a first trigger time until 2 is obtained ⁱ At the first trigger moment, the front division point is atA division point set before the front wheel division;

and generating a pulse with the width of one clock cycle of the clock signal based on the first trigger time to obtain the pulse adding enabling signal.

10. The clock calibration circuit of claim 9, wherein the generation control unit is further configured to:

11. The clock calibration circuit of claim 7, wherein when the pulse calibration number further comprises a reduced pulse number;

12. The clock calibration circuit of claim 11, wherein the generation control unit is further configured to:

13. The clock calibration circuit of claim 11,

the calibration period is characterized as 2 ⁿ The corrected number of subtracted pulses is characterized by:

the generation control unit is further configured to:

14. The clock calibration circuit of claim 11, wherein the pulse compensation unit comprises: the first NOT gate, the second NOT gate, the third NOT gate, the first trigger, the second trigger, the third trigger, the AND gate, the NAND gate, the OR gate, the buffer circuit and the two-way selector;

15. A clock calibration apparatus, the apparatus comprising:

a clock circuit;

and a clock calibration circuit as claimed in any one of claims 1 to 14.

16. A clock calibration method applied to a clock circuit for providing a clock signal, the clock calibration method comprising: