CN115001423A

CN115001423A - Sensing amplifying circuit for collecting multiple physiological electric signals

Info

Publication number: CN115001423A
Application number: CN202210578953.0A
Authority: CN
Inventors: 赵阳; 索研星; 连勇
Original assignee: Shanghai Jiaotong University
Current assignee: Shanghai Jiaotong University
Priority date: 2022-05-16
Filing date: 2022-05-16
Publication date: 2022-09-02

Abstract

A perception amplification circuit for collecting various physiological electric signals is characterized by comprising a chopped wave modulation capacitance coupling instrument amplifier, a programmable gain amplifier and a band-pass filter with adjustable bandwidth, wherein the chopped wave modulation capacitance coupling instrument amplifier, the programmable gain amplifier and the band-pass filter are sequentially connected. The input impedance can be greatly improved by adopting a positive feedback input impedance enhancing technology, but due to the influence of parasitic capacitance, the feedback capacitance needs to be accurately adjusted, and the circuit is prevented from oscillating. In addition, the frequency components of the bioelectrical signal are concentrated in a low frequency range (lower than 1Hz to several kHz), in order to avoid interference caused by extremely low frequency components such as DC offset and baseline drift, and meanwhile, to keep as many low frequency details of the original signal as possible, the sensing analog front end Amplifier (AFE) needs a high-pass cut-off frequency of less than 0.5Hz, which needs a very large RC constant to realize, and can be realized by adopting an off-chip capacitor with the order of μ F to cooperate with an on-chip resistor with the order of M Ω, or a resistor close to the order of T Ω to cooperate with an on-chip capacitor with the order of pF, but all occupy too much on-chip area.

Description

Sensing amplifying circuit for collecting multiple physiological electric signals

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a sensing amplification circuit for collecting various physiological electric signals.

Background

According to the existing reports, the occurrence of diseases of organs of important parts of human bodies such as heart, brain and the like has great threat to human life, and the serious physiological diseases are traceable to a certain extent and can be prevented. Therefore, the real-time long-term monitoring of various physiological signals (such as electrocardio signals ECG, electroencephalogram EEG and the like) of the human body plays an important role in the prevention and treatment of chronic diseases, rehabilitation management, exercise health and scientific endowment.

With the deep cross fusion of microelectronics and biomedical treatment, portable health monitoring equipment represented by an electrocardiogram patch, a sports chest strap and the like is rapidly developed. The equipment is used for realizing long-term real-time health monitoring, and plays an important role in chronic disease prevention and control, exercise health and the like. Common portable bioelectric signals are shown in table 1, and include electrocardiogram (electrocardiograph) ECG, electroencephalogram (electroencephalogragram) EEG, electromyogram (electromyogram) EMG, and Electrooculogram (Electrooculogram) EOG.

TABLE 1

As can be seen from table 1, these bioelectric signals have both low-amplitude and low-frequency band commonalities and multi-amplitude and multi-frequency band differences, so that the research on the analog front-end sense Amplifier (AFE) with low noise, multi-mode and strong anti-interference capability is the key to realize the accurate sensing of various physiological signals.

The existing analog front-end circuit has the following problems: the traditional direct current coupling and alternating current coupling have certain mismatch due to a gain feedback structure, so that the performance of the Common Mode Rejection Ratio (CMRR) is poor, and the detuning of an on-chip proportional capacitor can be greatly reduced by placing the chopping modulator at the connecting end of the input capacitor and the input electrode, so that the CMRR performance is improved. The capacitive coupling AFE adopting the chopping modulation technology can greatly inhibit flicker noise in a circuit. However, when the chopping modulator switches between different clock phases, the input capacitor needs to be charged and discharged inevitably, which results in the reduction of the input impedance and the introduction of charging and discharging ripples. The ripple can be relieved to a certain extent through the pre-charging technology, and the input impedance is improved to a certain extent, but the improvement effect is limited. The input impedance can be greatly improved by adopting a positive feedback input impedance enhancing technology, but due to the influence of parasitic capacitance, the feedback capacitance needs to be accurately adjusted, and the circuit is prevented from oscillating. In addition, the frequency components of the bioelectricity signal are concentrated in a low frequency band (lower than 1Hz to several kHz), in order to avoid interference caused by extremely low frequency components such as DC offset and baseline drift, and simultaneously retain as many low frequency details of the original signal as possible, the sensing analog front end Amplifier (AFE) needs a high-pass cut-off frequency of less than 0.5Hz, which needs a very large RC constant to realize, and can be realized by adopting an off-chip capacitor of the order of μ F to match an on-chip resistor of the order of M Ω, or a resistor close to the order of T Ω to match an on-chip capacitor of the order of pF, but all occupy too much on-chip area.

Disclosure of Invention

The invention aims to overcome the defects in the prior art, a chopped wave modulation capacitance coupling structure is applied to provide a CMRR with high enough intensity, an impedance boosting technology is introduced to boost the input impedance of a sensing amplifying circuit, a direct current servo loop DSL is introduced into a chopped wave modulation capacitance coupling instrument amplifier to provide a required high-pass cut-off frequency less than 0.5Hz, and finally a band-pass filter with adjustable bandwidth is introduced to realize independent adjustment of the bandwidth of an analog front-end circuit, so that the analog front-end circuit applied to monitoring of various physiological electric signals is provided, and the advantages of low noise, multiple modes and high common mode rejection ratio are achieved.

In order to achieve the purpose, the invention adopts the following technical scheme:

a perception amplifying circuit used for collecting various physiological electric signals is characterized by comprising a chopping modulation capacitance coupling instrument amplifier, a programmable gain amplifier and a band-pass filter with adjustable bandwidth, which are connected in sequence;

the chopper modulation capacitance coupling instrument amplifier comprises a first transconductance amplifier, a first direct current servo loop and a clock generator, wherein a first input signal and a second input signal are respectively input to the positive input end and the negative input end of the first transconductance amplifier; the chopper modulation capacitance coupling instrument amplifier is used for modulating and demodulating two paths of input signals, eliminating low-frequency noise of the signals and imbalance of the amplifier, simultaneously performing gain of fixed multiple on the signals, and transmitting the signals to the programmable gain amplifier;

the programmable gain amplifier comprises a second transconductance amplifier and a second direct current servo loop band-pass filter with adjustable bandwidth

The band-pass filter with the adjustable bandwidth comprises a third transconductance amplifier and is used for filtering out-of-band noise of a signal and finally outputting the signal.

The first transconductance amplifier, the second transconductance amplifier and the third transconductance amplifier have the same structure and function, so that the output signal is not distorted in the power supply voltage;

the first transconductance amplifier, the second transconductance amplifier and the third transconductance amplifier respectively comprise a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube, a nineteenth MOS tube, a twentieth MOS tube, a twenty-first MOS tube, a twenty-second MOS tube, a twenty-thirteenth MOS tube, a twenty-fourth MOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a first compensation capacitor, a second compensation capacitor, a third compensation capacitor, a fourth compensation capacitor, a first compensation resistor, a second compensation resistor, a first capacitor, a second capacitor, The third capacitor, the fourth capacitor, the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch and the eighth switch;

the drain electrode of the first MOS tube is connected with the source electrodes of the second MOS tube and the third MOS tube, the grid electrodes of the first MOS tube, the seventh MOS tube and the eighth MOS tube are connected, the drain electrode of the sixth MOS tube is connected with the source electrodes of the fourth MOS tube and the fifth MOS tube, the grid electrodes of the sixth MOS tube, the seventeenth MOS tube and the eighteenth MOS tube are connected with the seventh switch, the drain electrodes of the second MOS tube, the seventeenth MOS tube and the twenty third MOS tube are connected with the source electrode of the fifteenth MOS tube, the drain electrodes of the third MOS tube, the eighteenth MOS tube and the twenty fourth MOS tube are connected with the source electrode of the sixteenth MOS tube, the drain electrodes of the fourth MOS tube and the seventh MOS tube are connected with the source electrode of the ninth MOS tube, the drain electrodes of the fifth MOS tube and the eighth MOS tube are connected with the source electrode of the tenth MOS tube, the drain electrodes of the ninth MOS tube and the tenth MOS tube are connected, the fifteenth MOS tube and the grid electrode of the sixteenth MOS tube are connected, the drain electrode of the ninth MOS tube, the drain electrode of the thirteenth MOS tube, the source electrode of the eleventh MOS tube, the grid electrode of the twenty fourth MOS tube and the third compensation capacitor plate, the drain electrode of the tenth MOS tube, the drain electrode of the fourteenth MOS tube, the source electrode of the twelfth MOS tube, the grid electrode of the nineteenth MOS tube and the upper pole plate of the first compensation capacitor are connected, the drain electrode of the fifteenth MOS tube, the drain electrode of the eleventh MOS tube, the source electrode of the thirteenth MOS tube, the grid electrode of the twelfth MOS tube and the upper pole plate of the fourth compensation capacitor are connected, the drain electrode of the sixteenth MOS tube, the drain electrode of the twelfth MOS tube, the source electrode of the fourteenth MOS tube, the grid electrode of the twentieth MOS tube and the upper pole plate of the second compensation capacitor are connected, the eleventh MOS tube and the grid electrode of the twelfth MOS tube are connected, the thirteenth MOS tube and the grid electrode of the fourteenth MOS tube are connected, the drain electrode of the nineteenth MOS tube and the twentieth MOS tube are connected with the first compensation resistor, the drain electrode of the twenty-first MOS tube and the drain electrode of the twenty-second MOS tube are connected with the second compensation resistor, the lower pole plate of the first compensation capacitor and the lower pole plate of the first compensation capacitor, The third switch is connected, the third compensation capacitor lower polar plate and the fourth compensation capacitor lower polar plate are connected with the second compensation resistor, the second capacitor lower polar plate and the fifth switch, the twenty-third MOS tube grid, the twenty-fourth MOS tube grid, the first capacitor upper polar plate, the second capacitor upper polar plate and the fourth switch are connected, the third switch, the sixth switch and the third capacitor lower polar plate are connected, the fifth switch, the eighth switch and the fourth capacitor lower polar plate are connected, the third capacitor upper polar plate, the fourth switch and the seventh switch are connected, the sixth switch is connected with the eighth switch, the first resistor is connected with the first MOS tube source electrode, the second resistor is connected with the sixth MOS tube source electrode, the third resistor is connected with the seventh MOS tube source electrode, the fourth resistor R4 is connected with the eighth MOS tube source electrode, the fifth resistor is connected with the seventeenth MOS tube source electrode, the sixth resistor is connected with the eighteenth MOS tube source electrode, the seventh resistor is connected with a source electrode of the twenty-third MOS transistor, and the eighth resistor is connected with a source electrode of the twenty-fourth MOS transistor.

The first direct current servo loop and the second direct current servo loop have the same function and structure, and adopt a switched capacitor structure;

the first direct current servo loop and the second direct current servo loop respectively comprise a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a thirteenth switch, a fourteenth switch, a fifteenth switch, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor and a fourth transconductance amplifier;

taking a direct current servo loop of the chopper-modulated capacitive coupling instrumentation amplifier as an example, the input signal is an output signal of the chopper-modulated capacitive coupling instrumentation amplifier, the input signal is input through a tenth switch and a fifteenth switch input end, and the fourteenth switch is used as a signal reset switch and is connected with a thirteenth switch output end, a fifteenth switch output end, a fifth capacitor lower polar plate and a sixth capacitor lower polar plate, the fifth capacitor and the sixth capacitor are integrator input capacitors, a fifth capacitor upper polar plate is connected with a fourth transconductance amplifier negative electrode input end, a ninth capacitor upper polar plate and a tenth switch input end, a sixth capacitor upper polar plate is connected with a fourth transconductance amplifier positive electrode input end, a tenth capacitor upper polar plate and an eleventh switch input end, a tenth switch output end is connected with a ninth switch output end and a seventh capacitor lower polar plate, and an eleventh switch output end is connected with an eighth capacitor upper polar plate, The output end of the twelfth switch is connected, the ninth capacitor lower polar plate is connected with the seventh capacitor lower polar plate and the positive output end of the fourth transconductance amplifier, the tenth capacitor lower polar plate is connected with the eighth capacitor lower polar plate, and the negative output end of the fourth transconductance amplifier is connected; according to the following steps:

f _hp for the high pass cut-off frequency to be generated, C _DSL Is a DSL capacitance, C _fb For feedback of capacitance of capacitive coupling circuit, f _int Is the integration frequency of an integrator, C _in Is the input capacitance of an integrator, C _int Is the integrating capacitance of the integrator.

The fifth capacitor C5 and the sixth capacitor C6 are integrator input capacitors, and have equal capacitance values, the ninth capacitor C9 and the tenth capacitor C10 are integrator capacitors, and the ninth capacitor C9 and the tenth capacitor C10 have equal capacitance values and are far greater than the capacitance values of the fifth capacitor C5 and the sixth capacitor C6, so that a very low high-pass cut-off frequency can be generated.

The clock generator comprises: the circuit comprises a trigger, a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, a first NOT gate N1, a second NOT gate N2, a third NOT gate N3, state control logic AND a 4bit counter; the state control logic sets a four-bit control word, the output of the four-bit control word is connected with a first AND gate together with a reset signal RST, the output signal of the first AND gate AND1 is connected with the reset signal bit of a D flip-flop, the D bit of the D flip-flop is connected with a high level VDD, a trigger bit CLK is connected with a clock signal CLK, an output signal Q is connected with the input ends of a second AND gate N2 AND a third AND gate N3, the output end of the second AND gate 2 is connected with the input end of a first NOT gate N1, the output end of the first NOT gate N1 is connected with the input end of a second NOT gate N2, the output end of the second NOT gate N2 is connected with the input end of a third NOT gate N3, the output end of a third NOT gate N3 is connected with the input ends of the second AND gate 2 AND a third AND gate 3, therefore, the second AND gate, the first NOT gate, the second NOT gate AND the third NOT gate form a ring oscillator, a us-stage oscillation signal is generated, the output signal of the third NOT gate is connected with the 4bit counter, AND the output end of the state control logic is connected with the input end of the state control logic, adjusting the output counting times by setting state control logic, and determining an ultra-low duty cycle clock signal with high level time as a plurality of oscillation clocks; the adjusting interval is 16 steps, namely the counting interval of a 4-bit counter.

The chopper-modulated capacitively coupled instrumentation amplifier further comprises: the direct current servo circuit comprises a first chopper, a second chopper, a third chopper, a fourth chopper, a fifth chopper, a first input capacitor, a second input capacitor, a first feedback capacitor, a second feedback capacitor, a first direct current servo loop capacitor, a second direct current servo loop capacitor, a first adjustable capacitor, a second adjustable capacitor, a first direct current bias resistor and a second direct current resistor;

the gain programmable amplifier further comprises: a third input capacitor, a fourth input capacitor, a third feedback capacitor, a fourth feedback capacitor, a third direct current servo loop capacitor, a fourth direct current servo loop capacitor, a third direct current bias resistor and a fourth direct current bias resistor;

the band-pass filter with adjustable bandwidth further comprises: a fifth input capacitor, a sixth input capacitor, a fifth feedback capacitor, a sixth feedback capacitor, a first feedback resistor, a second feedback resistor, and a 1-bit adjustable bias current (I) _bias < 1: 0 >), a first switch and a second switch;

the first chopper first input end is connected with a signal input end Vip, the first chopper second input end is connected with a signal input end Vin, the first chopper first output end is connected with a first input capacitor lower pole plate and a second adjustable capacitor upper pole plate respectively, the first chopper second output end is connected with a second input capacitor lower pole plate and a first adjustable capacitor upper pole plate respectively, the first input capacitor upper pole plate is connected with a first direct current bias resistor, a first transconductance amplifier positive input pole, a second feedback capacitor upper pole plate and a fourth chopper first input end respectively, the second input capacitor upper pole plate is connected with a second direct current bias resistor, a first transconductance amplifier negative input pole, a first feedback capacitor upper pole plate and a fourth chopper second input end respectively, the second chopper input end is connected with a first transconductance amplifier positive pole plate, a second chopper input end is connected with a first transconductance amplifier positive pole plate, The output end of the second chopper is connected with the output end of the third chopper, the output end of the fifth chopper, the positive and negative output ends of the first direct current servo loop, the upper polar plate of the third input capacitor and the upper polar plate of the fourth input capacitor; the output end of the fourth chopper is connected with the upper pole plate of the first direct current servo loop capacitor and the upper pole plate of the second direct current servo loop capacitor, the positive and negative input ends of the first direct current servo loop capacitor are connected with the lower pole plate of the first direct current servo loop capacitor and the lower pole plate of the second direct current servo loop capacitor, the input end of the third chopper is connected with the lower pole plate of the first feedback capacitor and the lower pole plate of the second feedback capacitor, and the input end of the fifth chopper is connected with the lower pole plate of the first adjustable capacitor and the lower pole plate of the second adjustable capacitor;

the third input capacitor upper polar plate, the third direct current bias resistor, the fourth feedback capacitor upper polar plate and the fourth direct current servo loop capacitor upper polar plate are connected, the fourth input capacitor upper polar plate, the fourth direct current bias resistor, the third feedback capacitor upper polar plate and the third direct current servo loop capacitor upper polar plate are connected, the positive input end and the negative input end of the second direct current servo loop are connected with the third direct current servo loop capacitor lower polar plate and the fourth direct current servo loop capacitor lower polar plate, the third feedback capacitor lower polar plate, the second direct current servo loop positive output end, the second transconductance amplifier positive output end and the sixth input capacitor lower polar plate are connected, and the fourth feedback capacitor lower polar plate, the second direct current servo loop negative output end, the second transconductance amplifier negative output end and the fifth input capacitor lower polar plate are connected;

the fifth input capacitor upper polar plate, the third transconductance amplifier positive input end, the first feedback resistor and the fifth feedback capacitor upper polar plate are connected, the sixth input capacitor upper polar plate, the third transconductance amplifier negative input end, the second feedback resistor and the sixth feedback capacitor upper polar plate are connected, the first feedback resistor is connected with the first switch, the second feedback resistor is connected with the second switch, the fifth feedback capacitor lower polar plate is connected with the first switch, and the sixth feedback capacitor is connected with the second switch and the third transconductance amplifier output end.

Compared with the prior art, the invention has the following advantages:

(1) the invention uses a three-level analog front-end circuit system to carry out hierarchical reasonable design aiming at different functional requirements. The chopper modulation capacitance coupling instrument amplifier determines the performances of the whole noise, the common mode rejection ratio, the input impedance and the like of the analog front-end circuit; the programmable gain amplifier solves the problem of large amplitude difference of different biological signals, improves the readability of the signals and is convenient for subsequent data processing work; the band-pass filter with adjustable bandwidth is provided with different high-low pass cut-off frequencies which can be independently adjusted.

(2) The invention adopts a switched capacitor direct current servo loop to realize effective suppression of electrode DC offset, and simultaneously generates extremely low high-pass cut-off frequency to eliminate low-frequency noise and keep the low-frequency characteristic of signals;

(3) the invention adopts an ultra-low duty ratio clock generator to generate an ultra-low duty ratio signal f _DU The control switches S1 and S2 and the resistors Rfb1 and Rfb2 form a duty ratio resistor with a maximum resistance value (T omega level), so that a multi-step adjustable means is provided while an extremely low high-pass cut-off frequency is generated in a band-pass filter, and the area of a chip is reduced;

(4) the invention adopts transconductance amplifiers (GM1, GM2 and GM3) with full swing input and output in the chopping modulation capacitance coupling instrument amplifier, the programmable gain amplifier and the band-pass filter with adjustable bandwidth, thereby ensuring the input swing of the maximized input signal.

(5) According to the invention, a switched capacitor direct current servo loop is introduced into a chopped wave modulation capacitance coupling instrument amplifier and a programmable gain amplifier, a very low high-pass cut-off frequency is generated by introducing a very large resistance value into an adjustable bandwidth band-pass filter and combining with a feedback capacitor, and three-level low-frequency inhibition capacities are superposed, so that out-of-band low-frequency noise is greatly inhibited; the gain of the instrument amplifier is fixed and cannot be adjusted by combining the limitation of the swing amplitude of the input signal and the consideration of the noise, and the introduction of the programmable gain amplifier into the second stage can further amplify physiological signals with different amplitudes under the condition of not reducing the common-mode rejection ratio and the noise rejection capability of the analog front-end circuit; because the instrument amplifier and the gain adjustable amplifier introduce bandwidth adjustment to reduce gain precision and load carrying capacity, and the third stage introduces a bandwidth adjustable band-pass filter, the independent adjustment of high and low-pass cut-off frequencies can carry out accurate amplification and noise suppression aiming at physiological signals of different frequency bands, and meanwhile, the low-pass cut-off frequency lower than the chopping frequency can successfully suppress high-frequency burrs introduced in the signals by the chopper. The three-stage circuit in the invention works cooperatively, combines advantages, and introduces different functions for collecting multiple physiological electric signals on the premise of not influencing the performance of the analog front-end circuit.

Drawings

FIG. 1 is a system architecture diagram of a sense amplifier circuit for multiple physiological electrical signal acquisition according to the present invention

FIG. 2 is a circuit diagram of a transconductance amplifier employed in the present invention

FIG. 3 is a system architecture diagram of a DC servo loop employed in the present invention

FIG. 4 is a system architecture diagram of an ultra-low duty cycle clock generator employed in the present invention

FIG. 5 is a graph of gain tuning test of the present invention

FIG. 6 is a diagram of a bandwidth adjustable test chart of the present invention

FIG. 7 is a dry electrode electrocardiosignal test chart of the present invention

FIG. 8 is an electromyographic signal test chart of the electrode of the present invention

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of implementations of the present invention, and not all embodiments. The embodiments of the present invention, and all other embodiments obtained by a person of ordinary skill in the art without any inventive work, belong to the scope of protection of the present invention.

Referring to fig. 1, fig. 1 is a system architecture diagram of a sense amplifier circuit for collecting multiple physiological electrical signals according to the present invention, which includes a chopper modulation capacitance coupling instrumentation amplifier, a programmable gain amplifier and a band-pass filter with adjustable bandwidth.

The input signal of the positive end of the chopper modulation capacitance coupling instrument amplifier is a first input signal Vip, and the input signal of the negative end of the chopper modulation capacitance coupling instrument amplifier is a second input signal Vin;

the output signal of the band-pass filter with adjustable bandwidth is a first output signal;

the following describes the operation of the analog front end provided in this embodiment. Firstly, an analog signal input from the outside is modulated to an odd harmonic of a high-frequency chopping signal through a first-stage chopper CH1, then the modulated signal is connected to a differential input end of a first transconductance amplifier GM1 for amplification, and meanwhile, a feedback signal of a negative feedback loop is connected to an inverting input end of the first transconductance amplifier to stabilize the gain of the chopping modulation capacitive coupling amplifier, wherein the gain can be expressed as:

wherein A is ₀ Is the open loop gain, C, of the first transconductance amplifier GM1 _fb To feedback capacitance value, C _in Is the input capacitance value. The second stage chopping switch CH2 demodulates the amplified signal to obtain an amplified initial analog signal. The signal is the output signal of the chopper-modulated capacitively coupled instrumentation amplifier. The output end of the chopper modulation capacitance coupling instrument amplifier is connected with the input end of the programmable gain amplifier, the output signal of the instrument amplifier is used as an input signal to enter the programmable gain amplifier to be further amplified in the programmable gain amplifier, the gain of the programmable gain amplifier is consistent with the representation method of the chopper modulation capacitance coupling amplifier, a signal is output from the output end of the second transconductance amplifier GM2, and the signal is the output signal of the programmable gain amplifier. The output end of the programmable gain amplifier is connected with the input end of the bandwidth-adjustable band-pass filter, the output signal of the programmable gain amplifier is used as an input signal to enter the bandwidth-adjustable band-pass filter, and finally the bandwidth-adjustable band-pass filter converts the input differential signal into a single-ended signal and outputs the final signal of the analog front-end circuit. In the chopping modulation capacitive coupling, a chopper in a negative feedback loop is used for modulating an amplified signal output by a first transconductance amplifier to a chopping signal frequency, and is matched with an input signal modulated to the chopping signal frequency by the first chopper to form negative feedback. A high-pass pole is constructed by the DC servo loop, the DC offset of the electrode is attenuated, the chopper on the DC servo loop modulates the output signal of the DC servo loop to the frequency of a chopping signal matched with the input signal modulated by the first chopper and feeds back the signal to the input end to form the high-pass pole which can be expressed as

Wherein f is _hp High-pass cut-off frequency, f, formed for a DC servo loop ₀ Is the unity gain cut-off frequency, C, of the DC servo loop _hp For the output capacitance, C, of the DC servo loop _in Is the input capacitance. The working principle of the direct current servo loop in the programmable gain amplifier is the same, and the influence caused by direct current offset of the electrode is further inhibited.

Specifically, referring to fig. 1, a chopper-modulated capacitively-coupled instrumentation amplifier includes: first chopper CH ₁ A second chopper CH ₂ A third chopper CH ₃ A fourth chopper CH ₄ And the fifth chopper is turned off CH ₅ A first input capacitor C _in1 A second input capacitor C _in2 A first feedback capacitor Cfb1, a second feedback capacitor Cfb2, a first DC servo loop capacitor C _DSL1 The first direct current servo loop circuit comprises a first direct current servo loop capacitor CDSL2, a first adjustable capacitor Cpf1, a second adjustable capacitor Cpf2, a first direct current bias resistor Rb1, a second direct current resistor Rb2, a first transconductance amplifier Gm1, a first direct current servo loop DSL1 and a clock generator; the output end of a first chopper CH1 is connected with the lower pole plate of a first input capacitor Cin1 and a second adjustable capacitor Cpf2, the output end of the first chopper CH1 is connected with the lower pole plate of a second input capacitor Cin2 and a first adjustable capacitor Cpf2, the upper pole plate of a first input capacitor Cin1 is connected with a first direct current bias resistor Rb1, the positive input pole of a first transconductance amplifier Gm1, the upper pole plate of a second feedback capacitor Cfb2 and the input end of a fourth chopper, the upper pole plate of the second input capacitor Cin2 is connected with a second direct current bias resistor Rb2, the negative input pole of the first transconductance amplifier Gm1, the upper pole plate of the first feedback capacitor Cfb1 and the input end chopper of the fourth chopper, the second chopper input end is connected with the positive and negative output ends of the first transconductance amplifier Gm1, the output end of the second chopper is connected with the output end of the third chopper, the output end of a fifth chopper, the positive and negative output end of a first direct current servo loop DSL1, the upper pole plate of the third input capacitor Cin3 and the upper pole plate of the fourth input capacitor Cin4, the output end of the fourth chopper is connected with the upper pole plates of the first direct current servo loop CDSL1 and the second direct current servo loop CDSL2,the lower pole plates of the first direct current servo loop CDSL1 and the second direct current servo loop CDSL2 are connected with the positive and negative input ends of the first direct current servo loop DSL1, and the first feedback capacitor Cfb1 and the second feedback capacitor C are connected with the positive and negative input ends of the first direct current servo loop DSL1 _fb2 The lower plate of the first adjustable capacitor Cpf1 and the lower plate of the second adjustable capacitor Cpf2 are connected with the input end of the fifth chopper.

In this embodiment, the first input capacitor C _in1 And a second input capacitance C _in2 Has the same capacitance value, and the first feedback capacitor C _fb1 And a second feedback capacitor C _fb2 Have the same capacitance value, and the first input capacitor C _in1 A second input capacitor C _in2 A first feedback capacitor C _fb1 A second feedback capacitor C _fb2 Are all fixed capacitors.

The gain calculation based on the capacitively coupled feedback is:

wherein G is the closed-loop gain of the capacitively coupled instrumentation amplifier, C _in To input a capacitance value, C _fb For feedback of capacitance value, A ₀ The gain is opened for the transconductance amplifier. In this embodiment, the ratio of the first input capacitor to the first feedback capacitor is the same as the ratio of the second input capacitor to the second feedback capacitor, both of which are 100, so that the gain of the chopper-modulated capacitive-coupled instrument amplifier is 100 times, and the first transconductance amplifier G is a feedback amplifier _m The gain of 1 is 104 dB.

First chopper CH ₁ And a second chopper CH ₂ Respectively located in the first transconductance amplifier G _m1 The input terminal and the output terminal are both used for modulating the flicker noise and the direct current offset voltage so as to reduce the influence of the flicker noise and the direct current offset voltage. Wherein the first chopper CH ₁ A second chopper CH for modulating the first and second input signals from low frequency to high frequency ₂ A first transconductance amplifier G _m1 Is modulated to a low frequency while simultaneously passing a first cross-over to an amplifier G _m1 Input node induced low frequency noise and mismatch modulationTo high frequencies and eliminated at the band-pass filter stage.

Fig. 4 is a system architecture diagram of an ultra-low duty cycle clock generator employed in the present invention, including: the circuit comprises a D flip-flop, a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, a first NOT gate N1, a second NOT gate N2, a third NOT gate N3, state control logic AND a 4-bit counter.

In this embodiment, the state control logic first sets a four-bit control word, the output of which is connected to the first AND gate together with the reset signal RST, the output signal of the first AND gate AND1 is connected to the reset signal bit of the D flip-flop, the D bit of the D flip-flop is connected to the high level VDD, the trigger bit elk is connected to the clock signal CLK, the output signal Q is connected to the input terminals of the second AND gate AND2 AND the third AND gate AND3, the output of the second AND gate AND2 is connected to the input terminal of the first not gate N1, the output terminal of the first not gate N1 is connected to the input terminal of the second not gate N2, the output terminal of the second not gate N2 is connected to the input terminal of the third not gate N3, the output terminal of the third not gate N3 is connected to the input terminals of the second AND gate AND2 AND the third AND gate 3, so that the second AND gate, the first not gate, the second not gate AND the third not gate form a ring oscillator, which generates the us-level oscillation signal, the output signal of the third not gate N3 is connected to the AND gate counter, AND the output terminal of the state control logic, by setting the state control logic and adjusting the output counting times, the clock signal with ultra-low duty ratio and high level time as a plurality of oscillation clocks can be determined to be output. The adjusting interval is 16 steps, namely the counting interval of a 4-bit counter.

The equivalent resistance in the duty cycle is:

R _eq is an equivalent resistance value, R _f D is the duty cycle for the feedback resistor. In this embodiment, R _f Is a first feedback resistor R _fb1 And a second feedback resistor R _fb2 The duty ratio clock output of the clock generator, namely the output end Q of the D trigger is connected with the control ends of the first switch S1 and the second switch S2 to control the state of the switches, the high level is the switch closure, and the low level is the switch breakOn, the two resistance values are equal and in the order of 10M Ω, and the duty ratio D is greater than 1/100000, so that the resistance value in the order of T Ω can be generated according to f _hp ＝1/R _fb C _in ，C _in The input capacitor of the band-pass filter is a pF stage, so that a sufficiently low high-pass cut-off frequency can be generated under the condition of saving a relatively large area, and the state control logic ensures that the duty ratio can be adjusted, so that the high-pass cut-off frequency can be adjusted.

Specifically, referring to fig. 1, the gain programmable amplifier includes: third input capacitance C _in3 A fourth input capacitor Cin4, a third feedback capacitor Cfb3, a fourth feedback capacitor Cfb4, a third dc servo loop capacitor CDSL3, a fourth dc servo loop capacitor CDSL4, a second dc servo loop DSL2, a second transconductance amplifier Gm2, a third dc bias resistor Rb3, and a fourth dc bias resistor Rb 4; an upper plate of a third input capacitor Cin3, an upper plate of a third direct current bias resistor Rb3, an upper plate of a fourth feedback capacitor Cfb4 and an upper plate of a fourth direct current servo loop capacitor CDSL4 are connected, an upper plate of a fourth input capacitor Cin4, a fourth direct current bias resistor Rb4, an upper plate of a third feedback capacitor Cfb3 and an upper plate of a third direct current servo loop capacitor CDSL3 are connected, a lower plate of a third direct current servo loop CDSL3 and a lower plate of a fourth direct current servo loop CDSL4 are connected with a positive input end and a negative input end of a second direct current servo loop DSL2, a lower plate of the third feedback capacitor Cfb3, a positive output end of the second direct current servo loop DSL2, a positive output end of a second transconductance amplifier Gm2 and a lower plate of a sixth input capacitor Cin6 are connected, and a lower plate of the fourth feedback capacitor Cfb4, a negative output end of the second direct current servo loop DSL2, a negative transconductance amplifier Gm2 and a negative transconductance output end of a fifth input capacitor Gm 5 are connected.

In this embodiment, the third input capacitor C _in3 And a fourth input capacitor C _in4 Has the same and adjustable capacitance value, and a third feedback capacitor C _fb3 And a fourth feedback capacitor C _fb4 Has the same capacitance value, and a third input capacitor C _in3 A third feedback capacitor C _fb3 And the fourth input capacitance C _in4 A fourth feedback capacitor C _fb4 The ratio of the gain of the programmable gain amplifier is controlled.

In the embodiment, a switched capacitor direct current servo loop is introduced into a chopper modulation capacitance coupling instrument amplifier and a programmable gain amplifier, a very large resistance value is introduced into an adjustable bandwidth band-pass filter to be combined with a feedback capacitor to generate a very low high-pass cut-off frequency, and three-level low-frequency inhibition capacities are superposed to greatly inhibit out-of-band low-frequency noise; the gain of the instrument amplifier is fixed and cannot be adjusted by combining the limitation of the swing amplitude of the input signal and the consideration of the noise, and the introduction of the programmable gain amplifier into the second stage can further amplify physiological signals with different amplitudes under the condition of not reducing the common-mode rejection ratio and the noise rejection capability of the analog front-end circuit; because the instrument amplifier and the gain adjustable amplifier introduce bandwidth adjustment to reduce gain precision and load carrying capacity, and the third stage introduces a bandwidth adjustable band-pass filter, the independent adjustment of high and low-pass cut-off frequencies can carry out accurate amplification and noise suppression aiming at physiological signals of different frequency bands, and meanwhile, the low-pass cut-off frequency lower than the chopping frequency can successfully suppress high-frequency burrs introduced in the signals by the chopper. The three-stage circuit in the invention works cooperatively, combines advantages, and introduces different functions for collecting multiple physiological electric signals on the premise of not influencing the performance of the analog front-end circuit.

Specifically, referring to fig. 1, the band-pass filter with adjustable bandwidth includes: fifth input capacitance C _m5 Sixth input capacitor Cin6, fifth feedback capacitor Cfb5, sixth feedback capacitor Cfb6, first feedback resistor Rfb1, second feedback resistor Rfb2, third transconductance amplifier Gm3, 1-bit adjustable bias current Ibias < 1: 0 >, first switch S1, second switch S2; an upper plate of a fifth input capacitor Cin5, a positive input end of a third transconductance amplifier, a first feedback resistor Rfb1 and an upper plate of a fifth feedback capacitor Cfb5 are connected, an upper plate of a sixth input capacitor Cin6, a negative input end of the third transconductance amplifier, a second feedback resistor Rfb2 and an upper plate of a sixth feedback capacitor Cfb6 are connected, the first feedback resistor Rfb1 is connected with a first switch S1, the second feedback resistor Rfb2 is connected with a second switch S2, a lower plate of the fifth feedback capacitor Cfb5 is connected with a first switch S1, the sixth feedback capacitor Cfb6, a second switch S2 and the third transconductance amplifier G6324 are connected with the upper plate of the fifth feedback capacitor Cfb6, the upper plate of the third feedback capacitor Cfb 3925, the upper plate of the sixth feedback capacitor Cfb1 is connected with a second switch S1, and the upper plate of the sixth feedback capacitor Cfb6 is connected with a second switch S2 and the upper plate of the third transconductance amplifier G _m3 The output is connected.

In this embodiment, the fifth input powerContainer C _in5 And a sixth input capacitor C _in6 Has the same capacitance value, the first feedback resistor R _fb1 And a second feedback resistor R _fb2 Has the same resistance value, and a fifth feedback capacitor C _fb5 And a sixth feedback capacitor C _fb6 Have the same capacitance value, and the fifth input capacitor G _in5 A sixth input capacitor C _in6 A first feedback resistor R _fb1 A second feedback resistor R _fb2 A fifth feedback capacitor C _flb5 A sixth feedback capacitor C _fb6 All are fixed capacitors or resistors; fifth input capacitance C _in5 And a fifth feedback capacitor C _fb5 And sixth input capacitance C _in6 And a sixth feedback capacitor C _fb6 The ratio of the first feedback resistor to the second feedback resistor is equal to 1, so that the gain of the band-pass filter is unity, and meanwhile, the third feedback resistor and the fourth feedback resistor are duty ratio resistors to limit the high-pass cut-off frequency of the band-pass filter; adjusting the third transconductance amplifier G _m3 The tail current of (3) can then adjust its low-pass cut-off frequency.

Referring to fig. 2, fig. 2 is a circuit diagram of a transconductance amplifier used in the present invention, which adopts a structure combining a conventional folded cascode and a classa. As shown, a first transconductance amplifier G _m1 A second transconductance amplifier G _m2 And a third transconductance amplifier G _m3 Both comprise: a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, a fourteenth MOS transistor M14, a fifteenth MOS transistor M15, a sixteenth MOS transistor M16, a seventeenth MOS transistor M17, an eighteenth MOS transistor M18, a nineteenth MOS transistor M19, a twentieth MOS transistor M20, a twenty-first MOS transistor M21, a twelfth Cc MOS transistor M22, a second thirteenth MOS transistor M23, a fourteenth Cc MOS transistor M24, a first resistor R24, a second resistor R24, a third resistor R24, a fourth resistor R24, a sixth resistor R24, a seventh resistor R24, a seventh resistor, a 36r 24, a compensation capacitor R24, a compensation capacitor, A first capacitor C1, a second capacitor C2, and a third capacitorA capacitor C3, a fourth capacitor C4, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7 and an eighth switch S8; a drain of the first MOS transistor M1 is connected to sources of the second MOS transistor M2 and the third MOS transistor M3, gates of the first MOS transistor M1, the seventh MOS transistor M1 and the eighth MOS transistor M1 are connected, a drain of the sixth MOS transistor M1 is connected to sources of the fourth MOS transistor M1 and the fifth MOS transistor M1, gates of the sixth MOS transistor M1, the seventeenth MOS transistor M1 and the eighteenth MOS transistor M1 are connected to the seventh switch S1, a drain of the second MOS transistor M1, a drain of the seventeenth MOS transistor M1, a drain of the thirteenth MOS transistor M1 is connected to a source of the fifteenth MOS transistor M1, a drain of the third MOS transistor M1, a drain of the eighteenth MOS transistor M1, a drain of the fourteenth MOS transistor M1 is connected to a source of the ninth MOS transistor M1, a drain of the eighth MOS transistor M1, a drain of the ninth MOS transistor M1 is connected to a drain of the ninth MOS transistor M1, a ninth MOS transistor M1, a ninth MOS 1, a drain of the ninth MOS 1, a ninth MOS transistor M1, a drain of the ninth MOS transistor M1, a drain of the ninth MOS transistor M1, a ninth MOS 1, a ninth transistor M1, a ninth MOS transistor M1, a ninth MOS 1, a ninth transistor M1, a drain of the ninth MOS, a ninth transistor M1, and a ninth transistor M1, a ninth MOS, A drain of the thirteenth MOS transistor M13, a source of the eleventh MOS transistor M11, a gate of the twenty-first MOS transistor M21 and an upper plate of the third compensation capacitor Cc3 are connected, a drain of the tenth MOS transistor M10, a drain of the fourteenth MOS transistor M14, a source of the twelfth MOS transistor M12, a gate of the nineteenth MOS transistor M19 and an upper plate of the first compensation capacitor Cc1 are connected, a drain of the fifteenth MOS transistor M15, a drain of the eleventh MOS transistor M11, a source of the thirteenth MOS transistor M13, a gate of the twenty-second MOS transistor M22 and an upper plate of the fourth compensation capacitor Cc4 are connected, a drain of the sixteenth MOS transistor M16, a drain of the twelfth MOS transistor M12, a source of the fourteenth MOS transistor M14, a gate of the twentieth MOS transistor M20 and an upper plate of the second compensation capacitor c2 are connected, a drain of the eleventh MOS transistor M11, a source of the eleventh MOS transistor M11, a gate of the twenty-first MOS transistor M13, a gate of the fourteenth MOS transistor M13 and a gate of the nineteenth compensation capacitor Cc 13 are connected, drains of a twenty-first MOS transistor M21 and a second twelve MOS transistor M22 are connected with a second compensation resistor Rc2, a lower plate of a first compensation capacitor Cc1 and a lower plate of a second compensation capacitor Cc2 are connected with a first compensation resistor Rc1, a lower plate of a first capacitor C1 and a third switch S3, a lower plate of a third compensation capacitor Cc2 and a lower plate of a fourth compensation capacitor Cc4 are connected with a second compensation resistor Rc2, a lower plate of a second capacitor C2 and a fifth switch S3A switch S5, a gate of a twenty-third MOS transistor M23, a gate of a twenty-fourth MOS transistor M24, an upper plate of a first capacitor C1, an upper plate of a second capacitor C1, and a fourth switch S1, a third switch S1, a sixth switch S1, a lower plate of the third capacitor C1, a fifth switch S1, an eighth switch S1, and a lower plate of the fourth capacitor C1 are connected, an upper plate of the third capacitor C1, an upper plate of the fourth capacitor C1, a fourth switch S1, and a seventh switch S1 are connected, a sixth switch S1 is connected to the eighth switch S1, a source of the first resistor R1 is connected to the first MOS transistor M1, a source of the second resistor R1 is connected to the sixth transistor M1, a third resistor R1 is connected to the seventh transistor M1, a fourth resistor R1 is connected to the eighth MOS transistor M1, a source of the fifth resistor R1 is connected to the seventeenth MOS transistor M1, a source of the fifth resistor R1, a seventeenth transistor M1 is connected to the third resistor R1, the eighth resistor R8 is connected with the source of the twenty-fourth MOS transistor M24.

The transconductance amplifier in this embodiment can provide a common mode rejection ratio CMRR with better performance. It is assumed that the noise, common-mode to common-mode gain, common-mode to differential gain, and differential gain of each amplification stage are n1, ACC1, ACD1, a1, n2, ACC2, ACD2, a2, and n3, ACC2, ACD2, A3, respectively. The common mode rejection ratio CMRR and the input reference noise of the system are:

to mitigate CMRR degradation caused by the latter two polynomials, the differential IA and PGA stages are the best choice.

Fig. 3 shows a switched capacitor dc servo loop provided in an embodiment of the present invention, which specifically includes: a ninth switch S9, a tenth switch S10, an eleventh switch S11, a twelfth switch S12, a thirteenth switch S13, a fourteenth switch S14, a fifteenth switch S15, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, and a fourth transconductance amplifier Gm 4.

In this embodiment, the dc servo loop of the chopper-modulated capacitive-coupled instrumentation amplifier has the same structure as the dc servo loop of the programmable gain amplifier, and the dc servo loop of the chopper-modulated capacitive-coupled instrumentation amplifier will be described as an example. For the switched capacitor direct current servo loop, the input signal is the output signal of a chopper-modulated capacitor-coupled instrumentation amplifier, the input signal is input through a tenth switch and a fifteenth switch input end, a fourteenth switch is used as a signal reset switch and is connected with a thirteenth switch output end, a fifteenth switch output end, a fifth capacitor lower polar plate and a sixth capacitor lower polar plate, the fifth capacitor and the sixth capacitor are integrator input capacitors, a fifth capacitor upper polar plate is connected with a fourth transconductance amplifier negative electrode input end, a ninth capacitor upper polar plate and a tenth switch input end, a sixth capacitor upper polar plate is connected with a fourth transconductance amplifier positive electrode input end, a tenth capacitor upper polar plate and an eleventh switch input end, a tenth switch output end is connected with a ninth switch output end and a seventh capacitor lower polar plate, an eleventh switch output end is connected with an eighth capacitor upper polar plate and a twelfth switch output end, the ninth capacitor lower polar plate is connected with the seventh capacitor lower polar plate and the positive output end of the fourth transconductance amplifier, the tenth capacitor lower polar plate is connected with the eighth capacitor lower polar plate and the negative output end of the fourth transconductance amplifier.

The extremely low high-pass cut-off frequency of the analog front-end circuit is realized by a direct current servo loop based on a switched capacitor integrator, according to the following steps:

f _hp for the high pass cut-off frequency generated, C _DSL Is a DSL capacitance, C _fb For feedback of capacitance of capacitive coupling circuit, f _int Is the integration frequency of an integrator, C _in Is the input capacitance of an integrator, C _int Is the integrating capacitance of the integrator.

In the invention, the fifth capacitor C5 and the sixth capacitor C6 are integrator input capacitors and have equal capacitance values, the ninth capacitor C9 and the tenth capacitor C10 are integration capacitors, and the ninth capacitor C9 and the tenth capacitor C10 have equal capacitance values and are far larger than the fifth capacitor C5 and the sixth capacitor C6, so that an extremely low high-pass cut-off frequency can be generated.

The circuit level simulation of the embodiment adopts an SMIC 0.18 μm BCD process, and is obtained by using an SMIC 0.18 μm BCD process slice, and the power supply voltage for the circuit to work is 1.8V. The test results are shown in fig. 5, fig. 6, fig. 7, and fig. 8, where fig. 5 is a gain-adjustable test chart, fig. 6 is a bandwidth-adjustable test chart, fig. 7 is a dry electrode electrocardiosignal test chart of the present invention, and fig. 8 is an electrode-attached electromyographic signal test chart of the present invention. According to fig. 5, the gain of the analog front-end circuit can be adjusted from 40dB to 63 dB; according to fig. 6, the high-pass cut-off frequency of the analog front-end circuit can be adjusted from 100mHz level to 1Hz level, and the low-pass cut-off frequency can be adjusted from hundred Hz level to kHz level; therefore, during testing, the physiological electrical signals with different amplitudes and different frequencies can be amplified, out-of-band noise is eliminated, and according to the results shown in fig. 7 and 8, the myoelectric signals and the electrocardio signals have different amplitudes and frequency bands, and after being collected and amplified by the analog front-end circuit under different settings, the physiological signals with similar amplitudes and convenient analysis and observation are generated.

Claims

1. A perception amplifying circuit used for collecting various physiological electric signals is characterized by comprising a chopped wave modulation capacitance coupling instrument amplifier, a programmable gain amplifier and a band-pass filter with adjustable bandwidth which are connected in sequence;

the chopper-modulated capacitively coupled instrumentation amplifier comprises a first transconductance amplifier (G) _m1 ) A first direct current servo loop (DSL) ₁ ) And a clock generator, the first transconductance amplifier (G) _m1 ) A first input signal (Vip) and a second input signal (Vin) are respectively input to a positive input end and a negative input end; the chopper modulation capacitance coupling instrument amplifier is used for modulating and demodulating two paths of input signals, eliminating low-frequency noise of the signals and imbalance of the amplifier, simultaneously performing gain of fixed multiple on the signals, and transmitting the signals to the programmable gain amplifier;

the programmable gain amplifier comprises a second transconductance amplifier (Gm2) and a second direct current servo loop (DSL2) and is used for further amplifying the signal modulated and amplified by the chopper-modulated capacitor-coupled amplifier and transmitting the signal to the band-pass filter with adjustable bandwidth

The band-pass filter with adjustable bandwidth comprises a third transconductance amplifier (Gm3) for filtering out-of-band noise of the signal and finally outputting a signal (Vout).

2. The sense amplifier circuit for acquisition of multiple physiological electrical signals according to claim 1, wherein the first transconductance amplifier (Gm1), the second transconductance amplifier (Gm2) and the third transconductance amplifier (Gm3) have the same structure and function, so as to ensure that the output signal is not distorted in the supply voltage;

the first transconductance amplifier (G) _m1 ) A second transconductance amplifier (G) _m2 ) And a third transconductance amplifier (G) _m3 ) All comprise a first MOS tube (M) ₁ ) And a second MOS transistor (M) ₂ ) And the third MOS transistor (M) ₃ ) And the fourth MOS transistor (M) ₄ ) And the fifth MOS transistor (M) ₅ ) And a sixth MOS transistor (M) ₆ ) The seventh MOS transistor (M) ₇ ) And the eighth MOS transistor (M) ₈ ) And the ninth MOS transistor (M) ₉ ) The tenth MOS transistor (M) ₁₀ ) Eleventh MOS transistor (M) ₁₁ ) Twelfth MOS transistor (M) ₁₂ ) Thirteenth MOS transistor (M) ₁₃ ) Fourteenth MOS transistor (M) ₁₄ ) Fifteenth MOS transistor (M) ₁₅ ) Sixteenth MOS transistor (M) ₁₆ ) Seventeenth MOS transistor (M) ₁₇ ) Eighteenth MOS transistor (M) ₁₈ ) Nineteenth MOS transistor (M) ₁₉ ) Twentieth MOS transistor (M) ₂₀ ) Twenty-first MOS transistor (M) ₂₁ ) Twenty-second MOS transistor (M) ₂₂ ) Twenty-third MOS tube (M) ₂₃ ) Twenty-fourth MOS transistor (M) ₂₄ ) A first resistor (R) ₁ ) A second resistor (R) ₂ ) A third resistor (R) ₃ ) A fourth resistor (R) ₄ ) A fifth resistor (R) ₅ ) A sixth resistor (R) ₆ ) A seventh resistor (R) ₇ ) Eighth resistor (R) ₈ ) A first compensation capacitor (C) _c1 ) A second compensation capacitor (C) _c2 ) A third compensation capacitor (C) _c3 ) A fourth compensation capacitor (C) _c4 ) A first compensation resistor (R) _c1 ) A second compensation resistor (R) _c2 ) A first capacitor (C) ₁ ) A second capacitor (C) ₂ ) A third capacitor (C) ₃ ) A fourth capacitor (C) ₄ ) And a third switch (S) ₃ ) And a fourth switch (S) ₄ ) And a fifth switch (S) ₅ ) And a sixth switch (8) ₆ ) And a seventh switch (S) ₇ ) And an eighth switch (S) ₈ )；

The first MOS transistor (M) ₁ ) And the second MOS transistor (M) ₂ ) And the third MOS transistor (M) ₃ ) Is connected with the source electrode of the first MOS tube (M) ₁ ) And seventh MOS transistor (M) ₇ ) And the eighth MOS transistor (M) ₈ ) Grid electrode connected, sixth MOS transistor (M) ₆ ) The drain electrode of the transistor is connected with the fourth MOS transistor (M4) and the fifth MOS transistor (M) ₅ ) Is connected with the source electrode of the sixth MOS transistor (M) ₆ ) Seventeenth MOS transistor (M) ₁₇ ) Eighteenth MOS transistor (M) ₁₈ ) A gate and a seventh switch (S) ₇ ) Connected, a second MOS transistor (M) ₂ ) Seventeenth MOS transistor (M) ₁₇ ) Twenty-third MOS tube (M) ₂₃ ) Drain and fifteenth MOS transistor (M) ₁₅ ) Source electrode connected to the third MOS transistor (M) ₃₇ ) Eighteenth MOS transistor (M) ₁₈ ) Twenty-fourth MOS transistor (M) ₂₄ ) Drain and sixteenth MOS transistor (M) ₁₆ ) Source electrode connected, fourth MOS transistor (M) ₄ ) And seventh MOS transistor (M) ₇ ) Drain and ninth MOS transistor (M) ₉ ) Source electrode connected to the fifth MOS transistor (M) ₅ ) And the eighth MOS transistor (M) ₈ ) Drain and tenth MOS transistor (M) ₁₀ ) Source electrode connected to the ninth MOS transistor (M) ₉ ) The tenth MOS transistor (M) ₁₀ ) Gate connected, fifteenth MOS transistor (M) ₁₅ ) Sixteenth MOS transistor (M) ₁₆ ) Grid electrode connected, ninth MOS tube (M) ₉ ) Drain electrode of (1), thirteenth MOS transistor (M) ₁₃ ) Drain electrode of (1), eleventh MOS transistor (M) ₁₁ ) Source electrode of (1), twenty-first MOS transistor (M) ₂₁ ) And a third compensation capacitor (C) _c3 ) Is connected with the upper polar plate of the tenth MOS tube (M) ₁₀ ) Drain electrode of (1), fourteenth MOS tube (M) ₁₄ ) Drain electrode of (1), twelfth MOS tube (M) ₁₂ ) Source electrode of (1), nineteenth MOS tube (M) ₁₉ ) And a first compensation capacitor (C) _c1 ) Is connected with the upper polar plate of the fifth MOS transistor (M) ₁₅ ) Drain electrode of (1), eleventh MOS transistor (M) ₁₁ ) Drain electrode of (1), thirteenth MOS transistor (M) ₁₃ ) Source electrode of (1), twenty-second MOS tube (M) ₂₂ ) And a fourth compensation capacitor (C) _c4 ) Connected with the upper electrode plate of the sixteenth MOS transistor (M) ₁₆ ) Drain electrode of (1), twelfth MOS tube (M) ₁₂ ) Drain electrode of (1), fourteenth MOS tube (M) ₁₄ ) Source electrode of (1), twentieth MOS tube (M) ₂₀ ) And a second compensation capacitor (C) _c2 ) Is connected with the upper electrode plate of the eleventh MOS tube (M) ₁₁ ) Twelfth MOS transistor (M) ₁₂ ) Grid electrode connected, thirteenth MOS tube (M) ₁₃ ) Fourteenth MOS transistor (M) ₁₄ ) Grid electrode connected, nineteenth MOS tube (M) ₁₉ ) Twentieth MOS transistor (M) ₂₀ ) Drain electrode and first compensation resistor (R) _c1 ) Connected, twenty-first MOS transistor (M) ₂₁ ) Twenty-second MOS transistor (M) ₂₂ ) Drain and second compensation resistor (R) _c2 ) Connected to a first compensation capacitor (C) _c1 ) Lower pole plate, second compensation capacitor (C) _c2 ) Lower plate and first compensation resistor (R) _c1 ) A first capacitor (C) ₁ ) Lower polar plate, third switch (S) ₃ ) Connected to a third compensation capacitor (C) _c3 ) Lower pole plate, fourth compensation capacitor (C) _c4 ) Lower pole plate and second compensation resistor (R) _c2 ) A second capacitor (C) ₂ ) Lower pole plate, fifth switch (S) ₅ ) Connected twenty-third MOS transistor (M) ₂₃ ) Grid and twenty-fourth MOS tube (M) ₂₄ ) A gate, a first capacitor (C) ₁ ) Upper polar plate, second capacitor (C) ₂ ) Upper pole plate, fourth switch (S) ₄ ) Connected, third switch (S) ₃ ) And a sixth switch (S) ₆ ) A third capacitor (C) ₃ ) The lower pole plate is connected with a fifth switch (S) ₅ ) The eighth switch (S) ₈ ) A fourth capacitor (C) ₄ ) Lower plate connected to a third capacitor (C) ₃ ) Upper polar plate, fourth capacitor (C) ₄ ) Upper pole plate, fourth switch (S) ₄ ) A seventh switch (S) ₇ ) Connected, a sixth switch (S) ₆ ) And an eighth switch (S) ₈ ) Connected to a first resistor (R) ₁ ) And a first MOS transistor (M) ₁ ) Source electrode connected to a second resistor (R) ₂ ) And a sixth MOS transistor (M) ₆ ) Source connected to a third resistor (R) ₃ ) And a seventh MOS transistor (M) ₇ ) Source connected, fourth resistor R4 andeighth MOS transistor (M) ₈ ) Source connected, fifth resistor (R) ₅ ) And a seventeenth MOS transistor (M) ₁₇ ) Source connected, sixth resistor (R) ₆ ) And eighteenth MOS transistor (M) ₁₈ ) Source connected, seventh resistor (R) ₇ ) And a twenty-third MOS transistor (M) ₂₃ ) Source connected, eighth resistor (R) ₈ ) And a twenty-fourth MOS transistor (M) ₂₄ ) The sources are connected.

3. The sense amplifier circuit for acquisition of multiple physiological electrical signals according to claim 1, wherein the first DC servo loop (DSL1) and the second DC servo loop (DSL2) are identical in function and structure, and adopt a switched capacitor structure;

the first direct current servo loop (DSL) ₁ ) And a second direct current servo loop (DSL) ₂ ) All comprise a ninth switch (S) ₉ ) And a tenth switch (S) ₁₀ ) And an eleventh switch (S) ₁₁ ) And a twelfth switch (S) ₁₂ ) And a thirteenth switch (S) ₁₃ ) And a fourteenth switch (S) ₁₄ ) The fifteenth switch (S) ₁₅ ) A fifth capacitor (C) ₅ ) A sixth capacitor (C) ₆ ) A seventh capacitor (C) ₇ ) An eighth capacitor (C) ₈ ) A ninth capacitor (C) ₉ ) A tenth capacitor (C) ₁₀ ) And a fourth transconductance amplifier (G) _m4 )；

The fifth capacitor C5 and the sixth capacitor C6 are integrator input capacitors, and have equal capacitance values, the ninth capacitor C9 and the tenth capacitor C10 are integration capacitors, and the ninth capacitor C9 and the tenth capacitor C10 have equal capacitance values and are much larger than the capacitance values of the fifth capacitor C5 and the sixth capacitor C6, so that a very low high-pass cut-off frequency can be generated.

4. The sense amplifier circuit for multiple physiological electrical signal acquisition as claimed in claim 1, wherein the clock generator comprises: the circuit comprises a trigger (D), a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, a first NOT gate N1, a second NOT gate N2, a third NOT gate N3, state control logic AND a 4-bit counter; the state control logic sets a four-bit control word, the output of the four-bit control word is connected with a first AND gate together with a reset signal RST, the output signal of the first AND gate AND1 is connected with the reset signal bit of a D flip-flop, the D bit of the D flip-flop is connected with a high level VDD, a trigger bit CLK is connected with a clock signal CLK, an output signal Q is connected with the input ends of a second AND gate N2 AND a third AND gate N3, the output end of the second AND gate 2 is connected with the input end of a first NOT gate N1, the output end of the first NOT gate N1 is connected with the input end of a second NOT gate N2, the output end of the second NOT gate N2 is connected with the input end of a third NOT gate N3, the output end of a third NOT gate N3 is connected with the input ends of the second AND gate 2 AND a third AND gate 3, therefore, the second AND gate, the first NOT gate, the second NOT gate AND the third NOT gate form a ring oscillator, a us-stage oscillation signal is generated, the output signal of the third NOT gate is connected with the 4bit counter, AND the output end of the state control logic is connected with the input end of the state control logic, adjusting the output counting times by setting state control logic, and determining an ultra-low duty cycle clock signal with high level time as a plurality of oscillation clocks; the adjusting interval is 16 steps, namely the counting interval of a 4-bit counter.

5. The sense amplifier circuit for acquisition of multiple physiological electrical signals according to any one of claims 1 to 4,

the chopper modulation capacitance coupling instrument amplifier also comprises: first Chopper (CH) ₁ ) A second Chopper (CH) ₂ ) A third Chopper (CH) ₃ ) The fourth Chopper (CH) ₄ ) And a fifth Chopper (CH) ₅ ) A first input capacitor (C) _in1 ) A second input capacitor (C) _in2 ) A first feedback capacitor (C) _fb1 ) A second feedback capacitor (C) _fb2 ) A first DC servo loop capacitor (C) _DSL1 ) A second DC servo loop capacitor (C) _DSL2 ) A first adjustable capacitor (C) _pf1 ) A second adjustable capacitor (C) _pf2 ) A first DC bias resistor (R) _b1 ) And a second direct current resistance (R) _b2 )；

The gain programmable amplifier further comprises: third input capacitance (C) _in3 ) And a fourth input capacitor (C) _in4 ) A third feedback capacitor (C) _fb3 ) A fourth feedback capacitor (C) _fb4 ) A third DC servo loop capacitor (C) _DSL3 ) And a fourth DC servo loop capacitor (C) _DSL4 ) A third DC bias resistor (R) _b3 ) And a fourth DC bias resistor (R) _b4 )；

The band-pass filter with adjustable bandwidth further comprises: fifth input capacitance (C) _in5 ) A sixth input capacitor (C) _in6 ) A fifth feedback capacitor (C) _fb5 ) A sixth feedback capacitor (C) _fb6 ) A first feedback resistor (R) _fb1 ) A second feedback resistor (R) _fb2 ) 1 bit adjustable bias current (I) _bias < 1: 0 >), a first switch (S) ₁ ) And a second switch (S) ₂ )；

The first Chopper (CH) ₁ ) A first input terminal is connected to the signal input terminal Vip, and the first Chopper (CH) ₁ ) A second input terminal connected to the signal input terminal Vin, the first Chopper (CH) ₁ ) The first output terminal and the first input capacitor (C) are connected to the first output terminal and the second output terminal respectively _in1 ) Lower pole plate and second adjustable capacitor (C) _pf2 ) An upper pole plate is connected, the first Chopper (CH) ₁ ) The second output terminal is connected to the second input capacitor (C) _in2 ) Lower pole plate, first adjustable capacitor (C) _pf1 ) Upper plate connected to the first input capacitor (C) _in1 ) The upper polar plate is respectively connected with a first direct current bias resistor (R) _b1 ) A first transconductance amplifier (G) _m1 ) Positive input electrode, second feedback capacitor (C) _fb2 ) The upper polar plate is connected with the first input end of the fourth chopper, and the second input capacitor (C) _ia2 ) The upper polar plate is respectively connected with a second direct current bias resistor (R) _b2 ) A first transconductance amplifier (G) _m1 ) Negative input electrode, first feedback capacitance (C) _fb1 ) The upper pole plate is connected with the second input end of the fourth chopper, and the second Chopper (CH) ₂ ) Input terminal and first transconductance amplifier (G) _m1 ) A positive and a negative output pole, and the second Chopper (CH) ₂ ) Output terminal and third Chopper (CH) ₃ ) Output terminal, fifth Chopper (CH) ₅ ) Output, first direct current servo loop (DSL) ₁ ) Positive and negative output terminals, and a third input capacitor (C) _in3 ) Upper polar plate, fourth input capacitance (C) _in4 ) The upper polar plate is connected; the fourth Chopper (CH) ₄ ) Output terminal and first DC servo loop capacitance (C) _DSL1 ) Upper polar plate, second DC servo loop capacitance (C) _DSL2 ) Upper polar plate connected, the first direct current servo loop (DSL) ₁ ) Positive and negative input terminal and first DC servo loop capacitance (C) _DSL1 ) Lower polar plate, second DC servo loop capacitance (C) _DSL2 ) The lower pole plate is connected, and the third Chopper (CH) ₃ ) Input terminal and first feedback capacitor (C) _fb1 ) Lower plate, second feedback capacitor (C) _fb2 ) The lower pole plate is connected, and the fifth Chopper (CH) ₅ ) Input terminal and first tunable capacitor (C) _pf1 ) Lower pole plate and second adjustable capacitor (C) _pf2 ) A lower polar plate;

the third input capacitance (G) _in3 ) Upper polar plate, third DC bias resistance (R) _b3 ) A fourth feedback capacitor (C) _fb4 ) Upper polar plate, fourth DC servo loop capacitance (C) _DSL4 ) Upper polar plate connected, and fourth input capacitor (C) _in4 ) Upper polar plate, fourth DC bias resistance (R) _b4 ) A third feedback capacitor (C) _fb3 ) Upper polar plate, third DC servo loop capacitance (C) _DSL3 ) Upper pole plate connected, and the second direct current servo loop (DSL) ₂ ) Positive and negative input terminals and a third DC servo loop capacitor (C) _DSL3 ) Lower polar plate, fourth DC servo loop capacitance (C) _DSL4 ) Lower plate connected to each other, the third feedback capacitor (C) _fb3 ) Lower plate, second DC Servo Loop (DSL) ₂ ) A positive output terminal, a second transconductance amplifier (G) _m2 ) Positive output terminal, sixth input capacitance (C) _in6 ) Lower plate connected, the fourth feedback capacitor (C) _fb4 ) Bottom plate, second direct current servo loop (DSL) ₂ ) Negative output terminal, second transconductance amplifier (G) _m2 ) Negative output terminal, fifth input capacitance (C) _in5 ) Connecting the lower polar plates;

the fifth input capacitance (C) _in5 ) Upper plate, third transconductance amplifier (G) _m3 ) Positive input end, first feedback resistance (R) _fb1 ) A fifth feedback capacitor (C) _fb5 ) Upper polar plate connected with the sixth input capacitor (C) _in6 ) Upper plate, third transconductance amplifier (G) _m3 ) Negative input terminal, second feedback resistor (R) _fb2 ) A sixth feedback capacitor (C) _fb6 ) Upper polar plate connected, the first feedback resistor (R) _fb1 ) And a first switch (S) ₁ ) Connected, a second feedback resistor (R) _fb2 ) And a second switch (S) ₂ ) Connected, the fifth feedback capacitance (C) _fb5 ) Lower pole plate and first switch (S) ₁ ) Connected, the sixth feedback capacitance (C) _fb6 ) And a second switch (S) ₂ ) And a third transconductance amplifier (G) _m3 ) The output ends are connected.