CN114999555B - Fuse fault repair circuit - Google Patents
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- CN114999555B CN114999555B CN202110224959.3A CN202110224959A CN114999555B CN 114999555 B CN114999555 B CN 114999555B CN 202110224959 A CN202110224959 A CN 202110224959A CN 114999555 B CN114999555 B CN 114999555B
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- 230000015654 memory Effects 0.000 claims abstract description 118
- 238000001514 detection method Methods 0.000 claims description 28
- 238000012545 processing Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 abstract description 24
- 238000000034 method Methods 0.000 description 7
- 230000002950 deficient Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000002699 waste material Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 238000012544 monitoring process Methods 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
- G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy
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Abstract
The application provides a fuse fault repair circuit which comprises a fuse array, a signal storage module and a scanning repair module. The fuse array includes a redundancy fuse array and a non-redundancy fuse array, the redundancy fuse array has no signal output when the fuse array has no fault, and the non-redundancy fuse array outputs S first logic signals. Each memory cell in the signal memory module is used for storing a first logic signal sent by a connected fuse unit. The scanning repair module is used for scanning the storage units in the signal storage module, determining that a first fuse unit connected with the fault storage unit fails when the fault storage unit is scanned, and replacing the first fuse unit with a first redundant fuse unit corresponding to the first fuse unit. The first redundancy fuse unit belongs to a redundancy fuse array, and a first logic signal corresponding to the first redundancy fuse unit is a normal signal. The application can repair the failed fuse array to improve the utilization rate of the electronic fuse semiconductor memory.
Description
Technical Field
The present application relates to semiconductor integrated circuit technology, and more particularly, to a fuse fault repair circuit.
Background
One time programmable (One Time Programmable, OTP) is a memory type in semiconductor memories, electronic fuses are one type of OTP, which in turn may be Anti-fuses, for example. In the use of semiconductor memories, electronic fuses have been widely used, particularly in cases of trimming circuit parameters of semiconductor memories, repairing certain manufacturing problems of semiconductor memories, and the like. Compared with other memory technologies, the electronic fuse memory is read operation which cannot be customized, namely, the read sequence of the electronic fuse memory is fixed after the design is completed.
The manufacture and use of electronic fuses are easily affected by the process, but with the development of semiconductor processes, the semiconductor memory is required to be continuously reduced in size, and the failure rate of the electronic fuses is continuously improved. If the electronic fuse fails, the semiconductor memory including the electronic fuse is also unusable due to the failure, resulting in significant waste.
Therefore, how to ensure that the semiconductor memory can still be used when the electronic fuse fails is a problem to be solved.
Disclosure of Invention
The application provides a fuse fault repair circuit which is used for solving the problem of how to ensure that a semiconductor memory can still be used when an electronic fuse breaks down.
In one aspect, the present application provides a fuse fault repair circuit comprising:
The input end of the fuse array is used for being connected with a power supply end, the output end of the fuse array is used for outputting S first logic signals, the fuse array comprises M fuse units, each fuse unit correspondingly outputs one first logic signal, S and M are integers larger than zero, and S is smaller than M; the M fuse units comprise a redundant fuse array and a non-redundant fuse array, wherein when the fuse array fails, the redundant fuse array outputs no signal, and the non-redundant fuse array outputs S first logic signals;
The signal storage module comprises at least M storage units, wherein each storage unit is used for storing a first logic signal sent by a connected fuse unit;
The scanning repair module is in signal connection with the signal storage module and is used for scanning the storage units in the signal storage module, determining that a first fuse unit connected with the fault storage unit fails when the fault storage unit is scanned, replacing the first fuse unit with a first redundant fuse unit corresponding to the first fuse unit, wherein a first logic signal stored in the fault storage unit is a fault signal, the first redundant fuse unit belongs to the redundant fuse array, and the first logic signal corresponding to the first redundant fuse unit is a normal signal.
In one embodiment, the memory unit has a status flag, where the status flag is used to flag the first logic signal stored in the memory unit as a normal signal or a fault signal;
The scanning repair module is specifically configured to scan a status flag of a storage unit in the signal storage module, and determine whether the storage unit is the faulty storage unit according to the status flag of the storage unit.
In one embodiment, the at least M memory cells include redundant memory cells and non-redundant memory cells;
the signal storage module further comprises a signal detection circuit, wherein the input end of the signal detection circuit is connected with the output end of the fuse array, and the output end of the signal detection circuit is connected with the at least M storage units;
When the first logic signal is a redundant signal, storing the first logic signal into the redundant storage unit;
and when the first logic signal is a non-redundant signal, storing the first logic signal into the non-redundant storage unit.
In one embodiment, the method further comprises:
The redundant signal detection unit is connected with the output end of the redundant storage unit;
when the redundant memory cell stores a signal, the redundant signal detection unit outputs a fault repair signal.
In one embodiment, the fuse array is formed by arranging N1 rows and L1 columns of fuse units, and the at least M memory units form a memory array of N2 rows and L2 columns, where N2 is greater than or equal to N1, and L2 is greater than or equal to L1;
each row of memory cells is used for storing a first logic signal output by one row of fuse cells in the fuse array.
In one embodiment, the first memory cell in the signal memory module is further configured to receive a clock driving pulse;
When the clock driving pulse is a first pulse, the first storage unit cuts off signal storage of adjacent storage units in the same row, the storage units in the same row store data according to the sequence, and the adjacent storage units are next units to store signals.
In one embodiment, after determining the row and the column where the first fuse unit is located, the scan repair module determines the row and the column where the first redundancy fuse unit is located according to the row and the column where the first fuse unit is located, where the column where the first fuse unit is located and the column where the first redundancy fuse unit is located are symmetrical columns, and the row where the first fuse unit is located and the row where the first redundancy fuse unit is located are the same, where the symmetrical columns represent that the sum of the columns of any two columns is equal to the sum of the columns of any two other columns.
In one embodiment, each of the first logic signals carries an address code, and each of the memory cells is provided with an address code;
And when the signal storage module detects that the address code carried by the first logic signal is matched with the address code of the storage unit, the first logic signal is stored in the storage unit.
In one embodiment, the fuse unit includes:
One end of the fuse wire is used for connecting the power supply end;
The source electrode of the transistor is connected with the output end of the fuse, the drain electrode of the transistor is connected with the input end of the signal storage module, and the grid electrode of the transistor is used for receiving the address code corresponding to the fuse unit;
The transistor is used for receiving the output signal of the fuse, combining the output signal of the fuse with the address code corresponding to the fuse unit and then outputting the first logic signal.
In one embodiment, the method further comprises:
The input end of the inverter is connected with the drain electrode of the transistor, the output end of the inverter is connected with the signal storage module, and the inverter is used for carrying out signal processing on the first logic signal and then inputting the first logic signal into the signal storage module.
In one embodiment, the scan repair module is further configured to receive a scan code, and scan the storage unit according to the scan code;
wherein the scan code includes an address code of a memory cell.
In another aspect, the present application provides an electrical fuse memory comprising the fuse fault repair circuit according to the first aspect.
The fuse fault repair circuit provided by the application comprises a fuse array, a signal storage module and a scanning repair module, wherein the signal storage module is used for processing and storing logic signals correspondingly output by each fuse unit in the fuse array, the scanning repair module can scan the storage units in the signal storage module, and when the scanning repair module scans the fault storage unit, a first fuse unit corresponding to the fault storage unit is determined, wherein the first logic signals stored in the fault storage unit are fault signals. Further, the scan repair module replaces a first fuse cell in the non-redundant fuse array with a first redundant fuse cell in the redundant fuse array, or replaces an output of the first fuse cell with an output of the first redundant fuse cell in the redundant fuse array. It should be noted that, the non-redundant fuse array refers to a fuse array that is used when the memory in which the fuse array is located has no fault, and the redundant fuse array refers to a fuse array that is not used when the memory in which the fuse array is located has no fault. The fuse fault repair circuit provided by the application utilizes the normal fuses in the redundant fuse array to replace the fuse units with faults in the non-redundant fuse array, so that the normal fuse array can be used even if the memory with the fuse array is in fault, thereby ensuring that the semiconductor memory can still be used when the electronic fuse is in fault, and solving the problem of great waste of the semiconductor memory caused by the fault of the electronic fuse in the prior art.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.
FIG. 1 is a schematic diagram of a fuse fail-over circuit according to some embodiments of the present application;
FIG. 2 is a schematic diagram of a fuse fail-over circuit according to other embodiments of the present application;
FIG. 3 is a schematic diagram of a signal storage module according to some embodiments of the present application;
fig. 4 is a schematic diagram of an electrical fuse memory according to some embodiments of the application.
Reference numerals illustrate:
fuse fault repair circuit 10
Fuse array 100
Fuse unit 110
Fuse 111
Transistor 112
Inverter 113
Redundant fuse array 120
Non-redundant fuse array 130
First fuse unit 140
First redundancy fuse unit 150
Signal storage module 200
Memory cell 210
Failure storage unit 211
Redundant memory cell 220
Non-redundant memory cell 230
Signal detection circuit 240
Scan repair module 300
Scan logic 310
Repair logic 320
Redundant signal detection unit 400
Electrical fuse memory 20
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present disclosure as detailed in the accompanying claims.
One time programmable (One Time Programmable, OTP) is a memory type in semiconductor memories, electronic fuses are one type of OTP, and electronic fuses may be Anti-fuses, for example. With the development of semiconductor processes, the semiconductor memory is required to be reduced in size, but the fabrication and use of electronic fuses are easily affected by the processes. The smaller the volume of the semiconductor memory, the higher the failure rate of the electronic fuse. If the electronic fuse fails, the semiconductor memory including the electronic fuse is not used due to the failure, which causes great waste.
An electronic fuse-like semiconductor memory includes an antifuse array, which in turn includes a non-redundant fuse array and a redundant fuse array. When the electronic fuse semiconductor memory is used without faults, the redundant fuse array is in a standby state and is not used, and the non-redundant fuse array is in a use state, if the non-redundant fuse array breaks down, the electronic fuse semiconductor memory is directly caused to break down and is discarded.
Accordingly, the present application provides a fuse fault repair circuit 10, where the fuse fault repair circuit 10 can scan out a faulty fuse cell in a non-redundant fuse array in an anti-fuse array, and replace the faulty fuse cell with a fuse cell in a redundant fuse array. Therefore, the repair of the non-redundant fuse array is realized, and the condition that the whole semiconductor memory is abandoned because of the fault of the non-redundant fuse array is avoided.
The structure and operation principle of the fuse fault repair circuit 10 provided by the present application are explained in detail below.
Referring to fig. 1, the fuse fault repair circuit 10 provided in the present embodiment includes a fuse array 100, a signal storage module 200 and a scan repair module 300.
The input terminal of the fuse array 100 is used for being connected with a power supply terminal, and the output terminal of the fuse array 100 is used for outputting S first logic signals. The fuse array 100 includes M fuse units 110, each fuse unit 110 correspondingly outputs one of the first logic signals, S and M are integers greater than zero, and S is less than M. The M fuse units 110 include a redundancy fuse array 120 and a non-redundancy fuse array 130, the redundancy fuse array 120 has no signal output when the fuse array 100 has no fault, and the non-redundancy fuse array 130 outputs S first logic signals.
As shown in fig. 2, the fuse array 100 is schematically shown when the value of M is 256, and in fig. 2, 256 fuse units 100 are arranged in 16 rows and 16 columns. Each fuse cell 110 is marked with fn_m in fig. 2, where n is a number of columns, m is a number of rows, for example f0_0 represents the fuse cell 100 of column 1, f0_15 represents the fuse cell 100 of column 1, row 16, f15_0 represents the fuse cell 100 of column 16, row 1, f15_15 represents the fuse cell 100 of column 16, row 16.
As shown in fig. 2, assume that the non-redundant fuse array 130 of the 256 fuse cells 100 occupies 16 rows and 8 columns of the fuse cells 110, and the fuse cells corresponding to the non-redundant fuse array 130 are identified as f0_0、f0_1、f0_2……f0_15,f1_0、f1_1、f1_2……f1_15,f2_0、f2_1、f2_2……f2_15,f3_0、f3_1、f3_2……f3_15,f4_0、f4_1、f4_2……f4_15,f5_0、f5_1、f5_2……f5_15,f6_0、f6_1、f6_2……f6_15,f7_0、f7_1、f7_2……f7_15.
Correspondingly, the redundant fuse array 120 of the 256 fuse units 100 occupies the remaining 16 rows and 8 columns of fuse units 110, and the fuse units corresponding to the redundant fuse array 120 are identified as f8_0、f8_1、f8_2……f8_15,f9_0、f9_1、f9_2……f9_15,f10_0、f10_1、f10_2……f10_15,f11_0、f11_1、f11_2……f11_15,f12_0、f12_1、f12_2……f12_15,f13_0、f13_1、f13_2……f13_15,f14_0、f14_1、f14_2……f14_15,f15_0、f15_1、f15_2……f15_15.
The signal storage module 200 includes at least M memory cells 210, each memory cell 210 for storing a first logic signal transmitted from one of the connected fuse cells 110. When the fuse array 100 sends out S first logic signals, the signal storage module 200 correspondingly stores the S first logic signals.
In some embodiments, the fuse array 100 is comprised of an N1 row L1 column arrangement of fuse cells 110, and the at least M memory cells 210 form an N2 row L2 column memory array. Wherein, N1, L1, N2 and L2 are integers greater than zero, N2 is greater than or equal to N1, and L2 is greater than or equal to L1. Each row of the memory cells 210 is used to store the first logic signal output by one row of the fuse cells 110 in the fuse array when the first logic signal output by the fuse array 100 is stored.
Specifically, referring to fig. 2, each row of the memory cells 210 receives a corresponding clock sequence broadcast < m >, and sequentially propagates the received first logic signals backward based on the clock sequence broadcast < m >, where m is a flag indicating the row number. A schematic memory diagram when the fuse cells 110 of the 1 st and 16 th rows in the non-redundant fuse array output the first logic signal is shown in fig. 1. In fig. 1, when the first logic signal output from the fuse unit 110 of the 1 st row is stored in the 1 st row of the memory unit 210, the 1 st row of the memory unit 210 receives a clock sequence broadcast <0>, and sequentially propagates the received first logic signal backward based on the broadcast <0 >. When the first logic signal outputted from the fuse unit 110 of the 16 th row is stored in the 16 th row of the memory unit 210, the 16 th row of the memory unit 210 receives the clock sequence broadcast <15>, and sequentially propagates the received first logic signal backward based on the broadcast <15 >.
Further, when each row of the memory units 210 receives the corresponding clock sequence broadcast < m >, and propagates and stores the first logic signals based on the clock sequence broadcast < m >, the corresponding storage is further required according to the address code carried by each first logic signal. Specifically, each of the first logic signals carries an address code, each of the memory units 210 is provided with an address code, and when the signal storage module 200 detects that the address code carried by the first logic signal matches the address code of the memory unit 210, the first logic signal is stored in the memory unit 210.
As shown in FIG. 1, each column of the fuse cells 110 has a corresponding address code WL < n >, where n is a number of columns of indicia. The address of the fuse cell 110 in column 1 is encoded as WL <0>, the address of the fuse cell 110 in column 2 is encoded as WL <1>, and so on. While WL < n > is specifically a four-digit code (not specifically shown in FIG. 1, the identification of WL < n > in FIG. 1 is merely for the sake of brevity to illustrate that each fuse cell 110 has a corresponding address code), i.e., each fuse cell 110 has a corresponding address code WL < n >. Correspondingly, as shown in FIG. 1, each memory cell 210 has a corresponding address code WL [3:0], wherein the address code WL [3:0] is a four-bit number code, and the address codes WL [3:0] are in one-to-one correspondence with WL < n >. For example, the address code WL [3:0] represents the first logic signal output by the fuse cell 110 identified as f0_0 when WL [0000] and the address code WL [3:0] represents the first logic signal output by the fuse cell 110 identified as f7_0 when WL [0111 ].
Optionally, the fuse unit 110 includes a fuse 111, a transistor 112, and an inverter 113. One end of the fuse 111 is used for being connected to the power supply end (VANT shown in fig. 1), the source of the transistor 112 is connected to the output end of the fuse 111, the drain of the transistor 112 is connected to the input end of the signal storage module 200, and the gate of the transistor 112 is used for receiving the address code corresponding to the fuse unit 110. The transistor 112 is configured to receive the output signal of the fuse 111, combine the output signal of the fuse 111 with the address code corresponding to the fuse unit 110, and output the first logic signal. Therefore, the signal storage module 200 can determine the address code of the corresponding fuse unit 110 according to the first logic signal, and store the first logic signal output by the fuse unit 110 according to the address code matching result of the memory unit 210 and the fuse unit 110. An input end of the inverter 113 is connected to the drain of the transistor 112, an output end of the inverter 113 is connected to the signal storage module 200, and the inverter 113 is used for performing signal processing on the first logic signal and inputting the first logic signal to the signal storage module 200. That is, the signal output by the transistor 112 is subjected to signal inversion processing by the inverter 113 to generate the first logic signal, and the first logic signal is stored by the signal storage module 200.
The scan repair module 300 is in signal connection with the signal storage module 200. After the signal storage module 200 stores the S first logic signals output by the fuse array 100, the scan repair module 300 is configured to scan the storage units 210 in the signal storage module 200, and determine that the first fuse units 140 connected to the faulty storage unit 211 fail when the faulty storage unit 211 is scanned. Wherein the first logic signal stored in the fault storage unit 211 is a fault signal. The fault signal has an identifier such as 0 or 1, and, taking the identifier of the fault signal as 1 as an example, when the scan repair module 300 detects that the first logic signal in a certain storage unit 210 has an identifier of 1, it determines that the certain storage unit 210 is the faulty storage unit 211.
Alternatively, as shown in fig. 2, the memory cell 210 has a status flag rn_m, where n represents the identification of a column and m represents the identification of a row, and the status flag is used to flag the first logic signal stored in the memory cell as a normal signal or a fault signal. The scan repair module 200 is specifically configured to scan the status flag of the memory cell 210 in the signal memory module 200, and determine whether the memory cell is the faulty memory cell 211 according to the status flag of the memory cell 210. Assuming that the state flag of the memory cell 210 is "0" for normal, that is, rn_m=0 for normal, and the state flag of the memory cell 210 is "1" for failure, that is, rn_m=1 for failure, when the scan repair module 300 scans that the state flag of a certain memory cell 210 is "1", that is, rn_m=1, it is determined that the certain memory cell 210 is the failed memory cell 211.
Optionally, the scan repair module 300 is further configured to receive a scan code, and scan the storage unit 210 according to the scan code, where the scan code includes an address code of the storage unit 210. That is, the scan repair module 300 does not need to scan all the memory cells 210 in the signal memory module 200, but only needs to scan the corresponding memory cells 210 according to the scan code, thus reducing the workload of the scan repair module 300.
When the scan repair module 300 determines the defective memory cell 211, the scan repair module 300 replaces the first fuse cell 140 corresponding to the defective memory cell 211 with the first redundant fuse cell 150 corresponding to the first fuse cell 140. The first redundancy fuse unit 150 belongs to the redundancy fuse array, and the first logic signal corresponding to the first redundancy fuse unit 150 is a normal signal. That is, after the scan repair module 300 determines the defective memory cell 211, the defective fuse cell in the non-redundant fuse array 130 is replaced with any one or a specific fuse cell in the redundant fuse array 120 in the fuse array 100, thereby completing the repair of the non-redundant fuse array 130 of the fuse array 100.
Optionally, the scan repair module 300 includes scan logic 310 and repair logic 320, where the scan logic 310 is configured to scan the memory cells 210 in the signal memory module 200, determine that the memory cells 210 containing the fault signal are the faulty memory cells 211 when the scan logic 310 scans for the fault signal, and send a repair signal to the repair logic 320. After receiving the repair signal, the repair logic 320 determines the first redundancy fuse unit 150 corresponding to the first fuse unit 140 from the redundancy fuse array, and shifts the first redundancy fuse unit 150 to the position of the first fuse unit 140, thereby completing the repair of the redundancy fuse array. Wherein the repair logic 320 may set an indication to determine where the first fuse unit 140 is based on the repair signal issued by the scan logic 310.
Optionally, the scan repair module 300 determines the row and column in which the first redundancy fuse unit 150 is located according to the row and column in which the first fuse unit 140 is located after determining the row and column in which the first fuse unit 140 is located. The row where the first fuse unit 140 is located and the row where the first redundancy fuse unit 150 is located are symmetrical rows, and the row where the first fuse unit 140 is located and the row where the first redundancy fuse unit 150 is located are the same. For example, as shown in fig. 1, if the identifier of the first fuse unit 140 is f0—0, that is, the column number of the first fuse unit 140 is 1, the identifier of the first redundancy fuse unit 150 is f15—0, and at this time, the column number of the first redundancy fuse unit 150 is 16. If the first fuse unit 140 is identified as f2_0, i.e. the column number of the first fuse unit 140 is 3, the first redundant fuse unit 150 is identified as f13_0, and the column number of the first redundant fuse unit 150 is 14. If the first fuse unit 140 is identified as f3_1, i.e. the column number of the first fuse unit 140 is 4, the first redundant fuse unit 150 is identified as f12_0, and the column number of the first redundant fuse unit 150 is 13.
In summary, the fuse fault repair circuit 10 provided in this embodiment uses the scan repair module 300 to scan the memory cells 210 in the signal memory module 200, and replaces the first fuse unit 140 with the first redundant fuse unit 150 corresponding to the first fuse unit 140 when the defective memory cell 211 is scanned, thereby completing repair of the faulty non-redundant fuse array 130. Therefore, the fuse fault repair circuit 10 provided in this embodiment can ensure that the semiconductor memory can still be used normally when the electronic fuse fails, and avoid a great deal of waste of the electronic fuse semiconductor memory.
As shown in fig. 2 and 3, in some embodiments, the M memory cells 210 include a redundant memory cell 220 and a non-redundant memory cell 230. The signal storage module 200 further includes a signal detection circuit 240, an input terminal of the signal detection circuit 240 is connected to an output terminal of the fuse array 100, and an output terminal of the signal detection circuit 240 is connected to at least M storage units 210. When the signal detection circuit 240 detects that the first logic signal is a redundancy signal, the signal storage module 200 stores the first logic signal into the redundancy storage unit 220. When the signal detection circuit 240 detects that the first logic signal is a non-redundant signal, the signal storage module 200 stores the first logic signal to the non-redundant memory cell 230.
As shown in FIG. 3, the signal detection circuit 240 receives the clock sequences broadcast < m > and WL < n >, where broadcast < m > is used to drive signal propagation and WL < n > is the identity of the first logic signal. Alternatively, when WL < n > =0, it indicates that the first logic signal belongs to a non-redundant signal, the signal storage module 200 stores the first logic signal into the non-redundant memory cell 230. When WL < n > =1, it indicates that the first logic signal belongs to a redundancy signal, the signal storage module 200 stores the first logic signal into the redundancy memory unit 220.
It should be noted that, when the non-redundant fuse array 130 has no fault, the situation that the redundant fuse unit replaces the faulty non-redundant fuse unit does not occur, and the first logic signals output by the fuse array 100 all belong to non-redundant signals. Correspondingly, the signal storage module 200 stores no signal in the redundant memory cell 220 when storing the first logic signal. When the non-redundant fuse array 130 fails, the first redundant fuse unit 150 replaces the first fuse unit 140, and the first logic signal outputted from the fuse array 100 has a logic signal belonging to a redundant signal. Correspondingly, the signal storage module 200 stores signals in the redundant storage unit 220 when storing the first logic signal.
Optionally, the fuse fault repair circuit 10 is correspondingly provided with a redundant signal detection unit 400, and the redundant signal detection unit 400 is connected with the output end of the redundant storage unit 220. When the redundancy memory unit 220 stores a signal, the redundancy signal detecting unit 400 outputs a fail-over signal, and when the redundancy signal detecting unit 400 detects the fail-over signal, it is verified that the non-redundancy fuse array 130 in the fuse array 100 fails and has been replaced by the redundancy fuse array 120.
The fail-over signal is L1 as shown in fig. 3, and the redundant signal detection unit 400 proves that the redundant memory cell 220 stores the first logic signal, i.e., that the non-redundant fuse array 130 fails and has been replaced and repaired by the redundant fuse array 120 as long as l1=1 is detected.
In some embodiments, the first memory cell 210 in the signal storage module 200 is further configured to receive a clock driving pulse, and when the clock driving pulse is the first pulse, the first memory cell 210 truncates the signal storage of the adjacent memory cells 210 in the same row. When the signal storage module 200 stores the first logic signal, the memory cells 210 in the same row store data in sequence, and the adjacent memory cells 210 are the cells to be stored next.
As shown in FIG. 2, the redundant memory cell 220 and the non-redundant memory cell 230 respectively receive driving clocks WL [2:0] & CLK, if the first pulse is set to be other codes except [111], when WL [2:0] is not equal to [111], such as WL [2:0] = [000], the driving clocks WL [2:0] & CLK drive the memory cell 210 to continue to propagate the first logic signal backward, and when WL [2:0] is equal to [111], the memory cell 210 stops to continue to propagate the first logic signal backward.
In summary, in the present embodiment, the signal storage module 200 performs the differential storage of the first logic signal according to the storage forms of the redundant storage unit 220 and the non-redundant storage unit 230, that is, when the first logic signal is output by the non-redundant fuse array 130, the first logic signal is stored into the non-redundant storage unit 230. When the non-redundancy fuse array 130 fails and the redundancy fuse array 120 performs replacement repair, the first logic signal output by the first redundancy fuse unit 150 for replacement repair is stored into the redundancy memory unit 220. The present embodiment is further provided with a redundant signal detection unit 400, and outputs the fail-over signal when the redundant signal detection unit 400 detects that a signal is stored in the redundant storage unit 220. The fail-over signal may be displayed on a user interface whereby a worker knows that the fuse array 100 has completed an automatic repair, facilitating the worker's monitoring of the status of the fuse array.
Referring to fig. 4, an embodiment of the present application provides an electrical fuse memory 20, wherein the electrical fuse memory 20 includes the fuse fault repair circuit 10 according to any of the above embodiments. The electrical fuse memory 20 may also include other configuration elements, and the application is not limited thereto.
Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It is to be understood that the application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.
Claims (13)
1. A fuse fault repair circuit comprising:
The input end of the fuse array is used for being connected with a power supply end, the output end of the fuse array is used for outputting S first logic signals, the fuse array comprises M fuse units, each fuse unit correspondingly outputs one first logic signal, S and M are integers larger than zero, and S is smaller than M; the M fuse units comprise a redundant fuse array and a non-redundant fuse array, wherein when the fuse array fails, the redundant fuse array outputs no signal, and the non-redundant fuse array outputs S first logic signals;
The signal storage module comprises at least M storage units, wherein each storage unit is used for storing a first logic signal sent by a connected fuse unit;
The scanning repair module is in signal connection with the signal storage module and is used for scanning a storage unit in the signal storage module, determining that a first fuse unit connected with the fault storage unit fails when the fault storage unit is scanned, replacing the first fuse unit with a first redundant fuse unit corresponding to the first fuse unit, wherein a first logic signal stored in the fault storage unit is a fault signal, the first redundant fuse unit belongs to the redundant fuse array, and the first logic signal corresponding to the first redundant fuse unit is a normal signal;
The fuse array is formed by arranging N1 rows and L1 columns of fuse units, the at least M memory units form a N2 rows and L2 columns of memory array, N1, L1, N2 and L2 are integers larger than zero, N2 is larger than or equal to N1, and L2 is larger than or equal to L1;
each row of storage units is used for storing a first logic signal output by one row of fuse units in the fuse array respectively;
The first storage unit in the signal storage module is also used for receiving clock driving pulses; when the clock driving pulse is a first pulse, the first storage unit cuts off signal storage of adjacent storage units in the same row, the storage units in the same row store data according to the sequence, and the adjacent storage units are next units to store signals.
2. The fuse fault repair circuit of claim 1, wherein the memory cell has a status flag for marking a first logic signal stored in the memory cell as a normal signal or a fault signal;
The scanning repair module is specifically configured to scan a status flag of a storage unit in the signal storage module, and determine whether the storage unit is the faulty storage unit according to the status flag of the storage unit.
3. The fuse fault repair circuit of claim 1, wherein the at least M memory cells comprise redundant memory cells and non-redundant memory cells;
the signal storage module further comprises a signal detection circuit, wherein the input end of the signal detection circuit is connected with the output end of the fuse array, and the output end of the signal detection circuit is connected with the at least M storage units;
When the first logic signal is a redundant signal, storing the first logic signal into the redundant storage unit;
and when the first logic signal is a non-redundant signal, storing the first logic signal into the non-redundant storage unit.
4. The fuse fail-over circuit of claim 3, further comprising:
The redundant signal detection unit is connected with the output end of the redundant storage unit;
when the redundant memory cell stores a signal, the redundant signal detection unit outputs a fault repair signal.
5. A fuse fault repair circuit comprising:
The input end of the fuse array is used for being connected with a power supply end, the output end of the fuse array is used for outputting S first logic signals, the fuse array comprises M fuse units, each fuse unit correspondingly outputs one first logic signal, S and M are integers larger than zero, and S is smaller than M; the M fuse units comprise a redundant fuse array and a non-redundant fuse array, wherein when the fuse array fails, the redundant fuse array outputs no signal, and the non-redundant fuse array outputs S first logic signals;
The signal storage module comprises at least M storage units, wherein each storage unit is used for storing a first logic signal sent by a connected fuse unit;
The scanning repair module is in signal connection with the signal storage module and is used for scanning a storage unit in the signal storage module, determining that a first fuse unit connected with the fault storage unit fails when the fault storage unit is scanned, replacing the first fuse unit with a first redundant fuse unit corresponding to the first fuse unit, wherein a first logic signal stored in the fault storage unit is a fault signal, the first redundant fuse unit belongs to the redundant fuse array, and the first logic signal corresponding to the first redundant fuse unit is a normal signal;
The fuse array is formed by arranging N1 rows and L1 columns of fuse units, the at least M memory units form a N2 rows and L2 columns of memory array, N1, L1, N2 and L2 are integers larger than zero, N2 is larger than or equal to N1, and L2 is larger than or equal to L1;
each row of storage units is used for storing a first logic signal output by one row of fuse units in the fuse array respectively;
After determining the row and the column where the first fuse unit is located, the scan repair module determines the row and the column where the first redundant fuse unit is located according to the row and the column where the first fuse unit is located, wherein the column where the first fuse unit is located and the column where the first redundant fuse unit is located are symmetrical columns, the row where the first fuse unit is located and the row where the first redundant fuse unit is located are the same, and the symmetrical columns represent that the sum of the columns of any two columns is equal to the sum of the columns of any two other columns.
6. The fuse fail-over circuit of claim 5, wherein the memory cell has a status flag for marking a first logic signal stored in the memory cell as a normal signal or a fail signal;
The scanning repair module is specifically configured to scan a status flag of a storage unit in the signal storage module, and determine whether the storage unit is the faulty storage unit according to the status flag of the storage unit.
7. The fuse fault repair circuit of claim 5, wherein the at least M memory cells comprise redundant memory cells and non-redundant memory cells;
the signal storage module further comprises a signal detection circuit, wherein the input end of the signal detection circuit is connected with the output end of the fuse array, and the output end of the signal detection circuit is connected with the at least M storage units;
When the first logic signal is a redundant signal, storing the first logic signal into the redundant storage unit;
and when the first logic signal is a non-redundant signal, storing the first logic signal into the non-redundant storage unit.
8. The fuse fail-over circuit of claim 7, further comprising:
The redundant signal detection unit is connected with the output end of the redundant storage unit;
when the redundant memory cell stores a signal, the redundant signal detection unit outputs a fault repair signal.
9. The fuse fault repair circuit of any one of claims 1-8, wherein each of said first logic signals carries an address code, each of said memory cells being provided with an address code;
And when the signal storage module detects that the address code carried by the first logic signal is matched with the address code of the storage unit, the first logic signal is stored in the storage unit.
10. The fuse fault repair circuit of claim 9, wherein the fuse unit comprises:
One end of the fuse wire is used for connecting the power supply end;
The source electrode of the transistor is connected with the output end of the fuse, the drain electrode of the transistor is connected with the input end of the signal storage module, and the grid electrode of the transistor is used for receiving the address code corresponding to the fuse unit;
The transistor is used for receiving the output signal of the fuse, combining the output signal of the fuse with the address code corresponding to the fuse unit and then outputting the first logic signal.
11. The fuse fail-over circuit of claim 10, further comprising:
The input end of the inverter is connected with the drain electrode of the transistor, the output end of the inverter is connected with the signal storage module, and the inverter is used for carrying out signal processing on the first logic signal and then inputting the first logic signal into the signal storage module.
12. The fuse fault repair circuit of claim 9, wherein the scan repair module is further configured to receive a scan code and scan a memory cell according to the scan code;
wherein the scan code includes an address code of a memory cell.
13. An electrical fuse memory comprising the fuse fail-over circuit of any one of claims 1-12.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110224959.3A CN114999555B (en) | 2021-03-01 | 2021-03-01 | Fuse fault repair circuit |
| PCT/CN2021/105069 WO2022183649A1 (en) | 2021-03-01 | 2021-07-07 | Fuse fault repair circuit |
| US17/498,083 US11587641B2 (en) | 2021-03-01 | 2021-10-11 | Fuse fault repair circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110224959.3A CN114999555B (en) | 2021-03-01 | 2021-03-01 | Fuse fault repair circuit |
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| CN114999555A CN114999555A (en) | 2022-09-02 |
| CN114999555B true CN114999555B (en) | 2024-05-03 |
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| CN202110224959.3A Active CN114999555B (en) | 2021-03-01 | 2021-03-01 | Fuse fault repair circuit |
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| CN114999555A (en) | 2022-09-02 |
| WO2022183649A1 (en) | 2022-09-09 |
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