CN114978997B - Radio frequency intermediate frequency three-level CLOS non-blocking switching matrix route rapid selection method - Google Patents
Radio frequency intermediate frequency three-level CLOS non-blocking switching matrix route rapid selection method Download PDFInfo
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
- H04L45/745—Address table lookup; Address filtering
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- H—ELECTRICITY
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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Abstract
The invention discloses a radio frequency intermediate frequency three-level CLOS non-blocking switching matrix route rapid selection method, which comprises the following steps: s1, establishing a routing table; s2, establishing a memory table; s3: selecting response port number groups in the routing table according to the output port number; s4, searching in the grouped memory table, if the searching is successful, jumping to the step S6, and if the searching is failed, performing the step S5; s5, determining a search query direction according to the current routing state; s6, controlling the on-off of each switch according to the inquired routing control parameters; s7, updating the memory table. The invention establishes a routing state table and a short-time memory table, uses the current connection state as prior knowledge, adopts a memory search and update method to realize the quick selection of the routing, reduces the average calculation amount of table lookup search to 1/2N, consumes little calculation amount and realizes the quick selection of the switching matrix routing.
Description
Technical Field
The invention relates to the technical field of data communication, in particular to a rapid routing method for a radio frequency intermediate frequency three-level CLOS non-blocking switching matrix.
Background
In satellite earth stations, short-wave and ultrashort-wave communication hubs, radio signal detection stations and radio monitoring stations with larger scale, in order to realize large-scale communication link distribution management and signal detection and control link distribution management, a radio frequency intermediate frequency switching matrix is widely applied to complete distribution and exchange among a transmitting-receiving antenna, a communication terminal, a detection post and a monitoring station, and a routing method is an important basis for developing efficient communication link distribution management and signal receiving link distribution management. Because the radio frequency intermediate frequency switching matrix is used for power distribution and switching of high frequency analog signals, each level of distribution and switching brings insertion loss, low noise amplifiers are needed to be adopted for compensation, and in order to reduce electromagnetic radiation and interference of a calculation control unit to an analog high frequency channel, a simple operation and control device is usually adopted in engineering to complete route selection control except for electromagnetic shielding measures.
In the fields of radio communication, radio detection and radio monitoring, two methods are generally adopted for routing the radio frequency intermediate frequency switching matrix in engineering implementation: firstly, a sequential search algorithm is used for establishing a routing table in all states and obtaining the on-off states of all switches through sequential search; secondly, various parallel routing algorithms proposed by the Graph Edge Coloring (Graph Edge-Coloring) problem in Graph theory are used, and an n-degree binary multiple Graph Edge Coloring method (Edge Coloring of binary Multigraphs of degree n) is usually used. The sequential search algorithm is simple, but the operation amount is large, the cost is high, and a control computer or a routing resolving function is usually required to be added in upper computer software in engineering implementation; and the quantity of control information between the radio frequency intermediate frequency switching matrix and the control computer or the upper computer is large, the transmission timeliness of control instructions is low, and the route switching speed is low. The parallel routing algorithm reduces the operation amount, but the algorithm is still more complex and has higher cost, and a single board computer or a DSP board or an FPGA board with an ARM core needs to be integrated in a switching matrix; and a special electromagnetic shielding design is also needed, so that the electromagnetic compatibility interference caused by high-speed digital signal processing such as a single-board computer or a DSP board or an FPGA board with an ARM core is reduced.
At present, in satellite earth stations, short-wave and ultrashort-wave communication hubs, radio signal detection stations and radio monitoring stations with larger scale, the routing of radio frequency intermediate frequency switching matrix equipment is dynamically controlled according to the change requirements of services, targets and objects, so that the purpose of quickly establishing suitable communication transceiving channels and signal detection and control channels is achievedThe time complexity of the waterline routing algorithm is reduced to
However, for the rf intermediate frequency three-stage CLOS non-blocking switching matrix, it is still relatively complicated to use a low-cost single chip to solve the routing algorithm.
Disclosure of Invention
Aiming at the problems, the invention provides a low-cost and rapid method for realizing the routing selection of the radio frequency intermediate frequency non-blocking switching matrix by utilizing routing prior knowledge and memory search table look-up, short-time memory is simulated, firstly, the memory list is inquired, the table look-up search calculation amount is averagely reduced to 1/2N, and the routing selection and control are completed by a single chip microcomputer.
The invention adopts the following technical scheme: a radio frequency intermediate frequency three-level CLOS non-blocking switching matrix route rapid selection method comprises the following steps:
s1: establishing a routing table: the routing table is grouped according to the output port number, the input port numbers in the group are arranged from small to large, the routing table defines the control parameters of the module switch needed to be configured in the input stage T1, the intermediate stage T2 and the output stage T3, the control parameters of the routing table are arranged according to a matrix, and the routing table control parameter matrix of the C (n, m, r) non-blocking switching matrix is as follows, wherein C (n, m, r) represents the non-blocking switching matrix that the input port number and the output port number are n.r, r n x m input switching matrix modules are used for the input stage T1, r x n output switching matrix modules are used for the output stage T3, and m x r x r switching matrix modules are used for the intermediate stage T2:
wherein Z j For output port j, the routing list for all input ports is as follows:
wherein z is i,j Is output port j, connected to port jWhen the input port is I, the control parameters of the input stage, the intermediate stage and the output stage are as follows:
z i,j ＝[A 1,i,j ,A 2,i,j ,A 3,i,j ]
wherein A is 1,i,j ＝(a,T 1,a )，a＝(1,2,...,r)；
A 2,i,j ＝(b,T 2,b )，b＝(1,2,...,r)；
A 3,i,j ＝(c,T 3,c )，c＝(1,2,...,r)；
Wherein T is 1,a ,T 2,b ,T 3,c Respectively representing control parameters of an input stage number a sub-matrix, control parameters of a middle stage number b sub-matrix and control parameters of an output stage number c sub-matrix;
s2: establishing a memory table:
the depth of the memory table is selected to be 2 or 4 or 8 or 16, the depth of the memory table is selected to be 2 bit depth at the shallowest, the depth of the memory table is selected to be 16 bit depth at the deepest, the memory table is configured according to the scale of the switching matrix, the scale is less than 32 x 32, the scale is selected to be 2, 32 x 32 to 64 x 64, the scale is selected to be 4, 64 x 64 to 128 x 128, the scale is selected to be 8, the scale is greater than 128 x 128, and the depth of the memory table is selected to be 16;
s3: selecting a response port number packet Z in the routing table according to the output port number j j ；
S4: in the group Z j Memory meter M j Searching, if the searching is successful, jumping to the step S6, and if the searching is failed, performing the step S5;
s5: according to the current routing state, if the new input port number i is smaller than the input port number h of the current routing state, the search query direction is developed upwards, and if the new input port number is larger than the input port number h of the current routing state, the search query direction is developed downwards;
s6: according to the inquired route control parameter [ A ] 1,i,j ,A 2,i,j ,A 3,i,j ]Respectively controlling the on-off of each switch in the input stage matrix a, the intermediate stage matrix b and the output stage matrix c;
s7: and updating the memory table, wherein a first-in first-out mode is adopted, the routing state used last time is arranged at the first position, the routing state used last time is arranged at the second position, and the like, the routing state of the deepest position is forgotten, and the memory table is quitted.
The routing selection and control are completed by a simple low-cost singlechip.
The invention has the beneficial effects that: establishing a routing state table and a short-time memory table, using the current connection state as prior knowledge, adopting a memory search and update method to realize the quick selection of the routing, averagely reducing the table lookup search calculation amount to 1/2N, spending little calculation amount and realizing the quick selection of the switching matrix routing.
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To illustrate the technical solutions of the embodiments of the present invention more clearly, the drawings of the embodiments will be briefly introduced, and it is obvious that the drawings in the following description only relate to some embodiments of the present invention, and are not to limit the present invention.
FIG. 1 is a logic diagram of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without inventive step, are within the scope of protection of the invention.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of the word "comprising" or "comprises", and the like, in this disclosure is intended to mean that the elements or items listed before that word, include the elements or items listed after that word, and their equivalents, without excluding other elements or items. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
The invention is further illustrated by the following examples in conjunction with the drawings.
A radio frequency intermediate frequency three-level CLOS non-blocking switching matrix route rapid selection method comprises the following steps:
s1: establishing a routing table: the routing table is grouped according to the output port number, the input port numbers in the group are arranged from small to large, the routing table defines the control parameters of the module switch needed to be configured in the input stage T1, the intermediate stage T2 and the output stage T3, the control parameters of the routing table are arranged according to a matrix, and the routing table control parameter matrix of the C (n, m, r) non-blocking switching matrix is as follows, wherein C (n, m, r) represents the non-blocking switching matrix that the input port number and the output port number are n.r, r n x m input switching matrix modules are used for the input stage T1, r x n output switching matrix modules are used for the output stage T3, and m x r x r switching matrix modules are used for the intermediate stage T2:
wherein Z j For output port j, the routing list for all input ports is as follows:
wherein z is i,j When the output port is the output port of the number j and is connected to the input port of the number i, the control parameters of the input stage, the intermediate stage and the output stage are as follows:
z i ,j＝[A 1,i,j ,A 2,i,j ,A 3,i,j ]
wherein A is 1,i,j ＝(a,T 1,a )，a＝(1,2,...,r)；
A 2,i,j ＝(b,T 2,b )，b＝(1,2,...,r)；
A 3,i,j ＝(c,T 3,c )，c＝(1,2,...,r)；
Wherein T is 1,a ,T 2,b ,T 3,c Control of sub-matrices representing input stage number a respectivelyParameters, control parameters of a middle-stage number b sub-matrix and control parameters of an output-stage number c sub-matrix;
s2: establishing a memory table:
the depth of the memory table is selected to be 2 or 4 or 8 or 16, the depth of the memory table is selected to be 2 bit depth at the shallowest, the depth of the memory table is selected to be 16 bit depth at the deepest, the memory table is configured according to the scale of the switching matrix, the scale is less than 32 x 32, the scale is selected to be 2, 32 x 32 to 64 x 64, the scale is selected to be 4, 64 x 64 to 128 x 128, the scale is selected to be 8, the scale is greater than 128 x 128, and the depth of the memory table is selected to be 16;
s3: selecting a response port number packet Z in the routing table according to the output port number j j ；
S4: in the group Z j Memory meter M j Searching, if the searching is successful, jumping to the step S6, and if the searching is failed, performing the step S5;
s5: according to the current routing state, if the new input port number i is smaller than the input port number h of the current routing state, the search query direction is developed upwards, and if the new input port number is larger than the input port number h of the current routing state, the search query direction is developed downwards;
s6: according to the inquired route control parameter [ A ] 1,i,j ,A 2,i,j ,A 3,i,j ]Respectively controlling the on-off of each switch in the input stage matrix a, the intermediate stage matrix b and the output stage matrix c;
s7: and updating the memory table, adopting a first-in first-out mode, arranging the routing state used last time at the first position, arranging the routing state used last time at the second position, and so on, forgetting the routing state of the deepest position, and exiting the memory table.
The routing selection and control are completed by a simple low-cost singlechip.
The invention utilizes the state that the radio frequency intermediate frequency three-level CLOS non-blocking switching matrix is not completely disconnected in actual use to establish routing tables from all input ports to output ports, and divides the routing tables into 2 levels, wherein the routing tables comprise 2 routes which are selected most recently for 2 times and are used as a first-level routing table, and the rest are used as a second-level routing table; when the route is changed, firstly inquiring in the memory list, and simultaneously automatically updating the memory list, if the inquiry is successful, obtaining the route configuration of the input stage, the intermediate stage and the output stage switching module; if the query fails, switching to a second-level routing table for searching, and performing branch query by using the port number and the current routing state to finally obtain the routing configuration of the input-level switching module, the intermediate-level switching module and the output-level switching module; and transmitting the routing of the three modules to the corresponding modules to realize the routing of the radio frequency intermediate frequency three-stage CLOS non-blocking switching matrix, as shown in FIG. 1.
Although the present invention has been described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the present invention.
Claims (2)
1. A radio frequency intermediate frequency three-level CLOS non-blocking switching matrix route rapid selection method is characterized by comprising the following steps:
s1: establishing a routing table: the routing table is grouped according to the output port number, the input port numbers in the group are arranged from small to large, the routing table defines the control parameters of the module switch needed to be configured in the input stage T1, the intermediate stage T2 and the output stage T3, the control parameters of the routing table are arranged according to a matrix, and the routing table control parameter matrix of the C (n, m, r) non-blocking switching matrix is as follows, wherein C (n, m, r) represents the non-blocking switching matrix that the input port number and the output port number are n.r, the input stage T1 is provided with r n x m input switching matrix modules, the output stage T3 is provided with r x n output switching matrix modules, and the intermediate stage T2 is provided with m x r switching matrix modules:
wherein Z j For output port j, the routing list for all input ports is as follows:
wherein z is i，j When the output port is the output port of the number j and is connected to the input port of the number i, the control parameters of the input stage, the intermediate stage and the output stage are as follows:
z i，j ＝[A 1，i，j ，A 2，i，j ，A 3，i，j ]
wherein A is 1，i，j ＝(a，T 1，a )，a＝(1，2，...，r)；
A 2，i，j ＝(b，T 2，b )，b＝(1，2，...，r)；
A 3，i，j ＝(c，T 3，c )，c＝(1，2，...，r)；
Wherein T is 1，a ，T 2，b ，T 3，c Respectively representing control parameters of an input stage number a sub-matrix, control parameters of a middle stage number b sub-matrix and control parameters of an output stage number c sub-matrix;
s2: establishing a memory table:
the depth of the memory table is selected to be 2 or 4 or 8 or 16, the depth of the memory table is selected to be 2 bit depth at the shallowest, the depth of the memory table is selected to be 16 bit depth at the deepest, the memory table is configured according to the scale of the switching matrix, the scale is less than 32 x 32, the scale is selected to be 2, 32 x 32 to 64 x 64, the scale is selected to be 4, 64 x 64 to 128 x 128, the scale is selected to be 8, the scale is greater than 128 x 128, and the depth of the memory table is selected to be 16;
s3: according to the output port number j, selecting a response port number group Z in the routing table j ；
S4: in the group Z j Memory meter M j Searching, if the searching is successful, jumping to the step S6, and if the searching is failed, performing the step S5;
s5: according to the current routing state, if the new input port number i is smaller than the input port number h of the current routing state, the search query direction is developed upwards, and if the new input port number i is larger than the input port number h of the current routing state, the search query direction is developed downwards;
s6: according to the inquired route control parameter [ A ] 1,i,j ,A 2,i,j ,A 3,i,j ]Respectively controlling the on-off of each switch in the input stage matrix a, the intermediate stage matrix b and the output stage matrix c;
s7: and updating the memory table, wherein a first-in first-out mode is adopted, the routing state used last time is arranged at the first position, the routing state used last time is arranged at the second position, and the like, the routing state of the deepest position is forgotten, and the memory table is quitted.
2. The method as claimed in claim 1, wherein the routing is performed by a single chip.
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