CN114978054B - Self-zeroing operational amplifier - Google Patents
Self-zeroing operational amplifier Download PDFInfo
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- CN114978054B CN114978054B CN202210698748.8A CN202210698748A CN114978054B CN 114978054 B CN114978054 B CN 114978054B CN 202210698748 A CN202210698748 A CN 202210698748A CN 114978054 B CN114978054 B CN 114978054B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/38—DC amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/372—Noise reduction and elimination in amplifier
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Abstract
The embodiment of the disclosure provides a self-zeroing operational amplifier, which comprises four choppers, two first-stage amplifiers, a second-stage amplifier, two zeroing amplifiers, four storage capacitors and six switches, wherein a ping-pong architecture is used in the self-zeroing operational amplifier, a large off-chip capacitor is not needed, and a chopping technology is used for modulating low-frequency aliasing noise to a chopping frequency on the basis of the self-zeroing technology, so that noise characteristics which are very low in a range from direct current to chopping frequency are obtained, an additional filter circuit is not needed, the area is smaller, and the precision is higher.
Description
Technical Field
Embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular, to a self-zeroing operational amplifier.
Background
Currently, for the field of high-precision signal detection, an amplifier is generally required to have very low offset voltage and low noise characteristic within a certain signal bandwidth (< kHz), and common methods are a chopping technology and a self-zeroing technology.
Chopping is a modulation technique that modulates low frequency noise and offset voltages to the chopping frequency, but the noise energy at the chopping frequency is high, and to eliminate this effect, a low pass filter circuit is typically required. The self-zeroing technology is a sampling technology, namely, offset voltage and low-frequency noise are sampled firstly and then subtracted in the next clock period, so that offset voltage is eliminated, but aliasing of thermal noise is caused, low-frequency noise is increased, and sampling capacitance and power consumption are required to be increased in order to reduce low-frequency noise. In summary, current solutions for implementing amplifiers with very low offset voltages and low noise characteristics over a certain signal bandwidth increase circuit area and power consumption.
Disclosure of Invention
The embodiments described herein provide a self-zeroing operational amplifier in order to provide an amplifier with very low offset voltage and low noise characteristics over a certain signal bandwidth.
According to a first aspect of the present disclosure, there is provided a self-zeroing operational amplifier comprising: the four chopper, two first-stage amplifiers, the second-stage amplifier, two zeroing amplifiers, four storage capacitors and six switches, wherein through the arrangement of opening and closing the six switches, an input signal is alternately modulated through a first chopper and a third chopper, the input signal through the first chopper is amplified through the first-stage amplifier, the signal is demodulated through the second chopper, the signal is output through the second-stage amplifier after the signal is demodulated, the input signal through the third chopper is amplified through the second first-stage amplifier, the signal is demodulated through the fourth chopper after the signal is demodulated, and the signal is output through the second-stage amplifier after the signal is demodulated; the input signal is a low-frequency differential signal; the first zeroing amplifier alternately stores and counteracts the offset voltage of the first-stage amplifier through a first storage capacitor and a second storage capacitor, and the second zeroing amplifier alternately stores and counteracts the offset voltage of the second first-stage amplifier through a third storage capacitor and a fourth storage capacitor; the second chopper and the fourth chopper alternately modulate low-frequency aliasing noise of the self-zeroing operational amplifier during self-zeroing sampling to a chopping frequency.
Optionally, the input end of the first chopper is connected with an input signal, the two output ends of the first chopper are respectively connected with the normal phase input end and the reverse phase input end of the first stage amplifier, the normal phase output end of the first stage amplifier is sequentially connected between the second chopper and the normal phase input end of the first zeroing amplifier after being switched by the second switch, the reverse phase output end of the first stage amplifier is sequentially connected with the second chopper and the reverse phase input end of the first zeroing amplifier after being switched by the third switch, the normal phase output end and the reverse phase output end of the first zeroing amplifier are respectively connected with the reverse phase output end and the normal phase output end of the first stage amplifier in a feedback manner, one end of the first switch is connected between the first output end of the first chopper and the normal phase input end of the first stage amplifier, the other end of the first switch is connected between the first chopper and the reverse phase output end of the first stage amplifier, the other end of the first switch is connected between the first input end of the first chopper and the first stage amplifier, the other end of the first switch is connected between the first input end of the first switch and the first amplifier, the other end of the first switch is connected with the first capacitor; the input end of the third chopper is connected with an input signal, the two output ends of the third chopper are respectively connected with the normal phase input end and the reverse phase input end of the second first-stage amplifier, the normal phase output end of the second first-stage amplifier is sequentially connected between the first output end of the third chopper and the normal phase input end of the second first-stage amplifier, the reverse phase output end of the second first-stage amplifier is sequentially connected with the fourth chopper and the reverse phase input end of the sixth switch, the normal phase output end and the reverse phase output end of the second zero-stage amplifier are respectively connected with the reverse phase output end and the normal phase output end of the second first-stage amplifier in a feedback manner, one end of the fourth switch is connected between the first output end of the third chopper and the normal phase input end of the second first-stage amplifier, the other end of the fourth switch is connected between the other end of the third chopper and the reverse phase output end of the second first-stage amplifier, the other end of the fourth switch is connected between the fourth chopper and the reverse phase output end of the fourth switch and the second-stage amplifier, the other end of the fourth switch is connected between the second input end of the fourth chopper and the second-stage amplifier, the second-stage amplifier is connected between the reverse phase capacitor and the second input end of the fourth switch is connected with the second capacitor; the output end of the second-stage amplifier is a signal output end, the normal phase input end of the second-stage amplifier is respectively connected between one output end of the second chopper and the second switch, between one output end of the fourth chopper and the fifth switch, the reverse phase input end of the second-stage amplifier is respectively connected between the other output end of the second chopper and the third switch, between the other output end of the fourth chopper and the sixth switch, and the output end of the second-stage amplifier is connected with a compensation capacitor and then is connected to the reverse phase input end of the second-stage amplifier in a feedback manner.
Optionally, the clock control signals of the first switch, the second switch and the third switch are first clock signals, the clock control signals of the fourth switch, the fifth switch and the sixth switch are second clock signals, and the first clock signals and the second clock signals are two non-overlapping clock signals.
Optionally, the clock control signals of the first chopper and the second chopper are third clock signals, the clock control signals of the third chopper and the fourth chopper are fourth clock signals, the periods of the third clock signals, the fourth clock signals, the first clock signals and the second clock signals are the same, the first clock signals and the fourth clock signals arrive at the same time, the duration of the first clock signals is twice the duration of the fourth clock signals, the duration of the second clock signals and the third clock signals arrive at the same time, and the duration of the second clock signals is twice the duration of the third clock signals.
Optionally, the difference between the voltages stored on the first storage capacitor and the second storage capacitor is equal to the transconductance of the first stage amplifier multiplied by the offset voltage of the first stage amplifier divided by the transconductance of the first zeroing amplifier; the difference between the voltages stored on the third storage capacitor and the fourth storage capacitor is equal to the transconductance of the second first stage amplifier multiplied by the offset voltage of the second first stage amplifier divided by the transconductance of the second zeroing amplifier.
Optionally, the transconductance of the first stage amplifier is greater than the transconductance of the first zeroing amplifier; the transconductance of the second first stage amplifier is greater than the transconductance of the second zeroed amplifier.
Optionally, the transconductance of the first stage amplifier is ten times that of the first zeroing amplifier; the transconductance of the second first stage amplifier is ten times that of the second zeroed amplifier.
Optionally, the capacitance ranges of the first storage capacitor, the second storage capacitor, the third storage capacitor and the fourth storage capacitor are greater than or equal to 10 picofarads and less than or equal to 20 picofarads.
Optionally, the input signal is a high-precision sensor signal.
According to a second aspect of the present disclosure, there is provided a gain-adjustable amplifier, the gain-adjustable amplifier including the self-zeroing operational amplifier according to any one of the first aspect and an external resistor, the self-zeroing operational amplifier being connected to the external resistor with different resistance values to adjust gain.
A self-zeroing operational amplifier of an embodiment of the present disclosure includes: the four chopper, two first-stage amplifiers, the second-stage amplifier, two zeroing amplifiers, four storage capacitors and six switches, wherein through the arrangement of opening and closing the six switches, an input signal is alternately modulated through a first chopper and a third chopper, the input signal through the first chopper is amplified through the first-stage amplifier, then is demodulated through the second chopper, then is output through the second-stage amplifier, the input signal through the third chopper is amplified through the second first-stage amplifier, and then is output through the second-stage amplifier after being demodulated; the input signal is a low-frequency differential signal; the first zeroing amplifier alternately stores and counteracts the offset voltage of the first-stage amplifier through the first storage capacitor and the second storage capacitor, and the second zeroing amplifier alternately stores and counteracts the offset voltage of the second first-stage amplifier through the third storage capacitor and the fourth storage capacitor; the second chopper and the fourth chopper alternately modulate the low-frequency aliasing noise of the self-zeroing operational amplifier during the self-zeroing sampling process to the chopping frequency. It can be seen that the self-zeroing operational amplifier in the embodiment of the disclosure adopts the self-zeroing technology and the chopping technology at the same time, and on the basis of the self-zeroing technology, the chopping technology is used for modulating the low-frequency aliasing noise to the chopping frequency, so that the noise characteristic of very low in the range from direct current to the chopping frequency is obtained, no additional filter circuit is needed, and the self-zeroing uses a ping-pong architecture, so that a very large off-chip capacitor is not needed. Therefore, the area is smaller and the power consumption is lower compared to the existing solutions.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following brief description of the drawings of the embodiments will be given, it being understood that the drawings described below relate only to some embodiments of the present disclosure, not to limitations of the present disclosure, in which:
FIG. 1 is an exemplary circuit diagram of a self-zeroing operational amplifier according to an embodiment of the present disclosure;
Fig. 2 is a timing diagram corresponding to a switch and chopper according to an embodiment of the present disclosure.
Elements in the figures are illustrated schematically and not drawn to scale.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by those skilled in the art based on the described embodiments of the present disclosure without the need for creative efforts, are also within the scope of the protection of the present disclosure.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate parts.
In all embodiments of the present disclosure, additionally, terms such as "first" and "second" are used merely to distinguish one component (or portion of a component) from another component (or another portion of a component).
First, it should be noted that the self-zeroing operational amplifier in the embodiments of the present disclosure is a ping-pang (ping-pong) self-zeroing operational amplifier that uses a chopping technique to reduce low-frequency aliasing noise. The low frequency aliasing noise is mainly caused by the difference between the sampling frequency and the bandwidth, and the specific input signal of the embodiment of the disclosure is a low frequency (Kb level) input signal, which is greatly different from the bandwidth frequency (Gb level) of the thermal noise, so that the thermal noise of high frequency is aliased to low frequency when sampling. The self-zeroing operational amplifier of the embodiment of the disclosure combines the advantages of a chopping technology and a self-zeroing technology, wherein the self-zeroing technology of a sampling ping-pang structure does not need a large off-chip capacitor, and on the basis of the self-zeroing technology, a chopping technology is used for modulating low-frequency aliasing noise to a chopping frequency, so that the noise characteristic of low direct current to the chopping frequency range is obtained, and an additional filter circuit is not needed. The following describes the specific circuit configuration in detail.
Fig. 1 shows an exemplary circuit diagram of a self-zeroing operational amplifier 10. In the example of fig. 1, the self-zeroing operational amplifier 10 includes: four choppers, two first-stage amplifiers, two second-stage amplifiers, two zeroing amplifiers, four storage capacitors and six switches, wherein the main structure is a ping-pang self-zeroing amplifier consisting of six switches S1, S2, S3, S4, S5 and S6, two first-stage amplifiers (A1 and A2) are input stages, one second-stage amplifier A0 is output stage, and two zeroing amplifiers (A3 and A4). The four choppers (CH 1, CH2, CH3, CH 4) are designed to eliminate the increase in low frequency noise caused by the self-zeroing technique.
Specifically, as shown in fig. 1, the input end of the first chopper CH1 is connected with an input signal (INN, INP), two output ends of the first chopper CH1 are respectively connected with a normal phase input end and an inverted phase input end of the first stage amplifier A1, the normal phase output end of the first stage amplifier A1 is sequentially connected with the second chopper CH2 and the normal phase input end of the first zeroing amplifier A3 after being connected with the second chopper CH2 and the third switch S3, the inverted phase output end of the first stage amplifier A1 is sequentially connected with the inverted phase input end of the first zeroing amplifier A3, the normal phase output end and the inverted phase output end of the first zeroing amplifier A3 are respectively connected with the inverted phase output end and the normal phase output end of the first stage amplifier A1 in a feedback manner, one end of the first switch S1 is connected between the first output end of the first chopper CH1 and the normal phase input end of the first stage amplifier A3, the other end of the first switch S1 is connected between the first input end of the first chopper C1 and the first stage amplifier C2, the other end of the first switch S1 is connected between the second input end of the first switch C1 and the second switch C2, and the other end of the first switch C1 is connected between the first input end of the first switch C2 and the first switch C2 is connected with the storage capacitor C2; the input end of the third chopper CH3 is connected with an input signal, two output ends of the third chopper CH3 are respectively connected with a normal phase input end and an opposite phase input end of the second first-stage amplifier A2, the normal phase output end of the second first-stage amplifier A2 is sequentially connected with a fourth chopper CH4 and a fifth switch S5 and then is connected with the normal phase input end of the second zeroing amplifier A4, the opposite phase output end of the second first-stage amplifier A2 is sequentially connected with a fourth chopper CH4 and a sixth switch S6 and then is connected with the opposite phase input end of the second zeroing amplifier A4, the normal phase output end and the opposite phase output end of the second zeroing amplifier A4 are respectively connected with the opposite phase output end and the normal phase output end of the second first-stage amplifier A2 in a feedback manner, one end of the fourth switch S4 is connected between one output end of the third chopper CH3 and the normal phase input end of the second first-stage amplifier A4, the other end of the fourth switch S4 is connected between the other end of the third chopper CH3 and the second input end of the third switch C4 and the second input end of the third chopper C4, and the other end of the third switch S4 is connected between the other end of the third chopper C3 and the third input end of the third switch C4 and the third switch C4 is connected with the opposite phase output end of the third capacitor A4; the output end of the second-stage amplifier A0 is a signal output end (V OUT), the normal phase input end of the second-stage amplifier A0 is respectively connected between one output end of the second chopper CH2 and the second switch S2, one output end of the fourth chopper CH4 and the fifth switch S5, the reverse phase input end of the second-stage amplifier A0 is respectively connected between the other output end of the second chopper CH2 and the third switch S3, the other output end of the fourth chopper CH4 and the sixth switch S6, and the output end of the second-stage amplifier A0 is connected with the compensation capacitor C0 and then is connected with the reverse phase input end of the second-stage amplifier A0 in a feedback mode.
In combination with the circuit diagram of fig. 1, through the switching arrangement of six switches, differential input signals are alternately modulated by a first chopper CH1 and a third chopper CH3, the input signals passing through the first chopper CH1 are amplified by a first-stage amplifier A1, then are demodulated by a second chopper CH2, then are output by a second-stage amplifier A0, the input signals passing through the third chopper CH3 are amplified by a second first-stage amplifier A2, and then are demodulated by a fourth chopper CH4, and then are output by a second-stage amplifier A0; the input signal is a low-frequency differential signal; the first zeroing amplifier A3 stores and counteracts the offset voltage of the first-stage amplifier A1 through a first storage capacitor C1 and a second storage capacitor C2 alternately, and the second zeroing amplifier A4 stores and counteracts the offset voltage of the second first-stage amplifier A2 through a third storage capacitor C3 and a fourth storage capacitor C4 alternately; the second chopper CH2 and the fourth chopper CH4 alternately modulate the low frequency aliasing noise of the self-zeroing operational amplifier during the self-zeroing sampling to the chopping frequency.
In the embodiment of the present disclosure, for the switching arrangement of six switches, see, in particular, the timing diagram of the switches provided in fig. 2. Specifically, the clock control signals of the first switch S1, the second switch S2, and the third switch S3 are the first clock signal Φ1, the clock control signals of the fourth switch S4, the fifth switch S5, and the sixth switch S6 are the second clock signal Φ2, and the first clock signal Φ1 and the second clock signal Φ2 are two non-overlapping clock signals. In addition, the four choppers also need to be clocked, as shown in fig. 2, in the timing diagrams of the specific four choppers, the clock control signals of the first chopper CH1 and the second chopper CH2 are the third clock signal Φ3, the clock control signals of the third chopper CH3 and the fourth chopper CH4 are the fourth clock signal Φ4, the periods of the third clock signal Φ3, the fourth clock signal Φ4, the first clock signal Φ1 and the second clock signal Φ2 are the same, the first clock signal Φ1 and the fourth clock signal Φ4 arrive at the same time, the duration of the first clock signal Φ1 is twice the duration of the fourth clock signal Φ4, the second clock signal Φ2 and the third clock signal Φ3 arrive at the same time, and the duration of the second clock signal Φ2 is twice the duration of the third clock signal Φ3.
The operation principle of the self-zeroing operational amplifier in the embodiment of the present disclosure is further described with reference to the circuit diagram of fig. 1 and the timing diagram of fig. 2. When the switches S1, S2, S3 are at a high level, the input end of the input stage A1 is shorted, the output end thereof is connected to the input end of A3, and the output end of A3 is fed back to the output end of A1, so that the offset voltage (input offset voltage) of A1 is stored in the storage capacitors C1, C2 so as to be subtracted in the next period, when the switches S1, S2, S3 are at a high level, the switches S4, S5, S6 are at a low level, the switches A2, A4, A0 form an amplifier circuit (wherein the amplification of signals is mainly responsible for the operations of A2, A0 and A4 are zero-setting, namely, offset voltage cancellation is performed), the input signals are amplified normally, and meanwhile, the offset voltage (input offset voltage) of A2 is offset by the offset voltage of A2 stored in the previous period in the capacitors C3, C4; similarly, when the switches S4, S6 are at high level, the input end of the input stage A2 is shorted, the output end thereof is connected to the input end of A4, and the output end of A4 is fed back to the output end of A2, so that the offset voltage (input offset voltage) of A2 is stored in the storage capacitors C3, C4 so as to be subtracted in the next period, when the switches S4, S5, S6 are at high level, S1, S2, S3 are at low level, A1, A3, A0 form an amplifier circuit (wherein the amplification of signals is mainly responsible for A1, A0, the effect of A3 is zero setting, that is, the offset voltage is eliminated), the input signal is amplified normally, and meanwhile, the offset voltage (input offset voltage) of A1 is also offset by the offset voltage of A1 stored in the previous period in C1, C2. Thus, a continuous time ping-pang self-zeroing amplifier is realized and no large off-chip capacitance is required. According to the timing diagram of the chopper in fig. 2, four choppers, in which the clock signals of CH1 and CH2 are the same, CH1 and CH2 operate when the switches S1, S2, S3 are at low level, and the input signals are modulated and demodulated respectively through CH1, CH 2; when the switches S4, S5 and S6 are at low level, the CH3 and the CH4 work, and the input signals are modulated and demodulated respectively through the CH3 and the CH 4; the elimination of low frequency aliasing noise is mainly achieved by CH2 and CH4, and in addition, it can be seen from fig. 2 that the chopping frequency is twice the self-stabilizing zero frequency, so that the low frequency aliasing noise will be modulated at the chopping frequency, resulting in a noise energy characteristic that is very low from direct current to the chopping frequency. Again, since the self-zeroing technique has removed most of the noise energy, the noise energy modulated at the chopping frequency here is also relatively low, so that no additional low pass filter can be used.
In addition, the difference between the voltages stored in the first storage capacitor C1 and the second storage capacitor C2 is equal to the transconductance of the first stage amplifier A1 multiplied by the offset voltage of the first stage amplifier A1 divided by the transconductance of the first zeroing amplifier A3, and specific examples are given for illustration: assuming that the offset voltage of A1 is V os1, the difference between the voltages stored on C1 and C2 is: (g m1*Vos1)/gm3, wherein g m1,gm3 is the transconductance of A1, A3.
Similarly, the difference between the voltages stored in the third storage capacitor C3 and the fourth storage capacitor C4 is equal to the transconductance of the second first stage amplifier A2 multiplied by the offset voltage of the second first stage amplifier A2 divided by the transconductance of the second zeroing amplifier A4, and specific examples are given for illustration: assuming that the offset voltage of A2 is V os2, the difference between the voltages stored on C3 and C4 is: (g m2*Vos2)/gm4, wherein g m2,gm4 is the transconductance of A2, A4.
It should be further noted that, in order to make the capacitance stored on the storage capacitor more accurate and guarantee the accuracy, it is necessary to satisfy that the transconductance of the first stage amplifier A1 is greater than that of the first zeroing amplifier A3; similarly, the transconductance of the second first stage amplifier A2 is greater than the transconductance of the second zeroed amplifier A4. Preferably, the transconductance of the first stage amplifier A1 is ten times that of the first zeroed amplifier A3; the transconductance of the second first stage amplifier A2 is ten times that of the second zeroed amplifier A4.
In the embodiment of the present disclosure, in order to prevent excessive leakage and increase in circuit area, the capacitance values of the first storage capacitor, the second storage capacitor, the third storage capacitor, and the fourth storage capacitor cannot be too small or too large, and the capacitance ranges of the four storage capacitors in the preferred embodiment are 10 picofarads or more and 20 picofarads or less.
Based on the above description of the self-zeroing amplifier of the embodiments of the present disclosure, the embodiments of the present disclosure are applicable to sensor signals with high accuracy and low frequency input signals. A specific application may be in applications requiring accurate current sensing of amplifiers for pressure sensors, temperature sensors, etc.
In summary, the self-zeroing operational amplifier according to the embodiments of the present disclosure uses a chopping technique to reduce low frequency aliasing noise, does not require an additional low pass filter, does not require a large off-chip capacitor, and has a smaller area.
According to a second aspect of the present disclosure, there is further provided a gain-adjustable amplifier, including the self-zeroing operational amplifier 10 of fig. 1 and an external resistor, where the self-zeroing operational amplifier is connected to the external resistor with different resistance values (the external resistor is an external resistor with respect to the self-zeroing operational amplifier) to adjust the gain. The self-zeroing operational amplifier of fig. 1 is different from an instrument amplifier, and the instrument amplifier has a fixed gain, but the self-zeroing operational amplifier in the embodiment of the disclosure needs to be matched with an external resistor for use, so that a user can configure the gain according to the requirement of the user, and the self-zeroing operational amplifier is very flexible.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus and methods according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "comprising" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a set of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or broad.
Further aspects and scope of applicability will become apparent from the description provided herein. It should be understood that various aspects of the disclosure may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.
While several embodiments of the present disclosure have been described in detail, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present disclosure without departing from the spirit and scope of the disclosure. The scope of the present disclosure is defined by the appended claims.
Claims (10)
1. A self-zeroing operational amplifier, the self-zeroing operational amplifier comprising: the four chopper, two first-stage amplifiers, the second-stage amplifier, two zeroing amplifiers, four storage capacitors and six switches, wherein through the arrangement of opening and closing the six switches, an input signal is alternately modulated through a first chopper and a third chopper, the input signal through the first chopper is amplified through the first-stage amplifier, the signal is demodulated through the second chopper, the signal is output through the second-stage amplifier after the signal is demodulated, the input signal through the third chopper is amplified through the second first-stage amplifier, the signal is demodulated through the fourth chopper after the signal is demodulated, and the signal is output through the second-stage amplifier after the signal is demodulated; the input signal is a low-frequency differential signal;
the first zeroing amplifier alternately stores and counteracts the offset voltage of the first-stage amplifier through a first storage capacitor and a second storage capacitor, and the second zeroing amplifier alternately stores and counteracts the offset voltage of the second first-stage amplifier through a third storage capacitor and a fourth storage capacitor;
The second chopper and the fourth chopper alternately modulate low-frequency aliasing noise of the self-zeroing operational amplifier during self-zeroing sampling to a chopping frequency.
2. The self-zeroing operational amplifier according to claim 1, wherein the input end of the first chopper is connected with an input signal, the two output ends of the first chopper are respectively connected with the normal phase input end and the reverse phase input end of the first stage amplifier, the normal phase output end of the first stage amplifier is sequentially connected with the second chopper and the second switch and then is connected with the normal phase input end of the first zeroing amplifier, the reverse phase output end of the first stage amplifier is sequentially connected with the second chopper and the third switch and then is connected with the reverse phase input end of the first zeroing amplifier, the normal phase output end and the reverse phase output end of the first zeroing amplifier are respectively connected with the reverse phase output end and the normal phase output end of the first stage amplifier in a feedback manner, one end of a first switch is connected between one output end of the first chopper and the non-inverting input end of the first-stage amplifier, the other end of the first switch is connected between the other output end of the first chopper and the inverting input end of the first-stage amplifier, one ends of the first storage capacitor and the second storage capacitor are grounded, the other end of the first storage capacitor is connected between the second switch and the non-inverting input end of the first zeroing amplifier, and the other end of the second storage capacitor is connected between the third switch and the inverting input end of the first zeroing amplifier;
the input end of the third chopper is connected with an input signal, the two output ends of the third chopper are respectively connected with the normal phase input end and the reverse phase input end of the second first-stage amplifier, the normal phase output end of the second first-stage amplifier is sequentially connected between the first output end of the third chopper and the normal phase input end of the second first-stage amplifier, the reverse phase output end of the second first-stage amplifier is sequentially connected with the fourth chopper and the reverse phase input end of the sixth switch, the normal phase output end and the reverse phase output end of the second zero-stage amplifier are respectively connected with the reverse phase output end and the normal phase output end of the second first-stage amplifier in a feedback manner, one end of the fourth switch is connected between the first output end of the third chopper and the normal phase input end of the second first-stage amplifier, the other end of the fourth switch is connected between the other end of the third chopper and the reverse phase output end of the second first-stage amplifier, the other end of the fourth switch is connected between the fourth chopper and the reverse phase output end of the fourth switch and the second-stage amplifier, the other end of the fourth switch is connected between the second input end of the fourth chopper and the second-stage amplifier, the second-stage amplifier is connected between the reverse phase capacitor and the second input end of the fourth switch is connected with the second capacitor;
The output end of the second-stage amplifier is a signal output end, the normal phase input end of the second-stage amplifier is respectively connected between one output end of the second chopper and the second switch, between one output end of the fourth chopper and the fifth switch, the reverse phase input end of the second-stage amplifier is respectively connected between the other output end of the second chopper and the third switch, between the other output end of the fourth chopper and the sixth switch, and the output end of the second-stage amplifier is connected with a compensation capacitor and then is connected to the reverse phase input end of the second-stage amplifier in a feedback manner.
3. The self-zeroing operational amplifier of claim 2, wherein the clock control signals of the first switch, the second switch, and the third switch are first clock signals, the clock control signals of the fourth switch, the fifth switch, and the sixth switch are second clock signals, and the first clock signal and the second clock signal are two-phase non-overlapping clock signals.
4. A self-zeroing operational amplifier according to claim 3, wherein the clock control signals of the first chopper and the second chopper are third clock signals, the clock control signals of the third chopper and the fourth chopper are fourth clock signals, the periods of the third clock signal, the fourth clock signal, the first clock signal and the second clock signal are the same, the first clock signal and the fourth clock signal arrive at the same time, the duration of the first clock signal is twice the duration of the fourth clock signal, the duration of the second clock signal and the third clock signal arrive at the same time, and the duration of the second clock signal is twice the duration of the third clock signal.
5. The self-zeroing operational amplifier of claim 2, wherein the difference between the voltages stored on said first storage capacitor and said second storage capacitor is equal to the transconductance of said first stage amplifier multiplied by the offset voltage of said first stage amplifier divided by the transconductance of said first zeroing amplifier; the difference between the voltages stored on the third storage capacitor and the fourth storage capacitor is equal to the transconductance of the second first stage amplifier multiplied by the offset voltage of the second first stage amplifier divided by the transconductance of the second zeroing amplifier.
6. The self-zeroing operational amplifier of claim 5, wherein the transconductance of said first stage amplifier is greater than the transconductance of said first zeroing amplifier; the transconductance of the second first stage amplifier is greater than the transconductance of the second zeroed amplifier.
7. The self-zeroing operational amplifier of claim 6, wherein the transconductance of said first stage amplifier is ten times the transconductance of said first zeroing amplifier; the transconductance of the second first stage amplifier is ten times that of the second zeroed amplifier.
8. The self-zeroing operational amplifier according to claim 2, wherein the first storage capacitor, the second storage capacitor, the third storage capacitor, and the fourth storage capacitor have a capacitance range of 10 picofarads or more and 20 picofarads or less.
9. A self-zeroing operational amplifier according to claim 1, wherein said input signal is a high precision sensor signal.
10. A gain-adjustable amplifier, which is characterized by comprising the self-zeroing operational amplifier and an external resistor according to any one of claims 1 to 9, wherein the self-zeroing operational amplifier is connected with the external resistor with different resistance values to adjust gain.
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