CN114944187A

CN114944187A - TSV reconstruction-oriented stack memory aging test system

Info

Publication number: CN114944187A
Application number: CN202210697568.8A
Authority: CN
Inventors: 赵超; 郭雁蓉; 匡乃亮; 赵国良; 李庆
Original assignee: Xian Microelectronics Technology Institute
Current assignee: Xian Microelectronics Technology Institute
Priority date: 2022-06-20
Filing date: 2022-06-20
Publication date: 2022-08-26

Abstract

The invention discloses an aging test system for a TSV (through silicon via) reconstruction stack memory, which comprises a test fixture, a PCB (printed circuit board) and a driving circuit, wherein the test fixture is used for testing the TSV reconstruction stack memory; the test fixture is fixed on the PCB and used for clamping a device to be tested, the device to be tested is electrically connected with the PCB, and a heating device is arranged at the top of the device to be tested; the bottom of the tested device is provided with a temperature sensor which is electrically connected with the PCB; the driving circuit is arranged on the PCB, and a circuit of the tested device is electrically connected with the driving circuit. A through hole is formed in the center of a PCB at the bottom of the test fixture, a reinforcing plate is fixed to the bottom of the PCB, a groove is formed in the center of the reinforcing plate, a spring is arranged inside the groove, and a temperature measuring sensor is arranged at the top of the spring. The problem of signal long line transmission delay is solved, operating frequency is improved, aging efficiency is improved, and aging cost is controlled.

Description

TSV reconstruction-oriented stack memory aging test system

Technical Field

The invention belongs to the field of aging test of semiconductor integrated circuits, and particularly belongs to an aging test system for a TSV (through silicon via) reconstruction stacked memory.

Background

With the rapid development of electronic technology, the improvement of memory chip design capability and the improvement of manufacturing process, the speed of memory chips is continuously increased, and the storage capacity of memories is greatly improved by three-dimensional assembly represented by 3D packaging technology. In order to ensure the operational reliability of the memory chip, the burn-in screening of the memory chip is more and more emphasized, and the research on the burn-in test method is more and more increased. With the change of the dynamic aging concept in recent years, how to run the function test at full speed in the high-temperature aging environment becomes the biggest technical problem.

Traditional standard aging testing equipment adopts the design of drive plate + ageing board, and the drive plate is placed at the ageing oven back, moves under normal atmospheric temperature environment, and the ageing board is installed in the ageing oven, bears the high temperature environment, and drive plate and ageing board are through middle cross cabin connecting plate realization electrical signal connection. The traditional aging test system is oriented to the aging requirements of a discrete circuit and a power circuit, has low performance, cannot meet the dynamic aging requirements of a high-speed memory under the promotion of the large domestic background and military requirements, and the dynamic aging test method of the high-speed memory is a current research hotspot.

At present, the number of interface signals of the traditional aging test equipment is limited, and an aging test method of a non-standard system is generally adopted, namely, a drive plate and an aging plate both adopt a special customized method, the aging plate is freely placed in a high-temperature drying box, the drive plate is placed outside the aging box, and the two plates are connected through a cable. The structure solves the problem of the limitation of the number of signals of the interface of the traditional standard aging test box, but is limited by long-line transmission of cables, so that full-speed operation is difficult to achieve, and the aging test box usually operates at dozens of megafrequencies.

The traditional aging test system is limited by the signal quantity, connector selection and wiring conditions of a cabin-through connection system, signals can only work within 20MHz generally, and the requirement of hundreds of million dynamic aging of high-speed interface memories represented by DDR3, DDR4 and NAND FLASH is seriously not met.

The method adopts a non-calibration aging system, is limited by cable long-line transmission, and mainly has the problems that signal transmission delay is large and exceeds the timing sequence margin of a memory, and secondly, in the long-line transmission, signal quality is poor due to overshoot and reflection at the edge of a signal and the like, so that the long-line transmission is difficult to work at high frequency; finally, the memories represented by DDR3 and DDR4 have many signals, require a large number of cable cores, are extremely inconvenient to connect, and generally can only realize single-system one-to-one aging.

In summary, the conventional aging device has the disadvantages of low working frequency and small signal quantity, and the problems of large signal delay, low working frequency and low aging efficiency caused by long-line cable transmission of the non-standard aging system,

disclosure of Invention

In order to solve the problems in the prior art, the invention provides an aging test system for a TSV reconstruction stack memory, which aims to solve the problem of signal long line transmission delay, improve the working frequency, improve the aging efficiency and control the aging cost.

In order to achieve the purpose, the invention provides the following technical scheme:

an aging test system facing a TSV reconstruction stacked memory comprises a test fixture, a PCB and a driving circuit;

the testing fixture is fixed on the PCB and used for clamping a tested device, the tested device is electrically connected with the PCB, and a heating device is arranged at the top of the tested device;

the bottom of the tested device is provided with a temperature sensor which is electrically connected with the PCB; the drive circuit is arranged on the PCB, and a circuit of the tested device is electrically connected with the drive circuit.

Preferably, a through hole is formed in the center of the PCB at the bottom of the test fixture, a reinforcing plate is fixed to the bottom of the PCB, a groove is formed in the center of the reinforcing plate, a spring is arranged inside the groove, and a temperature measuring sensor is arranged at the top of the spring.

Preferably, the reinforcing plate is fixed to the PCB by screws.

Preferably, the temperature sensor is electrically connected with the connector through a wire, and the connector is electrically connected with the PCB.

Preferably, the driving circuit is an FPGA.

Preferably, the driving circuit is arranged at the central part of the PCB, the number of the test clamps is four, and the four test clamp arrays are arranged at the outer side of the driving circuit.

Preferably, the test fixture comprises a cover plate, a rotating handle, threads, a pressing block, a heating rod, an electric wire, a spring needle seat and a spring needle;

the top of the cover plate is provided with a through hole, the through hole is provided with threads, and the rotating handle penetrates through the through hole to be in threaded connection with the cover plate; the bottom of the rotating handle is connected with a pressing block, and a heating part is arranged inside the pressing block;

the bottom of the cover plate is fixed with a spring needle seat, a spring needle is arranged in the spring needle seat, the bottom of the spring needle is connected with the PCB, and a tested device is electrically connected with the PCB through the spring needle.

Further, the heating part includes heating rod and electric wire, and the heating rod sets up in the inside of briquetting, and the heating rod passes through the connection of electric wires power supply.

Further, the bottom of the pressing block is provided with a high-temperature organic sheet.

Preferably, the test fixture is electrically connected with a connector through a power supply cable, and the connector is connected with a PCB power supply circuit.

Compared with the prior art, the invention has the following beneficial technical effects:

the invention provides an aging test system for a TSV (through silicon via) reconstruction stack memory, which can operate the tested memory at the highest working speed by arranging a driver and a tested circuit on the same PCB (printed circuit board) nearby, realize the combination of test and aging and realize real dynamic aging; the aging plate has compact structure, realizes four-by-four aging under the size of a single plate of about 200mm multiplied by 200mm, occupies small space and ensures more economical aging; the aging box is separated from the operation, the scheme of local heating of the tested circuit is adopted, the temperature control is accurate, the energy consumption is low, the equipment dependence is low, other peripheral components and PCBs do not bear high-temperature environment, the selectable circuit requirement is low, the design is more universal, and the cost of the whole aging system is lower.

Drawings

FIG. 1 is a schematic structural diagram of an aging test system for a TSV reconfigurable stacked memory according to the present invention;

FIG. 2 is a schematic diagram of a memory structure processed based on a TSV reconstitution stack process;

FIG. 3 is a schematic structural diagram of a fixture for testing aging of a TSV stacked memory;

FIG. 4 is a schematic structural diagram of an aging test system for a TSV reconfigurable stacked memory according to the present invention;

in the drawings: 1 is a cover plate; 2 is a rotating handle; 3 is a screw thread; 4, pressing blocks; 5 is a heating rod; 6 is an electric wire; 7 is a high temperature organic flake material; 8 is the device under test; 9 is a spring needle seat; 10 is a spring needle; 11, a test fixture; 12 is a PCB board; 13 is a reinforcing plate; 14 is a screw; 15 is a temperature sensor; 16 is a spring; 17 is a connector; 18 is an electric wire; 19 is a power supply cable; 20 is a driving circuit; 21 is a TSV silicon substrate; 22 is an interlayer solder ball; 23 is a memory bare chip; 24 is filling glue; and 25 is an external PAD.

Detailed Description

The present invention will now be described in further detail with reference to specific examples, which are intended to be illustrative, but not limiting, of the invention.

The testing principle of the invention comprises two aspects: electrical principles and temperature control principles. As shown in FIG. 1, the present invention adopts a one-to-four design electrically, i.e. one driving circuit drives four tested memory circuits. The drive circuit selects FPGA with large IO number, high interface performance and programmable characteristic, the four tested memories adopt independent interfaces to ensure full-speed functional operation,

in the invention, four independent control logic blocks are integrated in the FPGA to independently control the power supplies of the four test stations and drive the tested circuit. Each test station designs a 64 bit control bus and a 72 bit data bus. The memory control circuit is integrated in an IP form, the test pattern is sent to the FPGA through a communication port by an upper computer, and the FPGA top-level control logic is responsible for loading the test vector.

A memory structure processed based on the TSV reconstruction stacking process is shown in fig. 2, in the TSV process stacked memory structure, a TSV silicon substrate 21 has a thickness of 200um, and the most important material is silicon; the height of the interlayer solder ball 22 is about 50um, and the main material is lead-tin alloy; the main material of the memory bare chip 23 embedded in the TSV substrate is silicon; the filling adhesive 24 between different silicon substrates is mainly made of epoxy material; TSV stack memory to PAD 25. According to the structure, the most main material of the stacked memory is silicon, and the silicon has high thermal conductivity, small height between silicon layers (typically 50um), epoxy filling glue and solder balls, so that the memory has small overall thermal resistance and uniform temperature distribution. The invention provides a method for heating the top surface and measuring the temperature of the bottom surface of the memory aiming at the thermal characteristics of the memory, the temperature of the central part of the bottom surface of the memory is taken as the integral working temperature of the memory, the temperature of the point is measured and taken as a temperature control parameter, and the heating power of a top surface heating element is controlled, so that the whole memory works in a certain temperature range and achieves higher temperature precision.

As shown in fig. 3, the TSV stacked memory aging test fixture structure of the invention includes a cover plate 1, a rotating handle 2, a thread 3, a pressing block 4, a heating rod 5, an electric wire 6, a high-temperature organic thin sheet 7, a device 8 to be tested, a pogo pin seat 9 and a pogo pin 10.

The top of the cover plate 1 is provided with a through hole, the through hole is provided with a thread 3, and the rotating handle 2 passes through the through hole to be in threaded connection with the cover plate 1; the bottom of the rotating handle 2 is connected with a pressing block 4, and a heating part is arranged inside the pressing block 4.

The bottom of the cover plate 1 is fixed on the spring needle seat 9 through a buckling structure, a spring needle 10 is arranged inside the spring needle seat 9, the bottom of the spring needle 10 is connected with a PCB 12, and the tested device 8 is electrically connected with the PCB 12 through the spring needle 10.

The heating part includes heating rod 5 and electric wire 6, and heating rod 5 sets up in the inside of briquetting 4, and heating rod 5 passes through electric wire 6 and connects power supply.

The up-and-down movement of the pressing block 4 is controlled by the rotating handle 2; the pressing block 4 is made of metal materials, usually a copper block, a heating rod 5 is embedded in the pressing block 4, and the heating rod 5 is electrified through an electric wire 6, so that the heating rod 5 generates heat; the LTCC substrate 5 is formed by sintering copper serving as a plurality of metal wiring layers at a low temperature; the bottom of the briquette 4 is provided with a high temperature organic sheet 7. The high-temperature organic sheet 7 plays a role in buffering the pressure of the pressing block to protect the tested device and stabilizing the temperature; the device 8 to be tested is placed on the spring needle seat 9, the spring needle seat 9 adopts a square structure, namely the center is hollowed out, so that the center of the bottom surface of the device to be tested is exposed, and the device 8 to be tested is electrically connected with the PCB 12 through the spring needle 10.

As shown in fig. 4, a burn-in test system for TSV reconfigurable stacked memories includes a test fixture 11, a PCB 12, and a driving circuit 20.

The test fixture 11 is fixed on the PCB 12, the test fixture 11 is used for clamping the device 8 to be tested, the device 8 to be tested is electrically connected with the PCB 12, and the top of the device 8 to be tested is provided with a heating device.

The bottom of the tested device 8 is provided with a temperature sensor 15, and the temperature sensor 15 is electrically connected with the PCB 12; the driving circuit 20 is disposed on the PCB board 12, and the circuit of the device under test 8 is electrically connected to the driving circuit 20.

In the aging system, the test fixture 11 is fixed with the PCB through a positioning pin, and is connected with a PCB power supply circuit through a connector 17 and a power supply cable 19; the PCB 12 is windowed at the center of the abdomen of the test fixture; the reinforcing plate 13 is connected to the PCB board 12 by screws 14; the temperature measuring sensor 15 is fixed inside the reinforcing plate 13 through a spring 16 and is electrically connected with the PCB 12 through an electric wire 18 and a connector 17; the driving circuit 20 is an FPGA and is placed at the center of the PCB board 12.

A temperature measuring circuit, a heating driving circuit, a temperature control MCU and the like are designed on the PCB 12, and the accurate control of each station is realized through a temperature control algorithm operated in the MCU. In addition, the MCU receives the instruction of the upper computer to complete the temperature setting and returns the current working temperature in real time. The temperature control method comprises the steps of heating through a top test fixture, sampling through a bottom temperature sensor and controlling the temperature based on the MCU.

A heating rod is embedded in a pressing block in the test fixture structure, an organic plate is sampled below the pressing block for transition, the center of the bottom of the socket is hollowed out, and a temperature sensor is embedded in a reinforcing plate; the FPGA on the aging plate structure is arranged in the middle, four test fixtures are distributed on the periphery of the aging plate structure, and the test fixture heating wire and the sensor wire are connected with the PCB through connectors.

In the invention, the driver and the tested circuit are arranged on the same PCB board nearby, so that the tested memory can be operated at the highest working speed, the combination of testing and aging is realized, and the dynamic aging in the true sense is realized.

The aging plate has compact structure, realizes aging with one driving four under the size of a single plate of about 200mm multiplied by 200mm, occupies small space and leads the aging to be more economical.

The aging box is separated from the operation, the scheme of local heating of the tested circuit is adopted, the temperature control is accurate, the energy consumption is low, the equipment dependence is low, other peripheral components and PCBs do not bear high-temperature environment, the selectable circuit requirement is low, the design is more universal, and the cost of the whole aging system is lower.

Claims

1. The aging test system for the TSV-oriented reconstruction stacked memory is characterized by comprising a test fixture (11), a PCB (12) and a driving circuit (20);

the testing fixture (11) is fixed on the PCB (12), the testing fixture (11) is used for clamping a tested device (8), the tested device (8) is electrically connected with the PCB (12), and a heating device is arranged at the top of the tested device (8);

the bottom of the tested device (8) is provided with a temperature sensor (15), and the temperature sensor (15) is electrically connected with the PCB (12); the driving circuit (20) is arranged on the PCB (12), and the circuit of the tested device (8) is electrically connected with the driving circuit (20).

2. The aging test system for the TSV reconfigurable stacked memory according to claim 1, wherein a through hole is formed in the center of the PCB (12) at the bottom of the test fixture (11), a reinforcing plate (13) is fixed to the bottom of the PCB (12), a groove is formed in the center of the reinforcing plate (13), a spring (16) is arranged inside the groove, and a temperature sensor (15) is arranged on the top of the spring (16).

3. The burn-in system for a TSV-oriented reconfigurable stacked memory as claimed in claim 1, wherein the stiffener plate (13) is fixed to the PCB board (12) by screws (14).

4. The TSV reconfigurable stacked memory-oriented burn-in test system of claim 1, wherein the temperature sensor (15) is electrically connected to the connector (17) by a wire (18), and the connector (17) is electrically connected to the PCB board (12).

5. The burn-in test system for a TSV reconfigurable stacked memory as claimed in claim 1, wherein the driving circuit (20) is an FPGA.

6. The burn-in test system for the TSV restructured stacked memory according to claim 1, wherein the driving circuit (20) is disposed in a central portion of the PCB (12), the number of the test fixtures (11) is four, and four arrays of the test fixtures (11) are disposed outside the driving circuit (20).

7. The TSV reconfigurable stacked memory-oriented burn-in test system of claim 1, wherein the test fixture (11) comprises a cover plate (1), a rotating handle (2), threads (3), a press block (4), a heating rod (5), wires (6), pogo pins seats (9), pogo pins (10);

the top of the cover plate (1) is provided with a through hole, a thread (3) is arranged on the through hole, and the rotating handle (2) penetrates through the through hole to be in threaded connection with the cover plate (1); the bottom of the rotating handle (2) is connected with a pressing block (4), and a heating component is arranged inside the pressing block (4);

a spring needle seat (9) is fixed at the bottom of the cover plate (1), a spring needle (10) is arranged inside the spring needle seat (9), the bottom of the spring needle (10) is connected with a PCB (printed circuit board) (12), and a tested device (8) is electrically connected with the PCB (12) through the spring needle (10).

8. The TSV reconfigurable stacked memory-oriented burn-in test system of claim 7, wherein the heating component comprises a heating rod (5) and an electric wire (6), the heating rod (5) is arranged inside the pressing block (4), and the heating rod (5) is connected with a power supply through the electric wire (6).

9. The burn-in test system for the TSV restructured stacked memory according to claim 7, wherein the bottom of the compact (4) is provided with a high temperature organic sheet (7).

10. The burn-in system for the TSV restructured stacked memory facing device according to claim 1, wherein the test fixture (11) is electrically connected to the connector (17) through a power cable (19), and the connector (17) is connected to a PCB power supply circuit.