CN114938243B - BOSA debugging method, system, debugger and debugging method - Google Patents

BOSA debugging method, system, debugger and debugging method Download PDF

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Publication number
CN114938243B
CN114938243B CN202210864508.0A CN202210864508A CN114938243B CN 114938243 B CN114938243 B CN 114938243B CN 202210864508 A CN202210864508 A CN 202210864508A CN 114938243 B CN114938243 B CN 114938243B
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bosa
adjusting
resistance
eye
state
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CN114938243A (en
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廖阳春
刘方亮
陈政
王周锋
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Shenzhen Yilian Unlimited Technology Co ltd
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Shenzhen Comnect Technology Co ltd
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B10/00Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/07Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
    • H04B10/073Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an out-of-service signal
    • H04B10/0731Testing or characterisation of optical devices, e.g. amplifiers
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G01R27/2605Measuring capacitance

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  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Debugging And Monitoring (AREA)

Abstract

A BOSA debugging method relates to the field of optical communication, and comprises the following steps: connecting the debugging instrument with the test computer and the BOSA respectively; connecting a tail fiber of the BOSA with an eye oscilloscope; the test computer sends out an instruction to enable the BOSA to emit light through the debugging instrument; an adjusting module of the debugging instrument is adjusted according to the state of the eye diagram, and when the eye diagram is in a normal state; stopping adjusting the adjusting module, and reading the resistance-capacitance value of the BOSA matched with the adjusting module; according to the method and the device, the peripheral resistance-capacitance value of the BOSA is matched through the eye pattern state, so that the eye pattern of the BOSA reaches the normal state, the matched resistance-capacitance value can be directly used for the application of the PCB, and is used as a reference standard, the complexity of debugging the peripheral resistance-capacitance matching of the BOSA is reduced, the workload of complexity and uncertainty is reduced, the determination of the direction of a debugging target is improved, and further the working efficiency is improved.

Description

BOSA debugging method, system, debugger and debugging method
Technical Field
The present application relates to the field of optical communications, and in particular, to a method, a system, a debugger, and a debugging method for debugging BOSA.
Background
With the popularization of optical fiber home, optical communication has been in progress in many families. The optical-to-electrical conversion device of optical communication, namely BOSA, is one of the indispensable components for realizing the electronic circuit, like the components of resistor, capacitor, triode and the like, and the BOSA has the particularity that the electrical parameters of the BOSA cannot be directly used like a resistor, the periphery of the BOSA needs to be matched with resistance-capacitance circuits, the signal eye diagram is subjected to optimization shaping to form a normal optical-to-electrical communication channel, if the BOSA is directly used, the generated signal eye diagram is abnormal, such as deformation, overshoot and jitter, even affects the optical communication, and is uncontrollable to users, so that research and development designers working in the optical communication field need to carry out parameter debugging and adjustment to the peripheral resistance-capacitance matching of the BOSA by maintenance personnel.
The debugging of the BOSA peripheral resistance-capacitance matching is a tedious work, the matching is irregular and can be followed, different machine types are matched differently, different BOSA manufacturers are matched differently, the resistor and the capacitor are required to be respectively debugged in the process, and the power-on is required to be repeatedly confirmed. Because the debugging BOSA peripheral resistance-capacitance matching is complex, the complexity and the uncertainty workload are increased in an intangible way, and the working efficiency is reduced.
Disclosure of Invention
Purpose of (one) application
In view of this, the purpose of the present application is to provide a method, a system, a debugger and a debugging method for debugging a BOSA, which are used for solving the technical problems of complicated matching of resistance and capacitance of the periphery of the debugger in the prior art, increased complexity and uncertainty workload, and reduced working efficiency.
(II) technical scheme
The application discloses a method for debugging BOSA, which comprises the following steps: s1, respectively connecting a debugging instrument with a test computer and a BOSA; connecting a tail fiber of the BOSA with an eye oscilloscope;
s2, the test computer sends out an instruction to enable the BOSA to emit light through the debugging instrument;
s3, adjusting an adjusting module of the debugger according to the state of the eye diagram, and when the eye diagram is in a normal state; stopping adjusting the adjusting module, and reading the resistance-capacitance value of the BOSA matched with the adjusting module.
In one possible implementation manner, the adjusting module of the adjusting and debugging instrument according to the state of the eye diagram includes:
s31, adjusting a first adjusting unit of the debugger to enable a first state of a normal state to meet the requirement;
s32, adjusting a second adjusting unit of the debugger to enable a second state of the normal state to meet the requirement, stopping adjusting and executing the step S33 when the second state meets the requirement, otherwise returning to the step S31;
s33, adjusting a third unit and a fourth unit of the debugger to enable the third state and the fourth state of the normal state to meet the requirements, stopping adjusting when the third state and the fourth state of the normal state meet the requirements, and otherwise, continuing executing the step.
As a second aspect of the present application, a system for debugging a BOSA is also disclosed, comprising a debugger, a test computer and an eye oscilloscope, the debugger being configured to test the computer and the BOSA respectively, the debugger being configured to adjust a resistance-capacitance value matching the BOSA; the test computer is connected with the debugging instrument and is used for sending out an instruction, and the instruction can enable the BOSA to emit light through the debugging instrument; the eye diagram oscilloscope is connected with the BOSA tail fiber and displays the eye diagram of the BOSA;
adjusting the resistance-capacitance value based on the eye diagram; and when the eye pattern is in a normal state, reading the resistance-capacitance value matched with the debugger.
In one possible implementation manner, the debugger comprises an adjusting module, wherein the adjusting module is used for matching the resistance-capacitance value of the BOSA, and the adjusting module comprises a first adjusting unit, a second adjusting unit, a third adjusting unit and a fourth adjusting unit, wherein the first adjusting unit is used for adjusting an eye pattern to enable a first state of a normal state to meet the requirement; the second adjusting unit is used for adjusting the eye pattern to enable a second state of the normal state to meet the requirement; the third adjusting unit is used for adjusting the eye diagram to enable the third state of the normal state to meet the requirement; the fourth adjusting unit is used for adjusting the eye diagram to enable the fourth state of the normal state to meet the requirement.
As a third aspect of the present application, a debug method for debugging a BOSA is also disclosed, including the steps of:
s100, respectively connecting with a BOSA and a test computer;
s200, receiving an instruction of a test computer to drive the BOSA, so that the BOSA emits light for a long time;
s300, receiving the adjustment operation of the resistance-capacitance value matched with the BOSA, so that the eye diagram of the BOSA is in a normal state.
In one possible implementation, the receiving the adjustment operation of the BOSA-matched resistance-capacitance value includes:
s301, receiving a first operation, and enabling a first state of a normal state of an eye diagram to meet requirements;
s302, receiving a second operation to enable the second state of the normal state of the eye diagram to meet the requirement, and executing S03 when the second state of the normal state of the eye diagram meets the requirement; otherwise, returning to step 301;
s303, receiving a third operation, and enabling a third state of a normal state of the eye diagram to meet the requirement;
s304, receiving a fourth operation to enable a fourth state of the normal state of the eye diagram to meet the requirement.
In one possible embodiment, the first operation includes adjusting a first regulator to adjust a resistance magnitude of a laser positive damping resistance; the second operation includes: the first part of the regulator is regulated to regulate the resistance of the laser negative electrode filter resistor and the second part of the regulator is regulated to regulate the capacitance of the laser negative electrode filter capacitor; the third operation includes adjusting a third regulator to adjust a resistance magnitude of the rising resistance; the fourth operation includes adjusting a fourth regulator to adjust a resistance magnitude of the falling resistance.
As a fourth aspect of the present application, there is also disclosed a debugger for debugging BOSA, comprising: the system comprises a control module, an adjusting module and a BOSA connecting module; the control module is used for receiving the instruction of the test computer and controlling the BOSA to emit light; the adjusting module is used for receiving the adjusting operation of the resistance-capacitance values matched with the BOSA, so that the eye diagram of the BOSA is in a normal state; the BOSA connection module is used for being connected with the BOSA to drive BOSA to emit light for a long time.
In one possible embodiment, the adjustment module comprises a first adjustment unit, a second adjustment unit, a third adjustment unit and a fourth adjustment unit, wherein the first adjustment unit is adapted to receive a first operation; the second adjusting unit is used for receiving a second operation; the third adjusting unit is used for receiving a third operation; the fourth adjusting unit is used for receiving a fourth operation.
In one possible embodiment, the first adjusting unit includes a laser positive damping resistor and a first adjuster for adjusting the resistance thereof; the second adjusting unit comprises a first adjusting part and a second adjusting part, wherein the first adjusting part comprises a laser negative electrode filter resistor and a first part adjuster for adjusting the resistance of the laser negative electrode filter resistor; the second adjusting part comprises a laser negative electrode filter capacitor and a second part adjusting part for adjusting the capacitance of the laser negative electrode filter capacitor; the third regulating unit comprises a rising resistor and a third regulator for regulating the resistance of the rising resistor; the fourth adjusting unit comprises a fourth regulator for reducing resistance and adjusting the resistance.
(III) beneficial effects
According to the method and the device, the peripheral resistance-capacitance value of the BOSA is matched through the eye pattern state, so that the eye pattern of the BOSA reaches the normal state, the matched resistance-capacitance value can be directly used for the application of the PCB, and is used as a reference standard, the complexity of debugging the peripheral resistance-capacitance matching of the BOSA is reduced, the workload of complexity and uncertainty is reduced, the determination of the direction of a debugging target is improved, and further the working efficiency is improved.
Additional advantages, objects, and features of the application will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the application. The objects and other advantages of the present application may be realized and attained by the written description which follows.
Drawings
The embodiments described below with reference to the drawings are exemplary and intended for the purpose of illustrating and explaining the present application and are not to be construed as limiting the scope of protection of the present application.
FIG. 1 is a system flow diagram of the present application;
FIG. 2 is a system block diagram of the present application;
FIG. 3 is a flow chart of a method for debugging a debugger of the present application;
FIG. 4 is a block diagram of a debugger of the present application;
FIG. 5 is a pin circuit connection diagram of a debugger and BOSA;
FIG. 6 is a block diagram of a debugger slide switch unit;
1, a debugging instrument; 2. testing a computer; 3. an eye diagram oscilloscope; 4. BOSA; 11. a control module; 12. an adjustment module; 13. a BOSA connection module; 14. and a measurement module.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the foregoing description of the present application, it should be noted that, the azimuth or positional relationship indicated by the terms "one side", "the other side", etc. are based on the azimuth or positional relationship shown in the drawings, or the azimuth or positional relationship that is commonly put when the product of the application is used, are merely for convenience of description and simplification of the description, and are not indicative or implying that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and therefore should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.
As shown in fig. 1, the present embodiment provides a method for debugging a BOSA, including the following steps: s1, respectively connecting a debugging instrument with a test computer and a BOSA; connecting a tail fiber of the BOSA with an eye oscilloscope;
s2, the test computer sends out an instruction to enable the BOSA to emit light through the debugging instrument; the BOSA (laser diode) is driven to emit light through the debugger, and the initial values of the long-term luminescence and the flash memory are read and call relations and are displayed on the 86100 oscilloscope. The initial value is just like a data optical disc, and the BOSA long-light reading initial value is presented to an eye oscilloscope through UX3320, RTL9601 and BOSA processing and exchanging data.
S3, adjusting an adjusting module of the debugger according to the state of the eye diagram, and when the eye diagram is in a normal state; stopping adjusting the adjusting module, and reading the resistance-capacitance value of the BOSA matched with the adjusting module. The normal state comprises a first state, a second state, a third state and a fourth state, and the normal state of the eye diagram is only when the first state, the second state, the third state and the fourth state meet the requirements. The first state is required that the eye pattern reaches 1 level and 0 level which are 0.5mm away from the template datum line, and the eye pattern does not touch the template, namely the index is reached: ER (11-14 dB), RMS (less than 14 PS), J P-P (less than 90 PS). The second state is required to have an eye jitter (RMS) of not more than 14PS and no distortion of the pattern of the eye, and to have no double eye line of the pattern of the displayed eye. The third state may require that the rise time of the eye diagram be less than 280PS. The fourth state requires that the eye drop time be less than 280PS. The adjusting module of the adjusting and debugging instrument according to the state of the eye diagram comprises: s31, a first adjusting unit of the debugging instrument is adjusted, no matter what state an eye diagram is in, the first adjusting unit of the debugging instrument can be adjusted at first, but 1 level cannot be propped against a datum line above a template, 0 level cannot touch a datum line below the template, and an eye line waveform cannot be pressed to a template eyeball after ascending and descending in the middle. In general, when the eye pattern 1 level and the eye pattern 0 level are relatively flat and short, at the moment, a first adjusting unit of the adjusting and debugging instrument increases the resistance of the access BOSA, and when the eye pattern 1 level and the eye pattern 0 level are approximately 0.5mm away from the template datum line, the resistance of the access BOSA is stopped from increasing, namely the access to the template datum line is ensured not to be touched; when the eye pattern 1 level and the eye pattern 0 level meet the template datum line, the resistance of the accessed BOSA is reduced; stopping adjusting when the distance from the template datum line is about 0.5mm, and ensuring that the middle orbit waveform does not touch the eyeball of the template. S32, adjusting a second adjusting unit of the debugger to enable a second state of the normal state to meet the requirement, stopping adjusting and executing the step S33 when the second state meets the requirement, otherwise returning to the step S31; the normal eye pattern signal 1 level does not touch the upper template datum line, the normal eye pattern signal 0 level does not touch the lower template datum line, the middle orbit waveform does not touch the template eyeball, and when the eye pattern shakes(RMS) large (over 14 PS), then turn up or down the resistance, when the eye pattern has distortion, or shows a double eye line, then turn up or down the capacitance; when the displayed poor eye pattern is waveform distortion or disorder, the jitter RMS exceeds 14PS by a certain value, the process returns to step S31. S33, adjusting a third unit and a fourth unit of the debugger to enable a third state and a fourth state of the normal state to meet the requirements, stopping adjusting when the third state and the fourth state of the normal state meet the requirements, otherwise, continuing executing the step; when the rising time and the falling time of the eye diagram are far beyond 280PS, such as 350PS, 400PS and the like, the step of adjusting is carried out, two resistors are adjusted without capacitance adjustment, one resistor adjusts the rising time and one resistor adjusts the falling time, the step of adjusting is carried out in S33, and whether the rising time and the falling time of the eye diagram are smaller than 280PS or not is checked through filtering of an eye diagram oscilloscope; if not, continuing to execute the rising time and the falling time of the eye pattern, and stopping adjusting when the rising time and the falling time are smaller than 280PS.
According to the method and the device, the peripheral resistance-capacitance value of the BOSA is matched through the eye pattern state, so that the eye pattern of the BOSA reaches the normal state, the matched resistance-capacitance value can be directly used for the peripheral resistance-capacitance value matching application of the BOSA on the PCB, and the peripheral resistance-capacitance value is used as a reference standard, so that complexity in debugging the peripheral resistance-capacitance matching of the BOSA is reduced, the workload of complexity and uncertainty is reduced, the determination degree of a debugging target direction is improved, and further the working efficiency is improved.
As shown in fig. 2, as a second aspect of the present application, a system for debugging a BOSA is also disclosed, including a debugger 1, a test computer 2 and an eye oscilloscope 3, where the debugger is used for respectively connecting the test computer and the BOSA4, and the debugger is used for adjusting a resistance-capacitance value matched with the BOSA; the test computer is connected with the debugging instrument and is used for sending out an instruction, and the instruction can enable the BOSA to emit light through the debugging instrument; the eye diagram oscilloscope is connected with the BOSA tail fiber and displays the eye diagram of the BOSA; adjusting the resistance-capacitance value based on the eye diagram; and when the eye pattern is in a normal state, reading the resistance-capacitance value matched with the debugger.
In this embodiment, the debugger includes an adjusting module, where the adjusting module is used for matchingThe adjusting module comprises a first adjusting unit, a second adjusting unit, a third adjusting unit and a fourth adjusting unit, wherein the first adjusting unit is used for adjusting an eye pattern to reach 1 level and 0 level, and is away from a template datum line by 0.5mm, and the eye pattern is not touched, namely an index is reached: ER (11-14 dB), RMS (less than 14 PS), J P-P (less than 90 PS); the second adjusting unit is used for adjusting the eye diagram jitter (RMS) to be not more than 14PS, the graph of the eye diagram is free from distortion, and the graph of the displayed eye diagram is free from double eye lines; the third adjusting unit is used for adjusting the rising time of the eye pattern to be less than 280PS; the fourth adjustment unit is used for eye diagram falling time less than 280PS.
As shown in fig. 3, as a third aspect of the present application, a debug method for debugging a BOSA is also disclosed, including the steps of:
s100, respectively connecting with a BOSA and a test computer;
s200, receiving an instruction of a test computer to drive the BOSA, so that the BOSA emits light for a long time;
s300, receiving the adjustment operation of the resistance-capacitance value matched with the BOSA, so that the eye diagram of the BOSA is in a normal state.
After S100 is completed, the power supply is connected, the current range is 1-2.5A, and the voltage is 4.5-18V.
Before step S300, a driver and its initial values are loaded, where the initial values include the initial values of BOSA, UX3320 for driving BOSA, and its peripheral circuits, and after loading, the driver and the peripheral circuits can be in a standby debug state.
In this implementation, the receiving the adjustment operation for the BOSA-matched resistance-capacitance value includes: s301, receiving a first operation to enable a first state of a normal state of an eye diagram to meet requirements, wherein the first state is to be
The eye pattern is calculated to reach 1 level and 0 level which are 0.5mm away from the template datum line, and the eye pattern is not touched with the template, namely the index is reached: ER (11-14 dB), RMS (less than 14 PS), JP-P (less than 90 PS).
S302, receiving a second operation to enable a second state of a normal state of the eye diagram to meet the requirement, wherein the second state of the eye diagram is required to enable the eye diagram jitter (RMS) to be not more than 14PS and the graph of the eye diagram to be free of distortion, and the displayed graph of the eye diagram is free of double eye lines, and executing S03 when the second state of the normal state of the eye diagram meets the requirement; otherwise, when the displayed poor eye pattern is waveform distortion or disorder, the jitter RMS exceeds 14PS by a certain value, the process returns to step 301.
S303, receiving a third operation, enabling the third state of the normal state of the eye diagram to meet the requirement, checking whether the rising time of the eye diagram is smaller than 280PS through filtering of the eye diagram oscilloscope, stopping adjusting when the rising time is smaller than 280PS, and otherwise, continuing to execute S303.
S304, receiving a fourth operation, enabling the fourth state of the normal state of the eye diagram to meet the requirement, checking whether the falling time of the eye diagram is smaller than 280PS or not through filtering of the eye diagram oscilloscope, stopping adjusting if the falling time is smaller than 280PS, and otherwise, continuing to execute S304.
The first operation comprises the steps of adjusting a first adjuster to adjust the resistance of the laser positive electrode damping resistor; the second operation includes: the first part of the regulator is regulated to regulate the resistance of the laser negative electrode filter resistor and the second part of the regulator is regulated to regulate the capacitance of the laser negative electrode filter capacitor; the third operation includes adjusting a resistance magnitude of the third regulator to adjust a rising resistance and adjusting a resistance magnitude of the fourth regulator to adjust a falling resistance. The first adjusting unit comprises a laser positive electrode damping resistor (LD+R resistor) and a first adjuster for adjusting the resistance of the first adjuster, wherein the laser positive electrode damping resistor (LD+R resistor) is connected with a T4 pin in the BOSA; the second adjusting unit comprises a first adjusting part and a second adjusting part, the first adjusting part comprises a laser negative electrode filter resistor (LD-R resistor) and a first part adjuster for adjusting the resistance, wherein the positive electrode of the laser negative electrode filter resistor (LD-R resistor) is connected with a T2 pin in the BOSA, and the negative electrode is connected with the LD-C positive electrode; the second adjusting part comprises a laser negative electrode filter capacitor (LD-C adjustable capacitor) and a second part adjusting part for adjusting the size of the capacitor, wherein the anode of the laser negative electrode filter capacitor (LD-C adjustable capacitor) is connected with an LD-C pin, the negative electrode is grounded, and the laser negative electrode filter capacitor (LD-C adjustable capacitor) is connected in series with a laser negative electrode filter resistor (LD-R resistor); the third regulating unit comprises a rising resistor (Rise resistor) and a third regulator for regulating the resistance of the rising resistor (Rise resistor); the fourth adjusting unit includes a falling resistance (Fall resistance) and a fourth regulator adjusting a resistance thereof.
As shown in fig. 4-6, as a fourth aspect of the present application, there is also disclosed a debug apparatus for debugging BOSA, comprising: a control module 11, an adjustment module 12 and a BOSA connection module 13; the control module is used for receiving the instruction of the test computer and controlling the BOSA to emit light; the adjusting module is used for receiving the adjusting operation of the resistance-capacitance values matched with the BOSA, so that the eye diagram of the BOSA is in a normal state; the BOSA connection module is used for being connected with the BOSA to drive BOSA to emit light for a long time.
In this embodiment, the adjusting module includes a first adjusting unit, a second adjusting unit, a third adjusting unit, and a fourth adjusting unit, where the first adjusting unit is configured to receive a first operation, adjust an eye diagram to make a first state of a normal state of the eye diagram meet a requirement, make the eye diagram reach 1 level and 0 level 0.5mm from a template datum line, not touch the template, and reach an index: ER (11-14 dB), RMS (less than 14 PS), J P-P (less than 90 PS); the second adjusting unit is used for receiving a second operation, adjusting the eye diagram to enable the second state of the normal state of the eye diagram to meet the requirement, enabling the eye diagram jitter (RMS) not to exceed 14PS and the graph of the eye diagram to be free from distortion, and enabling the displayed graph of the eye diagram to be free from double eye lines; the third adjusting unit is used for receiving a third operation and adjusting the eye diagram to enable the third state of the normal state of the eye diagram to meet the requirement, and the rising time of the eye diagram is smaller than 280PS; the fourth adjusting unit is used for receiving a fourth operation and adjusting the eye diagram to enable the fourth state of the normal state of the eye diagram to meet the requirement, and the falling time of the eye diagram is smaller than 280PS.
In this embodiment, the first adjusting unit includes a laser positive damping resistor (ld+r resistor) and a first adjuster for adjusting the resistance thereof, where the laser positive damping resistor (ld+r resistor) is connected to a T4 pin in the BOSA; the second adjusting unit comprises a first adjusting part and a second adjusting part, the first adjusting part comprises a laser negative electrode filter resistor (LD-R resistor) and a first part adjuster for adjusting the resistance, wherein the positive electrode of the laser negative electrode filter resistor (LD-R resistor) is connected with a T2 pin in the BOSA, and the negative electrode is connected with the LD-C; the second adjusting part comprises a laser negative electrode filter capacitor (LD-C adjustable capacitor) and a second part adjusting part for adjusting the capacity of the second adjusting part, wherein the anode of the laser negative electrode filter capacitor (LD-C adjustable capacitor) is connected with an LD-R negative electrode pin, the negative electrode is grounded, and the laser negative electrode filter capacitor (LD-C adjustable capacitor) is connected in series with a laser negative electrode filter resistor (LD-R resistor); the third regulating unit comprises a rising resistor (Rise resistor) and a third regulator for regulating the resistance of the rising resistor (Rise resistor); the fourth adjusting unit includes a falling resistance (Fall resistance) and a fourth regulator adjusting a resistance thereof.
Since BOSA is a component, its factory parameters are produced according to a certain standard, individual differences are negligible to the designer using it, and after ignoring these differences, it can be regarded as a constant, a standard; the BOSA device is finally placed in a circuit and placed on a PCB of a light cat, the PCB is provided with an impedance control requirement, generally 100 ohms or 90 ohms, when the PCB is manufactured, the difference between the models of the BOSA device and the PCB can be ignored for a designer, and the model PCB can be regarded as a constant; furthermore, there are several driver ICs of BOSA, such as GN25L95 of the forest, EN7571 of the MTK, etc., which drive ICs push the difference of the BOSA eye pattern signals to be small and negligible based on the specification of the BOSA, and the driver ICs can be regarded as a constant. Therefore, the debugging of BOSA resistance-capacitance matching can be independently listed to form a debugging instrument, then the resistance-capacitance matching is firstly debugged and matched on the debugging instrument, the debugging accords with the resistance-capacitance value of a normal eye pattern signal, and finally the resistance-capacitance values are made on an actual model circuit and a PCB. Compared with the actual value debugged in a certain model, the matching resistance-capacitance value obtained by the debugger has the difference of 1-3 ohms and the difference of 1-2 PF, can be used as a reference when designing the matching resistance of the BOSA, and even if the difference of the resistance-capacitance values is not counted, the obtained matching resistance-capacitance value is directly placed in the actual model, the waveform of the BOSA eye diagram is not severely distorted, and the obtained eye diagram is basically in a normal range.
In this embodiment, the debug apparatus further includes a measurement module 14, where the measurement module is configured to measure a peripheral resistance-capacitance value of the BOSA when an eye diagram of the BOSA is in a normal state, and the measurement module includes an MCU and an LCD reading unit and a sliding switch unit, where the sliding switch unit is in parallel connection with the MCU in the MCU and the LCD reading unit, as in fig. 6, a sliding switch negative electrode is connected to COM, a positive electrode is connected to V-OHM-CAP, a V-OHM-CAP PIN is connected to an MCU S4 (PIN 21 PIN 23), the COM is commonly connected to the MCU, S4 PIN21 is connected to an MCU capacitance detection PIN, S4 PIN23 is connected to an MCU resistance detection PIN, and the sliding switch unit is configured to connect one of a laser positive electrode damping resistor, a laser negative electrode filtering capacitor, a rising resistor, and a falling resistor to the MCU and the LCD reading unit, where the MCU and the LCD reading unit are configured to measure a resistance value of the resistor or a capacitance value of the capacitor and display a specific resistance value and capacitance value of the capacitor through an LCD display screen; when the sliding switch unit slides to a preset position, namely, the MCU and the LCD reading unit are connected with a resistor or a capacitor corresponding to the position connection, the MCU and the LCD reading unit have the resistance value of the resistor or the capacitance value of the capacitor. The resistance value of the resistor and the capacitance value of the capacitor read by the MCU and the LCD reading unit are effective values between the positive end and the negative end, and in the figure, the SW2 position is a vacancy, which indicates that the MCU and the LCD reading unit cannot be connected, namely the MCU and the LCD reading unit cannot be connected with one of the laser positive damping resistor, the laser negative filtering capacitor, the rising resistor and the falling resistor, so that the influence of the peripheral circuit of the resistor of the MCU and the LCD reading unit connected to the BOSA on the regulation of the peripheral resistance-capacitance value of the BOSA is avoided, and the accuracy of the peripheral resistance-capacitance value reading is reduced.
In this embodiment, the debugger further includes a power module, where the power module is configured to supply power to the debugger itself and supply power to the BOSA, and in this embodiment, the power module is converted from two DCDCs into 3.3V and 1.15V to provide continuous working energy for the debugger; the DCDC has overvoltage and overcurrent protection capability, and can provide a current range of 1-2.5A and a voltage of 4.5-18V.
In this embodiment, the debugger further includes a flash memory module, where the flash memory module is used to store a driver, where the driver is used to drive the debugger and the BOSA to operate, that is, the driver needs to be embedded into the flash memory module, and in an initialization stage of the debugger, the driver, the UX3320 including the BOSA and the driving BOSA, and initial values of peripheral circuits thereof begin to be loaded, and after loading is completed, the debugger can be in a standby debug state, and at this time, an eye diagram can begin to be debugged.
Finally, it is noted that the above embodiments are only for illustrating the technical solution of the present application and not for limiting the same, and although the present application has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solution of the present application may be modified or substituted without departing from the spirit and scope of the technical solution of the present application, and all such modifications are intended to be encompassed within the scope of the claims of the present application.

Claims (2)

1. The method for debugging the BOSA is characterized by comprising the following steps of:
s1, respectively connecting a debugging instrument with a test computer and a BOSA; connecting a tail fiber of the BOSA with an eye oscilloscope;
s2, the test computer sends out an instruction to enable the BOSA to emit light through the debugging instrument;
s3, adjusting an adjusting module of the debugger according to the state of the eye diagram, and when the eye diagram is in a normal state; stopping adjusting the adjusting module, and reading the resistance-capacitance value of the BOSA matched by the adjusting module, wherein the read resistance-capacitance value is used for peripheral resistance-capacitance value matching application of the BOSA on the PCB; the adjusting module of the adjusting and debugging instrument according to the state of the eye diagram comprises: s31, adjusting a first adjusting unit of the debugging instrument, when the eye pattern 1 level and the 0 level are short, the first adjusting unit of the adjusting debugging instrument increases the resistance of the access BOSA, and when the 1 level and the 0 level are 0.5mm away from the template datum line, the resistance of the access BOSA is stopped from increasing, and the template datum line is not touched; when the eye pattern 1 level and the eye pattern 0 level meet the template datum line, the resistance of the accessed BOSA is reduced; stopping resistance reduction when 0.5mm from the template datum line; s32, adjusting a second adjusting unit of the debugger to enable a second state of the normal state to meet the requirement, stopping adjusting and executing the step S33 when the second state meets the requirement, otherwise returning to the step S31; when the eye diagram jitter exceeds 14PS, the resistance is turned up or turned down, and when the eye diagram has distortion or displays double eye lines, the capacitance is turned up or turned down; returning to the step S31 when the displayed eye pattern waveform is distorted, disordered and jittered RMS exceeds 14PS by a certain value; s33, adjusting a third unit and a fourth unit of the debugger to enable a third state and a fourth state of the normal state to meet the requirements, stopping adjusting when the third state and the fourth state of the normal state meet the requirements, otherwise, continuing executing the step; when the rising time and the falling time of the eye diagram are larger than 350PS, adjusting two resistors, wherein the two resistors comprise a resistor, the rising time and the falling time are adjusted, and judging whether the rising time and the falling time of the eye diagram are smaller than 280PS or not through filtering of an eye diagram oscilloscope; if not, continuing to execute the rising time and the falling time of the eye pattern, and stopping adjusting when the rising time and the falling time are smaller than 280PS.
2. The system for debugging the BOSA is characterized by comprising a debugging instrument, a test computer and an eye diagram oscilloscope, wherein the debugging instrument is used for being connected with the test computer and the BOSA respectively; the eye diagram oscilloscope is used for being connected with the tail fiber of the BOSA, and the debugger is used for adjusting the resistance-capacitance value matched with the BOSA; the test computer is connected with the debugging instrument and is used for sending out an instruction, and the instruction can enable the BOSA to emit light through the debugging instrument; the eye diagram oscilloscope is connected with the BOSA tail fiber and displays the eye diagram of the BOSA;
adjusting the resistance-capacitance value based on the eye diagram; when the eye pattern is in a normal state, reading the resistance-capacitance value matched by the debugger, wherein the read resistance-capacitance value is used for peripheral resistance-capacitance value matching application of the BOSA on the PCB; said adjusting said resistance-capacitance value based on said eye pattern comprises performing the steps of: s31, adjusting a first adjusting unit of the debugging instrument, when the eye pattern 1 level and the 0 level are short, the first adjusting unit of the adjusting debugging instrument increases the resistance of the access BOSA, and when the 1 level and the 0 level are 0.5mm away from the template datum line, the resistance of the access BOSA is stopped from increasing, and the template datum line is not touched; when the eye pattern 1 level and the eye pattern 0 level meet the template datum line, the resistance of the accessed BOSA is reduced; when the resistance is reduced by 0.5mm from the template datum line, the middle orbit waveform does not touch the template eyeball; s32, adjusting a second adjusting unit of the debugger to enable a second state of the normal state to meet the requirement, stopping adjusting and executing the step S33 when the second state meets the requirement, otherwise returning to the step S31; when the eye diagram jitter exceeds 14PS, the resistance is turned up or turned down, and when the eye diagram has distortion or displays double eye lines, the capacitance is turned up or turned down; when the displayed poor eye pattern is waveform distortion, disorder and jitter RMS exceeds 14PS by a certain value, returning to step S31; s33, adjusting a third unit and a fourth unit of the debugger to enable a third state and a fourth state of the normal state to meet the requirements, stopping adjusting when the third state and the fourth state of the normal state meet the requirements, otherwise, continuing executing the step; when the rising time and the falling time of the eye diagram are larger than 350PS, adjusting two resistors, wherein the two resistors comprise a resistor, the rising time and the falling time are adjusted, and judging whether the rising time and the falling time of the eye diagram are smaller than 280PS or not through filtering of an eye diagram oscilloscope; if not, continuing to execute the rising time and the falling time of the eye pattern, and stopping adjusting when the rising time and the falling time are smaller than 280PS.
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