CN114928747A - Context probability processing circuit and method based on AV1 entropy coding and related device - Google Patents
Context probability processing circuit and method based on AV1 entropy coding and related device Download PDFInfo
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- 238000012545 processing Methods 0.000 title claims abstract description 158
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Abstract
One or more embodiments of the present specification disclose a context probability processing circuit, method and related apparatus based on AV1 entropy coding, the scheme includes: the second probability processing engine for independently processing the second type of coding syntax elements meeting the preset coefficient type condition is added in the original context probability processing circuit, so that the coding syntax elements of different types can be processed in parallel with the original first probability processing engine, the probability calculation speed is increased, and the coding efficiency is improved. Moreover, the second probability processing engine uniformly stores the probabilities of the second type of coded syntax elements in the second probability storage, and the probabilities of the second type of coded syntax elements and the probabilities of the first type of coded syntax elements are not required to be stored in a same storage, so that the waste of storage space is avoided, and the storage space is reasonably utilized.
Description
Technical Field
The present invention relates to the field of image coding technologies, and in particular, to a context probability processing circuit and method based on AV1 entropy coding, and a related apparatus.
Background
Entropy coding, i.e. coding without losing any effective information according to the principle of entropy in the coding process. Common entropy coding methods are: shannon coding, huffman coding and arithmetic coding.
AV1 is an Open source video compression format developed by the Open Media Alliance (AOM) and is commonly used in the current coding field. In the AV1 coding standard, the coding result of the image is determined through the selection and decision of the previous-stage intra-frame mode and the inter-frame mode, and then the entropy coding stage is entered; in the entropy coding stage, the probability distribution of each type of coding syntax element in input data needs to be determined, and then arithmetic coding is performed according to the probability distribution to obtain the simplest code stream.
In the existing entropy coding stage, the probabilities of various types of coding syntax elements can be calculated and counted in a context probability mode, wherein all coding syntax elements need to be executed sequentially in the probability calculation process, so that when the number of generated coding syntax elements is large under a certain image, the time consumption for calculating the probabilities of the coding syntax elements is large, and the processing speed is low.
Disclosure of Invention
An object of one or more embodiments of the present specification is to provide a context probability processing circuit, a context probability processing method, and a related apparatus for entropy encoding based on AV1, so as to add a second probability processing engine to the context probability processing circuit, so as to perform probability calculation for a second type of encoded syntax element that satisfies a predetermined coefficient type condition in the encoded syntax element, thereby implementing parallel processing of the encoded syntax element in the context probability processing circuit, and increasing the probability calculation speed, thereby increasing the encoding efficiency.
To solve the above technical problem, one or more embodiments of the present specification are implemented as follows:
in a first aspect, a context probability processing circuit based on AV1 entropy coding is proposed, including: the system comprises an encoding result memory for storing preceding-stage encoding results of different blocks of a target image, a control state machine, a first buffer and a second buffer, a first probability processing engine, a second probability processing engine, a first probability memory and a second probability memory; wherein,
the control state machine is used for reading the preceding-stage coding result of each block from the coding result storage, generating a plurality of coding syntax elements which are sequentially arranged according to the coding standard determined by the preceding-stage coding result, sequentially judging whether the coding syntax elements meet the preset coefficient condition, if not, sending the coding syntax elements as the first-type coding syntax elements to the first buffer for caching, and if so, sending the coding syntax elements as the second-type coding syntax elements to the second buffer for caching;
the first probability processing engine is used for sequentially extracting the cached first type of coding syntax elements from the first cache and sequentially updating the probability of the first type of coding syntax elements in the first probability memory;
and the second probability processing engine is used for sequentially extracting the cached second type coding syntax elements from the second cache and sequentially updating the probability of the second type coding syntax elements in the second probability memory.
In a second aspect, a context probability processing method based on AV1 entropy coding is proposed, which is applied to the context probability processing circuit based on AV1 entropy coding in the first aspect; the method comprises the following steps:
the control state machine reads a preceding-stage coding result of each block from the coding result storage, generates a plurality of coding syntax elements which are sequentially arranged according to a coding standard determined by the preceding-stage coding result, and sequentially judges whether the coding syntax elements meet preset coefficient type conditions, if not, the coding syntax elements are sent to a first buffer for caching as first-type coding syntax elements, and if so, the coding syntax elements are sent to a second buffer for caching as second-type coding syntax elements;
the first probability processing engine sequentially extracts the cached first type of coding syntax elements from the first cache and sequentially updates the probability of the first type of coding syntax elements in the first probability storage;
and the second probability processing engine sequentially extracts the cached second-type coding syntax elements from the second cache and sequentially updates the probability of the second-type coding syntax elements in the second probability memory.
In a third aspect, an image encoding apparatus is provided, including: the context probability processing circuit based on AV1 entropy coding of the first aspect.
In a fourth aspect, a chip is provided, where the chip includes the context probability processing circuit based on AV1 entropy coding according to the first aspect, or the image encoding apparatus according to the third aspect.
As can be seen from the above technical solutions provided by one or more embodiments of the present specification, a second probability processing engine is added in the context probability processing circuit to perform probability calculation on a second type of coded syntax elements that satisfy a preset coefficient type condition in the coded syntax elements, so that parallel processing of the coded syntax elements is implemented in the context probability processing circuit, and a second type of coded syntax elements whose probability speed tends to be stable can be continuously processed by a continuous address acceleration engine inside the second probability processing engine, and further, the processing speed of one path of coded syntax elements is increased on the basis of the parallel processing, so that the processing speed of the entire context probability processing circuit can be further increased, and the coding efficiency is increased. Moreover, the second probability processing engine uniformly stores the probability of the second type of coding syntax element on the distributed second probability storage, and does not need to store the probability of other coding syntax elements with more than 4 symbols in a storage together, thereby avoiding the waste of storage space, reasonably utilizing the storage space, and being convenient and fast to access.
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In order to more clearly illustrate one or more embodiments or prior art solutions of the present specification, reference will now be made briefly to the attached drawings, which are used in the description of one or more embodiments or prior art, and it should be apparent that the drawings in the description below are only some of the embodiments described in the specification, and that other drawings may be obtained by those skilled in the art without inventive effort.
Fig. 1 is a schematic structural diagram of a context probability processing circuit based on AV1 entropy coding according to an embodiment of the present specification;
fig. 2 is a schematic structural diagram of a branch where a second probability processing engine is located according to an embodiment of the present specification;
FIG. 3 is a schematic circuit diagram of a branch in which a second probability processing engine is located according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram of a step of a context probability processing method based on AV1 entropy coding according to an embodiment of the present specification;
fig. 5 is a second schematic diagram illustrating the steps of a context probability processing method based on AV1 entropy coding according to an embodiment of the present disclosure;
FIG. 6 is a general computer architecture diagram to which embodiments of the present description may be applied.
Detailed Description
In order to make the technical solutions in the present specification better understood, the technical solutions in one or more embodiments of the present specification will be clearly and completely described below with reference to the accompanying drawings in one or more embodiments of the present specification, and it is obvious that the one or more embodiments described are only a part of the embodiments of the present specification, and not all embodiments. All other embodiments that can be derived by a person skilled in the art from one or more of the embodiments described herein without making any inventive step shall fall within the scope of protection of this document.
Image coding, also called image compression, refers to a technique of representing an image or information included in an image with a small number of bits under a condition that a certain quality (for example, a signal-to-noise ratio requirement, a subjective evaluation score, or the like) is satisfied. AV1 is an encoding standard for image encoding, and employs multi-symbol entropy encoding to increase the parallelism of bits, support up to 16 symbols, and encode multiple bits simultaneously.
The context probability processing circuit can comprise an encoding result memory (RAM) for storing pre-stage decision and quantized information of different blocks of the target image, a control state machine, a first-in first-out buffer (FIFO), a first probability processing engine and a first probability memory (CDF RAM); the preceding-stage module divides the target image into blocks and encodes different blocks by adopting a set encoding standard to obtain a preceding-stage encoding result. The decision information and the quantized information in the preceding-stage coding result are stored in the RAM, under the triggering of a starting signal of the module, the state machine is controlled to read data from the RAM, the decision result of each block is analyzed, and coding syntax elements are generated according to a coding standard and a set sequence; thereafter, storing the generated coded syntax elements in a FIFO; the first probability processing engine reads the coding syntax elements from the FIFO, reads corresponding probabilities from the CDF RAM according to the types of the coding syntax elements, calculates the generated new probabilities, and generates new data to write into the CDF RAM. If too many syntax elements are generated under the target picture, and sequential execution is required for the same type of syntax elements, the processing speed of the whole coding is affected, and the computation logic is complex.
Therefore, the embodiments of the present disclosure provide a context probability processing circuit based on AV1 entropy coding, in which a coefficient processing engine (also referred to as a second probability processing engine) for separately processing encoded syntax elements satisfying a preset coefficient class condition is added to an original context probability processing circuit, so that different types of encoded syntax elements can be processed in parallel with an original first probability processing engine, thereby increasing a probability calculation speed and further increasing an encoding efficiency.
Referring to fig. 1, a schematic structural diagram of a context probability processing circuit based on AV1 entropy coding provided for an embodiment of this specification, the context probability processing circuit may include: an encoding result memory 102 for storing previous-stage encoding results of different blocks of the target image, a control state machine 104, a first buffer 106 and a second buffer 108, a first probability processing engine 110, a second probability processing engine 112, and a first probability memory 114 and a second probability memory 116.
It should be understood that, in the embodiment of the present specification, the context probability processing circuit in AV 1-based entropy coding commonly used may be implemented in a Field Programmable Gate Array (FPGA), where the arithmetic coding may be implemented in a CPU or in the FPGA, which is not limited herein. It should be noted that, if arithmetic coding is implemented in FPGA, there is a problem of resource preemption with context probability calculation, which will have a certain influence on coding speed. Thus, for the case where arithmetic coding is implemented in an FPGA, the context probability processing scheme provided in this specification can be used to mitigate the impact on coding speed, in particular.
The encoding result stored in the encoding result memory 102 contains coefficient information related to pixel information of each block and inter-block information between the block and other blocks. Since the coefficient information is of a large variety, the generated coded syntax elements are of a large variety and number.
The control state machine 104 reads the coding result of each block from the coding result storage 102, generates a plurality of coding syntax elements arranged in sequence (refer to sequence marks such as S1, S2, S3 and the like listed in fig. 1) according to the coding standard determined by the coding result, and sequentially judges whether the coding syntax elements meet preset coefficient class conditions, if not, the coding syntax elements are sent to the first buffer 106 as the coding syntax elements of the first class for buffering, and if so, the coding syntax elements are sent to the second buffer 108 as the coding syntax elements of the second class for buffering.
The control state machine 104 may read the coefficient information and inter-block information of each block, analyze the coding standard from the decision information and quantization information, and sequentially generate a plurality of coded syntax elements based on the coding standard and the content of the decision information and quantization information.
In this embodiment of the present specification, a coding syntax element (syntax elements) refers to data that needs to be entropy-coded and is generated after pre-processing by a previous stage, and specifically may include: coeff _ base, coeff _ base _ eob, coeff _ br, dc _ sign and the like, wherein the coeff _ base represents a coefficient base level; coeff base eob is a syntax element used to calculate the last non-zero coefficient of the coefficient base level coeff base; coeff _ br represents a coefficient increment.
For images with high granularity or with particularly many details, the ratio of coding syntax elements generated corresponding to the coefficient information is often more than half, so that the number of coding syntax elements generated by the coefficient part in the coding syntax elements generated by the control state machine 104 is more, and considering that the number of symbols occupied by the coding syntax elements generated by the coefficient part may be 4, but less than 16, the storage space may be wasted. Therefore, the embodiments of the present disclosure may set the preset coefficient class condition, and send the coded syntax elements that satisfy different conditions to different engines for processing, so as to implement parallel processing of different types of coded syntax elements at the same time.
In a specific implementation, the control state machine 104 may sequentially determine whether the coded syntax element belongs to a preset coefficient type; and the occupation ratio of the coding syntax elements corresponding to the preset coefficient type exceeds a threshold value, and the coding syntax elements corresponding to the preset coefficient type are coded by adopting a set number of symbols. That is, the preset coefficient type condition may be to determine whether the coding syntax element belongs to a preset coefficient type, where the coding syntax element corresponding to the preset coefficient type simultaneously satisfies two conditions: the occupancy exceeds a threshold; and supporting the encoding of a set number of symbols. Alternatively, the preset coefficient condition may be: the ratio exceeds the threshold and supports a set number of symbol codes. The ratio exceeding the threshold value can be that the ratio exceeds half of the total number or other set value range; the symbol coding supporting the set number can be the coding supporting 4 symbols, so that excessive storage space is not required to be occupied during storage, especially, the coding syntax elements are uniformly stored in the same probability memory, and the problem of storage space waste caused by the co-location of the probability memory with the probability of the coding syntax elements supporting the 16 symbol coding can be avoided.
If the coded syntax element satisfies the predetermined coefficient class condition, the coded syntax element may be stored as a second type coded syntax element in the second buffer 108, whereas if the coded syntax element does not satisfy the predetermined coefficient class condition, the coded syntax element may be stored as a first type coded syntax element in the first buffer 106. In this way, it is ensured that the second encoded syntax elements stored in the second buffer 108 all satisfy the predetermined coefficient-like condition.
In fact, for the context probability processing circuit in AV1 entropy coding, most of the resulting coded syntax elements are generated by the coefficient part, and the number of coded syntax elements such as coeff _ br is the largest among the coded syntax elements generated by the coefficient part, and the number of symbol codes supported by coeff _ br is 4. Therefore, a preferred implementation is to determine the coding syntax element such as coeff _ br as the second type coding syntax element satisfying the condition of the predetermined coefficient type or as the second type coding syntax element of the predetermined coefficient type. Thus, the type of the second encoded syntax element buffered by the second buffer 108 is coeff _ br, the type of the first encoded syntax element buffered by the first buffer 106 is other, e.g., coeff _ base _ eob, dc _ sign, etc., and other encoded syntax elements not generated by the coefficient part.
In the embodiment of the present specification, the first buffer 106 and the second buffer 108 are both first-in first-out FIFO memories, i.e. the encoded syntax elements stored in the first buffer 106 and the second buffer 108 are extracted in the order of entry.
The first probability processing engine 110 sequentially fetches the buffered first type of coded syntax elements from the first buffer 106 and sequentially updates the probabilities of the first type of coded syntax elements within the first probability store 114. In a specific implementation, based on the extracted first type of coded syntax element, the probability corresponding to the first type of coded syntax element may be searched from the first probability storage 114 according to an existing statistical updating manner, a new probability value is calculated based on an existing probability according to a coding standard, and the new probability is stored again in the probability address space corresponding to the first type of coded syntax element in the first probability storage 114.
In fact, the first type of coded syntax elements may include a plurality of coded syntax element types, such as coeff _ base, coeff _ base _ eob, dc _ sign, etc., and a plurality of element sub-entries may be further disposed under each coded syntax element, so that, in the first probability memory 114, a probability of occurrence of each coded syntax element or a probability of occurrence of a corresponding element sub-entry in each coded syntax element may be stored.
The second probability processing engine 112 sequentially extracts the buffered second-type coded syntax elements from the second buffer 108 and sequentially updates the probability of the second-type coded syntax elements in the second probability memory 116. Wherein the second probability processing engine 112 can update the probability of the second type of coded syntax element in the second probability storage 116 in the manner processed by the first probability processing engine 110.
In the AV1 coding standard, the probability of each coding syntax element can be counted in advance, classification comparison is carried out, and if the probability of a certain coding syntax element is different from other probabilities, a probability corresponding to address storage is developed; corresponding to the context probability processing circuit, it is necessary to individually count the probabilities for this coded syntax element, for example, to individually open up a piece of memory space in the first probability memory. In fact, the initialized probability can be input in advance in the first probability storage or the second probability storage, that is, an initial probability value is set for each coding syntax element, and then, each time a probability updating request is received, the probability of the coding syntax element corresponding to the probability updating request is updated.
In this way, while the first probability processing engine 110 processes the first type of coded syntax elements, the second probability processing engine 112 can process the second type of coded syntax elements, so as to achieve the purpose of processing the coded syntax elements in parallel in the same clock cycle, and further, the probability processing speed can be increased, and the coding efficiency can be improved.
It should be noted that, in the embodiment of the present specification, the first probability storage 114 may be a random access memory with a register function, and the second probability storage 116 may be a distributed storage LUT RAM, which has a simple structure and is faster and more convenient to access.
In fact, the purpose of adding the second probability processing engine 112 is not just to achieve parallel processing with the first probability processing engine 110. Within the second probability processing engine 112, the purpose of increasing the probability processing speed can also be achieved.
Basically, the probability processing engine in the context probability processing circuit processes a probability update request of a coding syntax element in one clock cycle. However, the second probability processing engine 112 of the present specification can support probability updating of two identical coded syntax elements in succession for a coded syntax element whose probability velocity is already stable, i.e. can process two probability update requests in one cycle.
Referring to fig. 2, the second probability processing engine 112 includes: a data parsing circuit 1122, a third probabilistic processing engine 1124 and a consecutive addresses acceleration engine 1126; the data parsing circuit 1122 determines whether the currently extracted second-type coded syntax element supports continuous address acceleration, and if so, sends the second-type coded syntax element to the continuous address acceleration engine 1126, and if not, sends the second-type coded syntax element to the third probability processing engine 1124; the third probability processing engine 1124 sequentially updates the probability of the second type of coded syntax elements within the second probability store 116; the sequential address acceleration engine 1126 sequentially updates the probabilities of the two second-type coded syntax elements in the second probability memory 116 in one clock cycle. The first probability processing engine 110 and the third probability processing engine 1124 are the same type of engine and the processing operation and implementation function are the same.
When determining whether the currently extracted second-type syntax element supports consecutive address acceleration, the data parsing circuit 1122 may determine whether the probability speed of the currently extracted second-type syntax element is stable and whether two consecutive second-type syntax elements point to the same address in the second probability storage.
Similarly, the second type of coded syntax element may comprise a plurality of element sub-entries; in fact, some of the first-type coding syntax elements may include multiple element sub-items, or may not include multiple element sub-items. The data parsing circuit 1122 may count the number of sub-items of multiple elements in the second-type coded syntax element when determining whether the probability speed of the currently extracted second-type coded syntax element is stable, and determine that the probability speed of the currently extracted second-type coded syntax element is stable if the sub-item of the element corresponding to the currently extracted second-type coded syntax element has reached a set threshold. In other words, if a plurality of element sub-items are included in the second type of coded syntax element, it can be determined whether the element sub-item of the second type of coded syntax element has reached a stable probability speed (also called a probability update speed) according to the number of times each element sub-item appears. Meanwhile, it is also necessary to determine whether the previous or next item of the element sub-item has the same address space in the second probability memory, and if both are satisfied, that is, the probability speed is stable and the same address space is available, the second type of coded syntax element may be sent to the consecutive address acceleration engine 1126 for acceleration processing. Otherwise, the data is sent to a third probability processing engine for serial processing, namely, a probability updating request is processed in one clock cycle.
The consecutive address acceleration engine 1126, when updating the probabilities of the two second-type coded syntax elements in the second probability memory sequentially within one clock cycle, is specifically configured to update the probabilities of the two second-type coded syntax elements pointing to the same address in the second probability memory sequentially within one clock cycle. It should be noted that, the number of the probability updating requests to be processed continuously is set to two, which is determined by combining the complexity of the circuit through a plurality of tests, and the probability processing speed when three probability updating requests are processed continuously is not increased too much, but is affected by the complexity of the circuit.
Referring to FIG. 3, the consecutive address acceleration engine includes a first sub-acceleration circuit cdf0, a second sub-acceleration circuit cdf1, and a data selector MUX; wherein, the first sub-accelerator cdf0 selects a signal based on the probability of a first consecutive address (for example, consecutive address 0), and calculates a first output result; the second sub accelerator circuit cdf1 selects a second signal and the first output result based on the probability of a second consecutive address (which may be, for example, consecutive address 1), and calculates a second output result. And then, the data selector MUX determines final probability output according to the second output result.
Still referring to fig. 3, the accelerateselect (acceleratemen) signal is input to the MUX, and the accelerateselect signal is used to trigger the MUX to turn on the consecutive address acceleration selection function, and the consecutive address acceleration only supports the input of two consecutive same addresses, so that two same address requests can be processed at a time. Under normal conditions, the common signal does not support acceleration, flows to a common engine branch of the third probability processing engine, is used as a gating signal to the MUX according to the upper clock _ en signal, and selects the common engine branch. Under acceleration conditions, two consecutive addresses can be supported simultaneously, such that there are two sub-acceleration circuits, a first sub-acceleration circuit cdf0 for the first address, a second sub-acceleration circuit cdf 1; similarly, there are two inputs, one for the probability of the first sub-accelerator circuit (assuming that the total number of accelerator address probability storage members is 4, the probability of the input is one, and the probability of the whole is modified for the input), and two for the probability of the second sub-accelerator circuit (probability selection corresponding to consecutive address 0/probability selection of consecutive address 1 on the graph). In fact, the two sub-accelerators cdf0 and cdf1 may be the same circuit unit.
Each SUB-acceleration circuit is actually in a circuit form of a calculation formula, wherein SUB is subtraction (upper value minus lower value), ADD is addition (addition of values of two branches), right _ shift _7 is right shift (data > 7 in the formula), and the whole means that a sel signal is input to trigger MUX, 32768 is used as a current number or a random number, the input signal is subtracted, then the input signal is shifted to the right by 7 bits, and the addition of the input signal obtains an addition result; the input signal is shifted to the right by 7 bits and then is subtracted from the input signal to obtain a subtraction result; finally, the MUX selects the addition result and the subtraction result.
Alternatively, in the present specification embodiment, when the number of occurrences of a coded syntax element reaches 32 times, it may be determined that the probability update speed of the coded syntax element has reached stability, and it may be decided whether the probability update acceleration processing can be performed on the coded syntax element using the consecutive address acceleration engine 1126. It should be understood that the occurrence number of the coding syntax element 32 times herein can be understood as an approximately ideal stable state, and actually, when the coding technology further develops or advances, the occurrence number used for achieving the stable probability updating speed may be other than 32, for example, 30 or 29, etc., which is not limited in this specification.
Therefore, on the basis that the first probability processing engine and the second probability processing engine perform parallel processing to improve the probability processing speed, the second type of coded syntax elements with the probability speed tending to be stable can be continuously processed through the continuous address acceleration engine in the second probability processing engine, and further, the processing speed of one path is improved on the basis of the parallel processing, so that the processing speed of the whole context probability processing circuit can be further improved, and the coding efficiency is improved. Moreover, the second probability processing engine uniformly stores the probabilities of the second type of coding syntax elements in the distributed second probability storage, and the probabilities of the second type of coding syntax elements and the probabilities of other coding syntax elements with more than 4 symbols are not required to be stored in one storage together, so that the waste of storage space is avoided, the storage space is reasonably utilized, and the fast access is convenient.
Referring to fig. 4, a schematic diagram of steps of a context probability processing method based on AV1 entropy coding provided in an embodiment of the present specification is shown, and it should be understood that the method is applied to the context probability processing circuit shown in fig. 1. With reference to fig. 1 to 3, the context probability processing method may include the following steps:
step 402: the control state machine reads a preceding-stage coding result of each block from the coding result storage, generates a plurality of coding syntax elements which are sequentially arranged according to a coding standard determined by the preceding-stage coding result, and sequentially judges whether the coding syntax elements meet preset coefficient conditions, if not, the coding syntax elements are sent to a first buffer for caching as first-type coding syntax elements, and if so, the coding syntax elements are sent to a second buffer for caching as second-type coding syntax elements;
step 404: the first probability processing engine sequentially extracts the cached first type of coding syntax elements from the first cache and sequentially updates the probability of the first type of coding syntax elements in the first probability memory;
step 406: and the second probability processing engine sequentially extracts the cached second-type coding syntax elements from the second cache and sequentially updates the probability of the second-type coding syntax elements in the second probability memory.
It should be noted that the order of step 404 and step 406 is not limited, and may be performed simultaneously.
Optionally, the controlling the state machine sequentially determines whether the coded syntax element satisfies a predetermined coefficient class condition, including: sequentially judging whether the coding syntax elements belong to preset coefficient types or not; and the occupation ratio of the coding syntax elements corresponding to the preset coefficient type exceeds a threshold value, and the coding syntax elements corresponding to the preset coefficient type are coded in parallel by adopting a set number of symbols.
In a specific implementation manner of the embodiments of the present specification, the sequentially updating, by the second probability processing engine, the probabilities of the second type of coded syntax elements in the second probability memory includes:
the data analysis circuit judges whether the currently extracted second-type coding syntax element supports continuous address acceleration, if so, the second-type coding syntax element is sent to the continuous address acceleration engine, and if not, the second-type coding syntax element is sent to a third probability processing engine; the third probability processing engine sequentially updates the probability of the second type coding syntax element in the second probability memory; the sequential address acceleration engine sequentially updates the probabilities of the two second-type coded syntax elements in the second probability memory in one clock cycle.
In another specific implementation manner of the embodiment of the present specification, the determining, by the data parsing circuit, whether the currently extracted second-type coding syntax element supports continuous address acceleration includes: and judging whether the probability speed of the currently extracted second-type coding syntax element is stable or not, and whether two continuous second-type coding syntax elements point to the same address in a second probability memory or not.
In yet another specific implementation manner of the embodiments of the present specification, the second type of coded syntax element includes a plurality of element sub-items; the data analysis circuit judges whether the probability speed of the currently extracted second-type coding syntax element is stable or not, and comprises the following steps: counting the number of the sub items of the plurality of elements in the second type of coding syntax elements, and if the sub items of the elements corresponding to the currently extracted second type of coding syntax elements reach a set threshold value, determining that the probability speed of the currently extracted second type of coding syntax elements is stable;
the sequential address acceleration engine sequentially updates the probabilities of the two second-type coded syntax elements in the second probability storage in one clock cycle, including: the probabilities of two second-type coded syntax elements pointing to the same address in the second probability memory are updated sequentially within one clock cycle.
Referring to fig. 5, a schematic diagram of a context probability processing flow based on AV1 entropy coding provided in an embodiment of the present specification is shown.
Step 502: the control state machine reads the previous-stage coding result of each block from the coding result memory, and generates a plurality of coded syntax elements arranged in sequence according to the coding standard determined by the previous-stage coding result.
Step 504: the control state machine judges whether the coding syntax element meets the preset coefficient class condition in turn, if yes, the step 506 is executed; if not, step 508 is performed.
Step 508: and the control state machine sends the current coding syntax element as a first type coding syntax element to a first buffer for buffering.
Step 510: the first probability processing engine sequentially extracts the buffered first type of coded syntax elements from the first buffer and sequentially updates the probability of the first type of coded syntax elements in the first probability memory.
It should be understood that sequential updating herein means sequential updating in the order of extraction from the first buffer. And the first probability processing engine updates the probability of a first type of coded syntax element in the first probability memory in one clock cycle when updating the probability.
Step 512: and the second probability processing engine sequentially extracts the cached second-type coding syntax elements from the second cache.
Step 514: and the second probability processing engine judges whether the probability speed of the currently extracted second-type coding syntax element is stable or not and whether two continuous second-type coding syntax elements point to the same address in the second probability memory or not. If yes, go to step 516, otherwise, go to step 518.
Step 516: and the second probability processing engine sends the second type coding syntax elements to the continuous address acceleration engine, and the continuous address acceleration engine sequentially updates the probability of the two second type coding syntax elements in the second probability memory in one clock cycle.
Unlike the updating method in step 510, step 516 is also a sequential updating, but the sequential address acceleration engine sequentially updates the probabilities of two second-type coded syntax elements in the second probability memory in one clock cycle. The specific update circuit can be seen with reference to fig. 3.
Step 518: the second probability processing engine sends the second type of coding syntax elements to a third probability processing engine, and the third probability processing engine sequentially updates the probability of the second type of coding syntax elements in the first probability memory.
The third probability processing engine is similar in function to the first probability processing engine in that it processes the probability of an encoded syntax element in the first probability store in one clock cycle, except that the objects processed by the third probability processing engine are encoded syntax elements of the second type and the objects processed by the first probability processing engine are encoded syntax elements of the first type.
The coefficient processing engine is added in the context probability processing circuit to perform probability calculation aiming at the coding syntax elements meeting the preset coefficient condition in the coding syntax elements, so that the parallel processing of the coding syntax elements is realized in the context probability processing circuit, the continuous processing of the second type coding syntax elements with the stable probability speed can be performed by the continuous address acceleration engine in the second probability processing engine, and further, the processing speed of one path is increased on the basis of the parallel processing, so that the processing speed of the whole context probability processing circuit can be further increased, and the coding efficiency is increased. Moreover, the second probability processing engine uniformly stores the probabilities of the second type of coding syntax elements in the distributed second probability storage, and the probabilities of the second type of coding syntax elements and the probabilities of other coding syntax elements with more than 4 symbols are not required to be stored in one storage together, so that the waste of storage space is avoided, the storage space is reasonably utilized, and the fast access is convenient.
An embodiment of the present specification further provides an image encoding apparatus, including: the context probability processing circuit based on AV1 entropy coding described in fig. 1-3, and other circuit modules connected with the context probability processing circuit. The probability distribution of each coding syntax element of the target image is obtained through statistics and updating of the context probability processing circuit, arithmetic coding is carried out to obtain the simplest code stream, and therefore coding of the target image is achieved.
The present specification also provides a chip, which includes the context probability processing circuit based on AV1 entropy coding described in fig. 1-3, or the image coding apparatus.
As can be seen from the above description, the context probability processing circuit based on AV1 entropy coding provided in this specification can be applied to any electronic device including an image coding apparatus and a chip. The electronic device may be, for example, a cloud server with a large number of data centers, or may be various electronic devices used in daily life.
FIG. 6 illustrates a general computer architecture to which the embodiments of the specification may be applied. As shown in fig. 6, computer system 600 may include one or more processors 602, and memory 604. In some embodiments, the context probability processing circuit based on AV1 entropy coding described above can be used in the computer architecture to provide coding services, and in other embodiments, the system-on-chip can be used directly as the processor 602 in the present embodiment. The memory 604 in the computer system 600 may be main memory (referred to simply as main memory or memory). For storing instruction information and/or data information represented by data signals, such as data provided by the processor 602 (e.g., operation results), and for implementing data exchange between the processor 602 and the external storage device 606 (or referred to as an auxiliary memory or an external memory). In some cases, the processor 602 may need to access the memory 604 to retrieve data in the memory 604 or to make modifications to data in the memory 604. Based on this, the processor 602 may include an instruction execution unit 6022, a memory management unit 6024, and the like. In addition, computer system 600 may also include input/output devices such as a display device 608, an audio device 610, a mouse/keyboard 612, and the like. The display device 608 is coupled to the bus, for example, via a corresponding graphics card, for displaying in accordance with display signals provided by the bus. Computer system 600 also typically includes a communication device 614, which may communicate with a network or other devices in a variety of ways. Different computer systems may vary in their configuration depending on the motherboard, operating system, and instruction set architecture. For example, many computer systems today have an input/output control hub coupled between the bus and various input/output devices, and the input/output control hub may be integrated within the processor 602 or separate from the processor 602.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement or the like made within the spirit and principle of the present application shall be included in the scope of the claims of the present application.
Claims (14)
1. A context probability processing circuit based on AV1 entropy coding, comprising: the system comprises an encoding result memory for storing preceding-stage encoding results of different blocks of a target image, a control state machine, a first buffer and a second buffer, a first probability processing engine, a second probability processing engine, a first probability memory and a second probability memory; wherein,
the control state machine is used for reading the preceding-stage coding result of each block from the coding result storage, generating a plurality of coding syntax elements which are sequentially arranged according to the coding standard determined by the preceding-stage coding result, sequentially judging whether the coding syntax elements meet the preset coefficient condition, if not, sending the coding syntax elements as the first-type coding syntax elements to the first buffer for caching, and if so, sending the coding syntax elements as the second-type coding syntax elements to the second buffer for caching;
the first probability processing engine is used for sequentially extracting the cached first type of coding syntax elements from the first cache and sequentially updating the probability of the first type of coding syntax elements in the first probability memory;
and the second probability processing engine is used for sequentially extracting the cached second type coding syntax elements from the second cache and sequentially updating the probability of the second type coding syntax elements in the second probability storage.
2. The AV1 entropy coding-based context probability processing circuit of claim 1, wherein the control state machine, when sequentially determining whether the encoded syntax elements satisfy the predetermined coefficient class conditions, is specifically configured to:
sequentially judging whether the coding syntax elements belong to preset coefficient types or not; and the occupation ratio of the coding syntax elements corresponding to the preset coefficient type exceeds a threshold value, and the coding syntax elements corresponding to the preset coefficient type are coded by adopting a set number of symbols.
3. The AV1 entropy encoding-based context probability processing circuit of claim 1, the second probability processing engine comprising: the data analysis circuit, the third probability processing engine and the continuous address acceleration engine; wherein,
the data analysis circuit is used for judging whether the currently extracted second type coding syntax element supports continuous address acceleration or not, if so, the second type coding syntax element is sent to the continuous address acceleration engine, and if not, the second type coding syntax element is sent to a third probability processing engine;
the third probability processing engine is used for sequentially updating the probability of the second type coding syntax element in the second probability memory;
the continuous address acceleration engine is used for sequentially updating the probability of the two second-type coding syntax elements in the second probability storage in one clock cycle.
4. The AV1 entropy coding based context probability processing circuit of claim 3, wherein the data parsing circuit, when determining whether the currently extracted second type of coded syntax element supports continuous address acceleration, is specifically configured to:
and judging whether the probability speed of the currently extracted second-type coding syntax element is stable or not, and whether two continuous second-type coding syntax elements point to the same address in a second probability memory or not.
5. The AV1 entropy based context probability processing circuit of claim 4, wherein the second type of coded syntax element comprises a plurality of element sub-entries;
the data analysis circuit is specifically used for counting the number of sub items of a plurality of elements in the second type of coding syntax elements when judging whether the probability speed of the currently extracted second type of coding syntax elements is stable, and if the sub items of the elements corresponding to the currently extracted second type of coding syntax elements reach a set threshold value, determining that the probability speed of the currently extracted second type of coding syntax elements is stable;
the sequential address acceleration engine is specifically configured to sequentially update the probabilities of two second-type coded syntax elements pointing to the same address in the second probability storage in one clock cycle when sequentially updating the probabilities of the two second-type coded syntax elements in the second probability storage in one clock cycle.
6. The AV1 entropy coding based context probability processing circuit of any one of claims 3-5, the serial address acceleration engine comprising a first sub-acceleration circuit, a second sub-acceleration circuit, and a data selector; the first sub-acceleration circuit selects input based on the probability of the first continuous address, and calculates to obtain a first output result; and the second sub-acceleration circuit selects input and the first output result based on the probability of a second continuous address, and calculates to obtain a second output result.
7. The AV1 entropy encoding based context probability processing circuit of any one of claims 1-5, the first probability processing engine and the third probability processing engine being a same type of engine; and/or;
the second probabilistic memory is a distributed memory.
8. A context probability processing method based on AV1 entropy coding, applied to the context probability processing circuit based on AV1 entropy coding of any one of claims 1-7; the method comprises the following steps:
the control state machine reads a preceding-stage coding result of each block from the coding result storage, generates a plurality of coding syntax elements which are sequentially arranged according to a coding standard determined by the preceding-stage coding result, and sequentially judges whether the coding syntax elements meet preset coefficient type conditions, if not, the coding syntax elements are sent to a first buffer for caching as first-type coding syntax elements, and if so, the coding syntax elements are sent to a second buffer for caching as second-type coding syntax elements;
the first probability processing engine sequentially extracts the cached first type of coding syntax elements from the first cache and sequentially updates the probability of the first type of coding syntax elements in the first probability memory;
and the second probability processing engine sequentially extracts the cached second-type coding syntax elements from the second cache and sequentially updates the probability of the second-type coding syntax elements in the second probability memory.
9. The AV1 entropy-based context probability processing method of claim 8, wherein the controlling state machine sequentially determines whether the encoded syntax elements satisfy predetermined coefficient class conditions, comprising:
sequentially judging whether the coding syntax elements belong to preset coefficient types or not; and the occupation ratio of the coding syntax elements corresponding to the preset coefficient type exceeds a threshold value, and the coding syntax elements corresponding to the preset coefficient type are coded in parallel by adopting a set number of symbols.
10. The AV1 entropy coding based context probability processing method of claim 8, wherein the second probability processing engine sequentially updates the probability of the second type of coded syntax element within the second probability store, comprising:
the data analysis circuit judges whether the currently extracted second-type coding syntax element supports continuous address acceleration, if so, the second-type coding syntax element is sent to the continuous address acceleration engine, and if not, the second-type coding syntax element is sent to a third probability processing engine;
the third probability processing engine sequentially updates the probability of the second type coding syntax element in the second probability memory;
the sequential address acceleration engine sequentially updates the probabilities of the two second-type coded syntax elements in the second probability memory in one clock cycle.
11. The AV1 entropy-based context probability processing method of claim 10, wherein the data parsing circuit determines whether the currently extracted second-type coded syntax element supports consecutive address acceleration, comprising:
and judging whether the probability speed of the currently extracted second-type coding syntax element is stable or not, and whether two continuous second-type coding syntax elements point to the same address in a second probability memory or not.
12. The AV1 entropy coding based context probability processing method of claim 11, wherein the second type of coded syntax element includes a plurality of element sub-items;
the data analysis circuit judges whether the probability speed of the currently extracted second-type coding syntax element is stable or not, and comprises the following steps: counting the number of the plurality of element sub-items in the second-type coding syntax element, and if the element sub-item corresponding to the currently extracted second-type coding syntax element reaches a set threshold value, determining that the probability speed of the currently extracted second-type coding syntax element is stable;
the sequential address acceleration engine sequentially updates the probabilities of the two second-type coded syntax elements in the second probability memory in one clock cycle, including: the probabilities of two second-type coded syntax elements pointing to the same address in the second probability memory are updated sequentially within one clock cycle.
13. An image encoding device comprising: the AV1 entropy coding-based context probability processing circuit of any one of claims 1-7.
14. A chip comprising the context probability processing circuit based on AV1 entropy coding of any one of claims 1 to 7, or the image encoding apparatus of claim 13.
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