CN114928361A

CN114928361A - System and method for realizing synchronous data acquisition across devices

Info

Publication number: CN114928361A
Application number: CN202210740747.5A
Authority: CN
Inventors: 徐驰
Original assignee: Shanghai Hanzhi Electronic Technology Co ltd
Current assignee: Shanghai Hanzhi Electronic Technology Co ltd
Priority date: 2022-06-28
Filing date: 2022-06-28
Publication date: 2022-08-19

Abstract

The invention discloses a system and a method for realizing cross-equipment synchronous data acquisition, wherein the system for realizing cross-equipment synchronous data acquisition comprises an external clock transmitting device, an analog-to-digital converter (ADC) and an FPGA chip, wherein the FPGA chip is connected with the external clock transmitting device and the ADC; the method for realizing synchronous acquisition comprises the following steps: determining the sampling rate of the ADC according to the sampling rate of the external clock; based on the determined sampling rate, the low-pass filter determines the word length of the coefficient and the number of the coefficient according to the precision requirement; the FPGA chip receives an external clock signal and controls the ADC to acquire data according to the sampling rate; the FPGA chip receives the sampling data and enters a sampling value buffering part, new sampling data is stored, and the earliest sampling data is popped up; calculating a sampling value after resampling according to the arrival time sequence of the external clock signal, the oversampling clock signal and the sampling data; the device needing data acquisition receives the homologous external clock signal, and the two steps of sampling and calculating are repeated, so that a sampling value is obtained, and synchronous acquisition among the devices is realized.

Description

System and method for realizing synchronous data acquisition across equipment

Technical Field

The invention relates to the field of electronics and data communication, in particular to a system and a method for synchronously acquiring data among devices.

Background

According to the working principle of the AD chip based on the Delta-Sigma module in the industry, an oversampling clock is arranged inside the AD chip, and the sampling frequency of the oversampling clock is very high, typically 12.8MHz, 13.1072MHz and the like. Such sharing among frequency modules can be achieved, but after the acquisition module is made into an equipment product, clock signals and trigger signals are shared among a plurality of pieces of equipment, so that synchronous acquisition is very inconvenient, and therefore, cross-equipment synchronization becomes very difficult to achieve.

At present, a technical implementation for realizing synchronization between devices based on the principle of external clock resampling is provided. First, the operation principle of band-limited interpolation is described. Band-limited interpolation based on off-line digital signal sequences is a very basic digital signal processing tool, but at the same time it has a very wide range of applications. When we need to reconstruct the sampling value at any time for the sampling value of a discrete time sequence, we need to do interpolation operation. We assume that this discrete time sequence corresponds to a signal bandwidth less than 1/2 at the sampling rate, which meets the band-limit requirement. Otherwise aliasing will occur in the signal. According to the Shannon sampling theory, the band-limited interpolation can accurately recover and reconstruct the sampling value at any moment.

There are many interpolation algorithms in mathematics, such as lagrange interpolation, spline difference interpolation, berzel interpolation. These algorithms have very good results in terms of smoothness of the curves. But there are frequency requirements in digital signal processing and therefore none of the above algorithms are applicable. Therefore, the method is realized by using a band-limited interpolation algorithm under the consideration of a sampling theory based on fragrance concentration.

Multirate digital signal processing provides an integrated signal processing technique that provides a flexible method of sample rate variation. A digital signal obtained by a certain sampling rate can be first interpolated by L (positive integer) times and then decimated by M (positive integer) factors, and a new sampling rate of any rational number factor (L/M) can be obtained. This variation requires the design of a low pass filter cut-off frequency that is the maximum of the L and M decimation operations. Such a calculation process is less convenient for sample point recovery at arbitrary times and resampling at variable sampling rates.

In view of the foregoing, there is a need to develop a system and method for synchronously acquiring devices to solve the above technical problems.

Disclosure of Invention

The existing synchronous acquisition technology for digital signal processing has the defects that cross-equipment acquisition is inconvenient, resampling calculation is difficult to easily realize sampling point recovery reconstruction at any time and with variable sampling rate.

In order to solve the above technical problem, an aspect of the present application provides a system for implementing synchronous data acquisition across devices, including: the external clock device comprises an external clock sending device, an Analog Digital Converter (ADC) and an FPGA chip. The FPGA chip is connected with the external clock sending equipment and the ADC, the FPGA chip is used for receiving an external clock signal provided by the external clock sending equipment, and the FPGA chip generates sampling rate control based on the sampling rate of the external clock; the ADC is coupled to receive the parallel data and a sampling rate control, the ADC generates an oversampling clock based on the sampling rate control and the oversampling rate, and the ADC converts the parallel data to an analog voltage level; the FPGA chip is installed on the equipment needing to acquire data.

According to an embodiment of the application, the system for synchronously acquiring data further comprises a GPS receiver, which is responsible for providing a pulse signal of a synchronous clock for the acquired device.

According to the embodiment of the application, the system for synchronously acquiring data further comprises a low-pass filter, a sampling value buffer and a time register. The low-pass filter is used for controlling the frequency of the acquired signal not to be higher than a limit value based on the principle of a sinc function; the sampling value cache receives the collected data and is used for reserving a latest sampling value; the time register comprises a sampling domain, a lookup table domain and a placement output domain, wherein the sampling domain is used for placing sampling points of input signals; the lookup table field is used for storing the word length and the number of the sampling rate coefficients determined by the low-pass filter; the output field is arranged to indicate a time signal between adjacent ones of the sampling points.

According to the embodiment of the application, the ADC comprises a sampling data reading interface and a starting control interface, the sampling data reading interface is connected with collected equipment, and the starting control interface is connected with the FPGA chip.

In another aspect, the present invention provides a method for implementing data acquisition across devices synchronously, which is applied to the above system for implementing data acquisition across devices synchronously, and the method includes the following steps:

step 1: determining the sampling rate of the ADC according to the sampling rate of the external clock;

step 2, determining the word length of the coefficient and the number of the coefficient according to the precision requirement by utilizing the sampling rate determined in the step 1 and the principle of a low-pass filter based on a sinc function;

step 3, starting the external clock sending equipment, receiving an external clock signal by the FPGA chip, and controlling the ADC to collect data according to the sampling rate;

and 4, step 4: the FPGA chip receives the sampling data and enters a sampling value buffering part, new sampling data are stored, the earliest sampling data are popped out, and the amount of the stored sampling data is ensured to accord with the capacity of a sampling domain of a time register;

and 5: calculating a sampling value after resampling according to the arrival time sequence of the external clock signal, the oversampling clock signal and the sampling data;

step 6: and (5) the equipment needing to acquire data receives the homologous external clock signal, and the step 4 and the step 5 are repeated, so that a sampling value is obtained, and synchronous acquisition among the cross-equipment is realized.

According to an embodiment of the present application, the following algorithm is used for calculating the sampling value in step 5:

wherein,

in the formula: x (t) is a sampling value of a continuous analog signal, t is a real number, and t is more than or equal to 0; ts is sampling interval time; n-0, 1, 2, … …, representing an integer, resulting in a time series x [ nTs ]; fs is sampling rate, and Fs is 1/Ts; the frequency range of x (t) is within + -Fs/2.

According to the embodiment of the application, each reconstructed sampling value is calculated by formula (1) and then is calculated by a time register to obtain a reconstructed value y (t):

wherein,

in the formula: n is the sample value index and n is 0,1, 2, … …, representing an integer; l is the filter coefficient index in the time register; eta is an interpolation factor between the nth sampling point and the (n + 1) th sampling point at the reconstruction moment, and eta is more than or equal to 0 and less than 1; h (l) is the coefficient of the low-pass filter.

According to an embodiment of the application, the time register stores an input signal comprising N2 ^ (nn) samples, and the coefficient lookup table of the low pass filter stores L2 ^ (nl) filter coefficients.

According to the embodiment of the present application, in step 1, the required sampling rate is achieved through internal down-sampling, and the internal filter also passes through the algorithm of low-pass decimation, so that the signal bandwidth frequency is ensured to be 1/2 smaller than the sampling rate of the external clock.

Compared with the prior art, the technical scheme of the invention has the beneficial effects that:

1. by utilizing the powerful online processing capacity of the FPGA chip, the resampling data with an external clock signal as a reference can be obtained. When multiple devices receive external clock signals with the same frequency and the same phase, the effect of synchronous acquisition of the multiple devices can be achieved.

2. The time register is used and coupled to receive the collected data, store the filter coefficient lookup table and represent the position between adjacent sampling points, and the time register stores and outputs the collected data at a high speed, so that the calculation speed during recovery and reconstruction can be improved.

3. According to the technical scheme, the sampling value index, the filter coefficient index and the interpolation factor are introduced into the calculation method, calculation is carried out based on the sinc function, and the relation between the sampling point and the sinc function at any moment can be displayed in a graph, so that the signal can be calculated and recovered at any time.

4. The method of the application realizes that the interpolation process is 1:1 interpolation processing, namely the sampling rate is the same as the frequency of the external clock, and the algorithm also supports N times of interpolation, namely the frequency of the external clock can be 1/N of the target sampling rate. This reduces the clock frequency when sharing the clock between devices, which reduces the requirements on the transmission cable for deploying synchronous acquisition in a range of hundreds of meters.

5. To further reduce the pin count, only one of the external or other clocks is required, in addition to the input serial data from the ADC interface bus, the other clock being generated locally on the chip. The external clock is the only input clock and the oversampling clock is generated by the ADC according to a predefined external clock frequency.

Drawings

FIG. 1 is a block diagram of a system for implementing synchronous data acquisition across devices according to the present invention;

FIG. 2 is a schematic diagram of a reconstructed band-limited signal recovered after superposition of a partial image of a sinc function and the sinc function in the method for realizing synchronous data acquisition across devices according to the present invention;

FIG. 3 is a graph of the amplitude-frequency response of an ideal low-pass filter in an embodiment of the present invention;

FIG. 4 is a schematic diagram illustrating differences between rectangular windows and kaiser windows used in convolution calculation in a method for achieving synchronous data acquisition across devices according to the present invention;

FIG. 5 is a schematic diagram illustrating the components of a time register of a system for implementing synchronous data acquisition across devices according to the present invention;

fig. 6 is a waveform diagram of a relationship between a sampling point and a sinc function at a certain time in the method for realizing synchronous data acquisition across devices according to the present invention.

The specific implementation mode is as follows:

the invention is further described with reference to the following figures and specific examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.

As shown in fig. 1, in one aspect, the present application provides a system for implementing synchronous data acquisition across devices, including: the device comprises external clock sending equipment, an Analog Digital Converter (ADC) and an FPGA chip, wherein the resampling data with an external clock signal as a reference can be obtained by utilizing the strong online processing capacity of the FPGA chip. When multiple devices receive external clock signals with the same frequency and the same phase, the effect of synchronous acquisition of the multiple devices can be achieved.

The FPGA chip is connected with the external clock sending equipment and the ADC, the FPGA chip is used for receiving an external clock signal provided by the external clock sending equipment, and the FPGA chip generates sampling rate control based on the sampling rate of the external clock; the ADC is coupled to receive the parallel data and a sampling rate control, the ADC generates an oversampling clock based on the sampling rate control and the oversampling rate, and the ADC converts the parallel data to an analog voltage level; the FPGA chip is installed on equipment needing data acquisition.

Furthermore, the system for synchronously acquiring data also comprises a GPS receiver which is responsible for providing pulse signals of synchronous clocks for the acquired equipment.

Further, the system for synchronously acquiring data also comprises a low-pass filter, a sampling value buffer and a time register. The low-pass filter is used for controlling the frequency of the collected signal not to be higher than a limit value based on the principle of a sinc function; the sampling value cache receives the collected data and is used for reserving a latest sampling value; the time register comprises a sampling domain, a lookup table domain and a placement output domain, wherein the sampling domain is used for placing sampling points of input signals; the lookup table field is used for storing the word length and the number of the sampling rate coefficients determined by the low-pass filter; the output field is arranged to indicate a time signal between adjacent ones of the sampling points.

Furthermore, the ADC comprises a sampling data reading interface and a starting control interface, the sampling data reading interface is connected with the collected equipment, and the starting control interface is connected with the FPGA chip.

The invention provides a method for realizing cross-equipment synchronous data acquisition, which is applied to the system for realizing cross-equipment synchronous data acquisition and comprises the following steps:

and 6: and (4) the equipment needing to acquire data receives the homologous external clock signal, and the step 4 and the step 5 are repeated, so that a sampling value is obtained, and synchronous acquisition among the cross-equipment is realized.

wherein,

in the formula: x (t) is a sampling value of a continuous analog signal, t is a real number, and t is more than or equal to 0; ts is sampling interval time; n-0, 1, 2, … …, representing an integer, resulting in a time series x [ nTs ]; fs is a sampling rate, and Fs is 1/Ts; the frequency range of x (t) is within + -Fs/2.

Further, after each reconstructed sampling value is calculated by formula (1), a reconstructed value y (t) is calculated by a time register:

wherein,

Further, the time register stores an input signal comprising N2 samples, and the coefficient lookup table of the low pass filter stores L2 filter coefficients.

Further, in step 1, the required sampling rate is achieved through internal down-sampling, and the internal filter also passes through the algorithm of low-pass decimation, so that 1/2 that the signal bandwidth frequency is less than the sampling rate of the external clock is ensured.

The algorithm principle of a specific embodiment of the present application is as follows:

for samples of a continuous analog signal x (t), t is a real number and t ≧ 0. The sampling interval of Ts is also the inverse of the sampling rate Fs 1/Ts. n is 0,1, 2, … …, representing an integer, resulting in a time series x [ nTs [ [ n ] s [ ]]. x (t) is a band-limited signal with a frequency range within + -Fs/2. X (ω) is the Fourier transform of X (t),

as the band-limited signal, X (ω) is 0, | ω | > or ≧ pi Fs. According to the Shannon sampling theorem, the x (t) signal can be x [ nTs ]]And (4) completely recovering.

Here, the

If the signal is to be reconstructed at the new sampling rate F's of 1/T's, the recalculation of positions for integer multiples of T's in the above equation needs to be considered. When the new sampling rate F's is less than Fs, the cut-off frequency of the low pass filter must be less than F's/2.

Here, the function sinc (t) ═ sin (tt)/sin (t) is introduced, and as the right side of fig. 2 is its waveform diagram, sinc (0) ═ 1, and others oscillate and attenuate endlessly to both sides of the origin, and sinc (t) ═ 0 at each integer position. Introducing ". x" denotes a convolution operation in digital signal processing, the formula can be expressed as (x.hs) (t). The formula can be understood as a superposition of a set of time-offset and amplitude-scaled sinc functions hs. Each time shifted sinc function is multiplied by the sample points and the results summed. Since each non-0 integer position sinc (nts) is 0, only the value of the sinc (0) 1 position sample point, i.e., the sample point itself, is retained. Therefore, when the sinc (t) is subjected to nTs time shifting, a group of sinc functions is obtained, and the convolution result of each sinc function and the sampling value is the sampling value at the nTs moment. These settlement results are then superimposed to equal the original sample data sequence x [ nTs ].

The right waveform of fig. 2 shows the process of restoring the reconstructed band-limited signal after the superposition of the sinc functions. There is a superposition of 5 sinc functions, each normalized to 1. If the sample data sequence is x ═ … …,0,1,1,1,1, 0 … …, when t is nTs, the sinc function waveform is exactly 0.

The summation process of equation (1) is practically impossible to implement. Since the impulse response of an ideal low-pass filter goes from negative infinity to positive infinity in a dozen kinds. Therefore, in the implementation, a part of sinc needs to be cut out to become a sequence with a wire length. There are many implementation techniques to make this filter a robust and simple window function. Fig. 3 shows a plot of the amplitude-frequency response of an ideal low-pass filter, corresponding to the result of the fourier transform of hs (t) above.

If hs (t) takes only 5 zero-crossings to either side, the stopband has only 20dB of rejection capability when rectangular windows are used to obtain the amplitude-frequency response as in the left graph of FIG. 4. When using the kaiser window, an amplitude-frequency response is obtained as shown in the right graph of fig. 4, a stop-band rejection of-80 dB can be obtained. The Kaiser window can have a parameter to adjust the stopband rejection capability at the expense of a large passband to stopband transition.

The algorithm of the application can calculate and restore the signal at any time.

As shown in fig. 5, the time register incorporates a sample value index n, a filter coefficient index l and an interpolation factor η, where time is an unsigned binary fixed point number in units of sample periods of the signal. There are three fields in the time register that hold 3 messages. The first field places the sample number n, which indicates that it is the nth sample in the sample's buffer; the second field places the filter coefficient index l and has a filter coefficient look-up table indicating the ith value of the look-up table. The third domain placement η, which is a value in the range of [0,1), represents the position of the moment of reconstruction between the nth sample point to the n +1 th sample point.

The three fields have respective word lengths of nn, nl and n eta bits. The buffer storing the input signal contains N2 ^ (nn) sampling points, and the filter coefficient lookup table places L2 ^ (nl) filter coefficients.

Fig. 6 shows a waveform diagram of a relationship between a sampling point and a sinc function at a certain time, which is implemented based on a Kaiser window, and has symmetrical coefficients on the left and right sides. Not only the coefficients of the right half of the FIR filter are stored, but also a table of differential sequences

h (l) is the coefficient of the previous filter, and this set of data can increase the computation speed when the reconstruction is resumed.

Assuming that the coefficient ρ of the sampling rate change is F's/Fs, each reconstructed sample point is calculated by formula (1), and the filter coefficient lookup table stores half of the coefficients, which are used in reverse and forward sequences. And obtaining a reconstruction value y (t) after the convolution calculation is finished.

Based on the band-limited interpolation algorithm of the principle, the ADC resampling processing of 24bit Delta-Sigma is provided, so that the effect of synchronous acquisition among devices is achieved, and the algorithm is realized on an FPGA and verified.

Hardware block diagram as shown in the following figure, a 24-bit ADC is connected to 1 FPGA. It provides a data interface for sample value reading, an oversampling clock, and a start control interface. Assuming that the sampling rate is Fs, the sampling interval Ts is 1/Fs. A set of sampled value data is available on the sampled value data interface every Ts time.

If the synchronization of the acquisition modules is to be achieved on the basis of an external clock, a resampling algorithm of the band-limited signal may be used. Firstly, the mainstream 24-bit ADCs on the market at present are all provided with anti-aliasing filters, so that the acquired signals are band-limited, the highest frequency is not higher than 1/2 of the oversampling clock frequency, the sampling rate Fs is reached through internal down-sampling, and the bandwidth of the signals is ensured to be less than Fs/2 through a low-pass extraction algorithm by an internal digital filter. This meets the requirements for band-limited signals.

And secondly, an oversampling clock, a sampling clock and a starting signal can be obtained on the FPGA, so that n, l and eta required by the realization of the band-limited interpolation algorithm can be obtained.

According to the method and the device, the resampling data with an external clock signal as a reference can be obtained by utilizing the strong online processing capacity of the FPGA chip. When multiple devices receive external clock signals with the same frequency and the same phase, the effect of synchronous acquisition of the multiple devices can be achieved. A specific operation flow of the invention is as follows, wherein, the ADC adopts a 24bit delta-sigma ADC acquisition card, and the specific processing flow is as follows:

1. and determining the sampling rate of the 24-bit delta-sigma ADC acquisition card according to the sampling rate F's of the external clock, wherein the most suitable condition is that Fs is F's. But the sampling rate of a typical 24bit delta-sigma ADC is not arbitrarily selectable, so the lowest sampling rate Fs above F's is chosen. Too high a sampling rate is unnecessary and consumes excessive memory and computational resources.

And 2, determining the word length of the coefficient and the number L of the coefficient to be 2^ nl according to the precision requirement by using the sampling rate determined in the step 1 and based on the principle of a sinc function through a low-pass filter. Lookup table for storing filter coefficients on FPGA

and 4, step 4: the FPGA chip receives the sampling data and enters a sampling value buffering part, new sampling data are stored, the earliest sampling data are popped out, the amount of the stored sampling data is ensured to accord with the capacity of a sampling domain of a time register, namely, the latest L (2 ^ nn) sampling values are reserved

And 5: and taking corresponding values from a sampling value buffer and coefficient lookup table according to the arrival time sequences n, l and eta of the external clock signal, the oversampling clock signal and the sampling data to perform convolution operation, thereby obtaining the resampled sampling value. Calculating a sampling value after resampling;

and (4) repeatedly executing the step (4) and the step (5), continuously obtaining resampled data which are generated based on the external clock, and therefore, when a plurality of devices use the same FPGA processing algorithm and the same source external clock signal, the synchronous acquisition can be realized.

The previous implementation of the interpolation process is a 1:1 interpolation process, i.e. the sampling rate and the external clock frequency are the same. This algorithm also supports N-fold interpolation, i.e. the frequency of the external clock may be 1/N of the target sampling rate. This reduces the clock frequency when sharing the clock between devices, which reduces the requirements on the transmission cable for deploying synchronous acquisition in a range of hundreds of meters. Yet another application scenario is where multiple devices are synchronized based on GPS. The GPS module can provide globally synchronous pulse-per-second signals, the frequency of the globally synchronous pulse-per-second signals is 1Hz, the resampling effect of any frequency can be achieved by matching with an N-time interpolation algorithm, the sampling values can be aligned with the pulse-per-second of the GPS, and erection of a wider synchronous acquisition system is achieved.

To sum up, the system and the method for realizing the cross-device synchronous data acquisition have the following beneficial effects:

2. The time register is used and coupled to receive the collected data, store the filter coefficient lookup table and represent the position between adjacent sampling points, and the time register stores and outputs the collected data at a high speed, so that the calculation speed during reconstruction recovery can be increased.

4. The method realizes that the interpolation process is 1:1 interpolation processing, namely the sampling rate is the same as the frequency of the external clock, and the algorithm also supports N times of interpolation, namely the frequency of the external clock can be 1/N of the target sampling rate. This reduces the clock frequency when sharing the clock between devices, which reduces the requirements on the transmission cable for deploying synchronous acquisition in a range of hundreds of meters.

While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention.

Claims

1. A system for synchronously acquiring data across devices is characterized by comprising: an external clock transmitting device, an Analog Digital Converter (ADC) and an FPGA chip,

the FPGA chip is connected with the external clock sending equipment and the ADC, the FPGA chip is used for receiving an external clock signal provided by the external clock sending equipment, and the FPGA chip generates sampling rate control based on an external clock sampling rate;

the ADC is coupled to receive parallel data and the sample rate control, the ADC generates an oversampling clock based on the sample rate control and an oversampling rate, and at the same time, the ADC converts the parallel data to an analog voltage level;

the FPGA chip is installed on the equipment needing to acquire data.

2. The system for achieving synchronous data acquisition across devices as claimed in claim 1, further comprising a GPS receiver responsible for providing a pulse signal of a synchronous clock to the acquired devices.

3. The system for enabling synchronized data collection across devices of claim 1, further comprising:

the low-pass filter is used for controlling the frequency of the collected signal not to be higher than a limit value based on the principle of a sinc function;

the sampling value cache receives the collected data and is used for reserving a latest sampling value; and

the time register comprises a sampling domain, a lookup table domain and a placement output domain, wherein the sampling domain is used for placing sampling points of input signals; the lookup table domain is used for storing the word length and the number of the sampling rate coefficients determined by the low-pass filter; the placement output field is used for indicating a time signal between adjacent sampling points.

4. The system for synchronously acquiring data among devices according to claim 1, wherein the ADC comprises a sampling data reading interface and a starting control interface, the sampling data reading interface is connected with the acquired devices, and the starting control interface is connected with the FPGA chip.

5. The system for achieving synchronous data acquisition across devices according to claim 1, wherein the FPGA chip is specifically configured to perform data acquisition and transmission once each time the external clock signal of a same source is received.

6. A method for realizing synchronous data acquisition across devices, which is applied to the synchronous acquisition system of any one of claims 1-5, and comprises the following steps:

7. The method for synchronously collecting data across devices according to claim 6, wherein the calculation of the sampling value in step 5 adopts the following algorithm:

wherein,

in the formula: x (t) is a sampling value of a continuous analog signal, t is a real number and is more than or equal to 0; ts is sampling interval time; n is 0,1, 2, … …, representing an integer, resulting in a time series x [ nTs ]; fs is a sampling rate, and Fs is 1/Ts; the frequency range of x (t) is within + -Fs/2.

8. The method for synchronously acquiring data across devices according to claim 7, wherein each reconstructed sampling value is calculated by formula (1) and then is calculated by a time register to obtain a reconstructed value y (t):

wherein,

in the formula: n is the sample value index and n is 0,1, 2, … …, representing an integer; l is the index of the filter coefficient in the time register; eta is an interpolation factor between the nth sampling point and the (n + 1) th sampling point at the reconstruction moment, and eta is more than or equal to 0 and less than 1; h (l) is the coefficient of the low-pass filter.

9. The method of claim 8, wherein the time register stores an input signal comprising N2 samples, and wherein the coefficient lookup table of the low pass filter places L2 filter coefficients.

10. The method for synchronously collecting data across devices according to claim 6, wherein in step 1, the required sampling rate is achieved through internal down-sampling, and the internal filter also passes through an algorithm of low-pass decimation, so that 1/2 that the signal bandwidth frequency is less than the sampling rate of the external clock is ensured.