CN114928243A - High duty ratio control system of step-down DC-DC switching power supply - Google Patents
High duty ratio control system of step-down DC-DC switching power supply Download PDFInfo
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- CN114928243A CN114928243A CN202210679292.0A CN202210679292A CN114928243A CN 114928243 A CN114928243 A CN 114928243A CN 202210679292 A CN202210679292 A CN 202210679292A CN 114928243 A CN114928243 A CN 114928243A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0006—Arrangements for supplying an adequate voltage to the control circuit of converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
The invention discloses a high duty ratio control system of a buck DC-DC switching power supply, which is additionally provided on the basis of the basic structure of the switching power supply and comprises an LDO (low dropout regulator), a diode D2 for charging a capacitor C1 by the LDO, an error amplifier, a current comparator, an OR gate, a pulse generator, an RS (read-only memory) latch and an undervoltage locking circuit for detecting the voltage VBS (voltage source) at two ends of the capacitor C1. The undervoltage locking circuit detects the voltage VBS at two ends of the C1, when the voltage is insufficient, the charging switch tube M1 is turned off briefly, a capacitor C1 which provides a voltage stabilizing power supply for the driving circuit is charged during the period of turning off M1 to recover the power supply voltage of the driving circuit, and then the M1 is turned on again to achieve high duty ratio conduction work of the NMOS type charging switch tube.
Description
Technical Field
The invention relates to a switching power supply, in particular to a high duty ratio control system of a step-down DC-DC switching power supply, and belongs to the technical field of integrated circuit power supply management core design.
Background
In the step-down DC-DC switching power supply chip, some applications can have the condition that the input voltage is lower than the set output voltage, the switching power supply needs to be in a 100% duty cycle working state, namely, the charging switching tube is in a long conduction state, and the output voltage is equal to the input voltage at the moment. The low voltage-withstanding voltage-reducing DC-DC switching power supply chip is generally designed by adopting low-voltage devices, the charging switching tube adopts 5V PMOS, the high duty ratio control is easy to realize, but in the high voltage-withstanding voltage-reducing DC-DC switching power supply chip, the charging switching tube generally adopts high-voltage NMOS devices, a driving circuit of the charging switching tube and a partial circuit of a controller are respectively powered by two independent power supplies, the power voltage of the driving circuit is continuously reduced when the charging switching tube is conducted for a long time, when the voltage is reduced to be below the required minimum working voltage, the problem that the normal conduction of the NMOS switching tube cannot be maintained can be faced, and the NMOS switching tube can be continuously and stably conducted for a long time in a high duty ratio mode by reasonable control.
Disclosure of Invention
The invention aims to provide a high duty ratio control system of a step-down DC-DC switching power supply, which can help the step-down DC-DC switching power supply adopting an NMOS charging switching tube to keep high duty ratio operation when the input voltage is lower than the set output voltage.
In order to realize the purpose, the invention adopts the following technical scheme: a high duty ratio control system of a voltage-reducing DC-DC switching power supply comprises an NMOS charging switching tube M1, a driving circuit for driving the switching tube M1, a capacitor C1 for providing a voltage-stabilizing power supply for the driving circuit, a freewheeling diode D1, an inductor L1, an output filter capacitor C2, and feedback proportional resistors R1 and R2; the gate of the NMOS charging switch tube M1 is connected to the output of the driving circuit, the drain of the NMOS charging switch tube M1 is connected to the power supply VIN, the source and the substrate of the NMOS charging switch tube M1, the cathode of the freewheeling diode D1 and one end of the inductor L1 are connected to the floating ground SW, the capacitor C1 and the driving circuit are bridged between the floating power supply BOOT and the floating ground SW, the voltage between the floating power supply BOOT and the floating ground SW is VBS, the voltage of the floating ground SW changes between the power supply VIN and the ground GND, the anode of the freewheeling diode D1 is grounded GND, the other end of the inductor L1 is connected to one end of the filter capacitor C2 and one end of the resistor R1 and serves as the output voltage terminal of the switching power supply, the other end of the filter capacitor C2 is grounded VOUT, the other end of the resistor R1 is connected to one end of the resistor R2 and generates the feedback voltage FB, and the other end of the resistor R2 is grounded;
the method is characterized in that: the high duty ratio control system is additionally arranged and comprises an oscillator LDO, a diode D2 for charging a capacitor C1 by the oscillator LDO, an error amplifier, a current comparator, an OR gate, a pulse generator, an RS latch and an under-voltage locking circuit for detecting voltage VBS at two ends of the capacitor C1, wherein the under-voltage locking circuit is bridged between a floating power BOOT and a floating ground SW, the oscillator LDO is powered by a power VIN, the output of the oscillator LDO is connected with the anode of the diode D2, the cathode of the diode D2 is connected with the floating power BOOT, the output of the under-voltage locking circuit is connected with one end of the OR gate and the input end of the pulse generator or the other end of the gate is connected with the output of the current comparator, the positive input end of the current comparator is connected with the floating ground SW and used for detecting current (inductance current IL) flowing through an NMOS charging switch tube M1, the negative input end of the current comparator is connected with the output of the error amplifier, the positive input end of the error amplifier is connected with reference voltage VREF, the negative input end of the error amplifier is connected with a feedback voltage FB generated by voltage division of a resistor R1 and a resistor R2, the output of the OR gate is connected with the input end R of the RS latch, the output of the pulse generator is connected with the input end S of the RS latch, and the output end Q of the RS latch is connected with the input end of the driving circuit; in the circuit, an oscillator LDO, an error amplifier, a current comparator, an OR gate, a pulse generator and an RS latch are all in the prior art.
When the input power voltage VIN is lower than the set output voltage VOUT, the feedback voltage FB is always lower than the reference voltage VREF, the reference current of the negative input end of the current comparator controlled by the output of the error amplifier is in a maximum current state, the inductive current IL flowing through the NMOS charging switch tube M1 is always lower than the reference current of the negative input end of the current comparator, the comparison result of the current comparator does not reset and trigger the RS latch to turn off the charging switch tube M1, the charging switch tube M1 is kept in a conducting state, because the internal circuit comprising the driving circuit, the undervoltage locking circuit and other auxiliary circuits has the current to continuously consume the charge in the capacitor C1, the voltage VBS at two ends of the capacitor C1 is gradually reduced, the undervoltage locking circuit detects the voltage VBS at two ends of the C1, the undervoltage locking circuit sends a reset signal when detecting that the VBS is lower than the minimum power supply voltage VBSL required when the driving circuit works normally, the reset signal and the result of the current comparator are subjected to logical OR operation and then reset and trigger the RS latch, the charging switch tube M1 is turned off, a reset signal is simultaneously input to the pulse generator, the pulse generator is prevented from generating a set signal, the set signal can set the RS latch and restart the charging switch tube M1, after the charging switch tube M1 is turned off, the SW voltage of the node is dropped to the ground potential GND, the oscillator LDO charges the capacitor C1 through the diode D2, when the undervoltage locking circuit detects that VBS rises and exceeds the minimum supply voltage VBSL required by the driving circuit in normal work, the reset signal disappears, the pulse generator is allowed to be set to trigger the RS latch, the charging switch tube M1 is restored to be in a conducting state, and the charging switch tube M1 is periodically conducted for a long time through the high duty ratio control system.
Preferably, the undervoltage locking circuit comprises a constant current source I1, a PMOS transistor PM1, a PMOS transistor PM2, a PMOS transistor PM3, a PMOS transistor PM4, an NMOS transistor NM1, an NMOS transistor NM2, an NMOS transistor NM3, an inverter INV1, an inverter INV2 and a resistor R3; the input end of the constant current source I1 is connected with the drain and the gate of the PMOS tube PM1 and the gate of the PMOS tube PM2 and the gate of the PMOS tube PM3, the source and the substrate of the PMOS tube PM1 and the source and the substrate of the PMOS tube PM2 and the source and the substrate of the PMOS tube PM3 are both connected with the power supply BOOT, the drain of the PMOS tube PM2 is connected with the substrate and the source of the PMOS tube PM4, the gate and the drain of the PMOS tube PM4 are connected with the gate and the drain of the NMOS tube NM1 and the gate of the NMOS tube NM2, the source and the substrate of the NMOS tube NM1 are connected with one end of the resistor R3 and the drain of the NMOS tube NM3, the drain of the PMOS tube PM3 is connected with the drain of the NMOS tube NM2 and used as the output end of the under-voltage locking circuit to connect with one end of the OR gate and the input end of the pulse generator and simultaneously connected with the input end of the inverter INV1, the output end of the inverter INV1 is connected with the input end of the inverter INV2, the output end of the inverter INV 3939 2 is connected with the input end of the inverter NM3, the output end of the inverter NM1 and the NMOS tube NM2 and the substrate of the NMOS tube NM3, the NMOS tube PM2, the output end of the NMOS tube PM3 and the NMOS tube PM 362 are connected with the input end of the substrate, The other end of the resistor R3 and the source and substrate of the NMOS transistor NM2 are both connected to a floating ground SW.
Furthermore, the PMOS transistor PM1, the PMOS transistor PM2 and the PMOS transistor PM3 are in a current mirror relationship, and the size ratio is PM1: PM2: PM 3: 1:2: 1; the size ratio of the NMOS tube NM1 to the NMOS tube NM2 is NM1 to NM2 as 1: 1.
The invention has the advantages and obvious effects that: on the basis of the basic structure of the switching power supply, the high duty ratio control system is additionally arranged, the voltage VBS at two ends of the C1 is detected through the under-voltage locking circuit, when the voltage is insufficient, the charging switching tube M1 is turned off temporarily, a capacitor C1 which provides a voltage stabilizing power supply for the driving circuit is charged during the period of turning off M1, the power supply voltage of the driving circuit is recovered, then the M1 is turned on again, and the high duty ratio conduction work of the NMOS type charging switching tube is realized.
Drawings
FIG. 1 is a circuit diagram of the present invention;
FIG. 2 is one implementation of the under-voltage lockout circuit employed in FIG. 1;
fig. 3 is a graph of voltage waveforms during operation of fig. 1.
Detailed Description
Fig. 1 is a control system for realizing high duty cycle operation of an NMOS type charging switching tube based on a control architecture of an existing step-down DC-DC switching power supply. The switching power supply part comprises an NMOS charging switching tube M1, a driving circuit, a capacitor C1 for providing a regulated power BOOT for the driving circuit, a freewheeling diode D1, an inductor L1, an output filter capacitor C2 and feedback proportional resistors R1 and R2. When the input voltage VIN is lower than the set output voltage VOUT, the feedback voltage FB is correspondingly lower than the reference voltage VREF, the output voltage of the error amplifier is in the highest voltage state, the inductive current corresponding to the flip point of the controlled current comparator is in the maximum current value ILIM, the current IL flowing through M1 is equal to the output current IOUT and is lower than ILIM, the output result of the current comparator is not flipped, the latch is not reset to turn off M1, at the moment, M1 is kept in the conducting state, the voltage VBS at two ends of the capacitor C1 is gradually reduced because the current in the internal circuit continuously consumes the charge stored in C1, when the undervoltage locking circuit detects that the voltage VBS is reduced to the minimum power supply voltage VBSL required when the driving circuit works normally, the reset signal is sent out, the RS latch is reset, then the charging switch tube M1 is turned off, and the pulse generator is prevented from generating the set signal at the same time, the latch will not be set, the SW node voltage drops to GND after M1 turns off, then the LDO module will charge the capacitor C1 through the diode D2, when the under-voltage-locked circuit detects that the VBS voltage rises to VBSH voltage higher than the VBSL voltage, the reset signal is released, and the pulse generator module is allowed to send out the set pulse, M1 is turned back on after the latch is set, the charging switch on-time Ton is determined by the under-voltage-locked circuit trip point voltages VBSH and VBSL, the capacitor C1 and the discharging current Idis of the capacitor C1, the on-time calculation formula Ton (VBSH-VBSL) C1/Idis, the M1 off-time Toff is determined by the under-voltage-locked circuit trip point voltages VBSH and VBSL, the capacitor C1 and the current Icharge of the LDO charging the capacitor C1, the off-time calculation formula Toff (VBSH-Icharge) C1/1, the ratio of the on-time to the off-time is approximate to the charging current of the capacitor C1, and ensuring that Ichar is far larger than Idis, the high duty ratio working mode with high proportion of on-time and off-time of the charging switch tube can be realized.
Fig. 2 is a specific implementation of the under-voltage lockout circuit adopted by the present invention, which includes a constant current source I1, a constant current source I1 for biasing the PMOS transistor PM1, an output terminal SW of the constant current source I1, an input terminal SW of the constant current source I1, a source terminal and a drain terminal of the PMOS transistor PM1, a source terminal and a substrate terminal BOOT of the PM1, a gate terminal of the PMOS transistor PM2 and the PM3 connected to the gate terminal of the PM1, a source terminal and a substrate terminal of the PM2 connected to the power source BOOT, a drain terminal of the PM2 connected to the substrate and the source terminal of the PM2, a drain terminal of the PM2 connected to the substrate and the drain terminal of the NMOS transistor NM2, the PM2, the drain terminal of the NM2 connected to the NMOS transistor NM2, the drain terminal of the PM2 connected to the drain terminal of the PM2, the drain terminal of the PM2 connected to the drain terminal of the PM2, the size ratios of NM1 and NM2 are NM1: NM 2:1, the drains of PM3 and NM2 are commonly connected to the input end of an inverter INV1, the output end of INV1 is connected to the input end of the inverter INV2, the output end of INV2 is connected to the gate of NM3, the drain of NM3 is connected to one end of a resistor R3, the substrate and the source of NM3 are connected to SW, the width-to-length ratio of NM3 needs to be sufficiently large, NM3 works in a deep linear region conducting state when INV2 outputs logic "high", the conducting resistance is ensured to be much smaller than that of R3, the drain voltages of PM3 and NM2 are fed back to the input end of the inverter INV1 as detection output results, UVLO _ READYb is fed back to the input end of the inverter INV1, and the resistor R3 can be approximately short-circuited by controlling NM 3.
The working principle is as follows: when the power supply voltage VBS is low, the output result UVLO _ READYb is logic "1", NM3 is in a linear region on state, the resistor R3 is approximately short-circuited to SW, NM1 and NM2 are approximately in a mirror image relationship, the current when the PM3 saturation region operates is IDS1, IDS1 is equal to the current value of the constant current source I1, as the VBS voltage rises, the gate voltages of NM1 and NM2 also rise, and when the NM2 current exceeds the PM3 current 1, the output result UVLO _ READYb flips to logic "0", it is considered that the power supply voltage meets the requirement, the current flowing through NM1 is also IDS1 at this time, the voltage corresponding to the VBS flipping point is VBSH ═ VGS2+ VGS4_1, wherein VGS2 is the gate-source voltage difference required by the NM2 operating in the saturation region flowing through IDS1 current, VGS4_1 is the gate-source voltage difference required by PM4 IDS1 operating in the saturation region, and MOS 1/2 μ I · MOS 82 flowing through the MOS 1/2 μ I-V — V β -V ox ·W/L·(V GS -V th ) 2 It can be determined that the voltage at the VBSH turning point corresponds to the specific width-to-length ratio of NM2 and PM4, the smaller the size of the width-to-length ratio of NM2 and PM4, the higher the corresponding voltage at the turning point, the higher the voltage at the UVLO _ READYb is turned to logic "0", and then NM3 is in the cut-off state, and at this time, the NM1 source is connected to SW through a resistor R3, in this operating state, the gate voltage of NM1 is IDS2 when the gate voltage of NM1 is VGS2, IDS2 is smaller than IDS1 due to the series connection of resistor R3, as the VBS voltage drops, the gate voltage of NM1 also drops, when the gate voltages of NM1 and NM1 drop below VGS 1, and the current of NM1 is lower than PM1, the output result lo _ READYb is turned to logic "1", the power source BOOT is considered to be in the undervoltage state, the voltage at the VBS turning point is in which the VBS voltage is vgsl + VGS 1, wherein the voltage of NM 5872 is smaller than the gate voltage at the operating region IDS1, and the gate voltage of NM1 is smaller than the gate voltage of the gate 72, and the gate voltage of PM1 is smaller than the gate 72, and the gate voltage of the gate 72, and the gate voltage of the gate 72 is considered to be smaller than the gate voltage of the gate 72, and the gate voltage of the gate 72 is lower than the gate voltage of the gate 72, therefore, the detection of the hysteresis of the BOOT voltage can be realized, and the difference between IDS1 and IDS2 can be adjusted by adjusting the resistance value of the resistor R3, so as to adjust the difference between VGS4_1 and VGS4_2, and adjust the hysteresis of the detection of the voltage VBS.
Fig. 3 shows a voltage waveform diagram of the main circuit of the present invention when it works, in which 4 complete switching cycles are shown, the output signal UVLO _ READYb of the under-voltage lock circuit in the initial state is logic "0", the NMOS charge switch tube M1 is in the on state, the SW voltage is equal to the VIN voltage, the supply voltage VBS of the driving circuit of M1 is gradually decreased, when the VBS is lower than VBSL, the output signal UVLO _ READYb of the under-voltage lock module is inverted to logic "1", the switch tube M1 is turned off, the pulse generator module stops generating the set pulse signal, the SW voltage is decreased to the GND voltage, the LDO module charges the capacitor C1, the VBS voltage gradually increases, when the VBS exceeds VBS, the output signal UVLO _ READYb of the under-voltage lock circuit is inverted to logic "0", the pulse generator generates the set pulse signal to restore the conduction of the switch tube M1, it can be seen that the M1 conduction time Ton is determined by the time required by the capacitor C1 voltage to discharge VBSH to sl from VBSH, the off-time Toff is determined by the time required for the voltage VBS of the capacitor C1 to charge from VBSL to VBSH.
Claims (4)
1. A high duty ratio control system of a step-down DC-DC switching power supply is disclosed, wherein the basic structure of the step-down DC-DC switching power supply comprises an NMOS charging switching tube M1, a driving circuit for driving the switching tube M1, a capacitor C1 for providing a voltage-stabilized power supply for the driving circuit, a freewheeling diode D1, an inductor L1, an output filter capacitor C2, and feedback proportional resistors R1 and R2; the gate of the NMOS charging switch tube M1 is connected to the output of the driving circuit, the drain of the NMOS charging switch tube M1 is connected to the power supply VIN, the source and the substrate of the NMOS charging switch tube M1, the cathode of the freewheeling diode D1 and one end of the inductor L1 are connected to the floating ground SW, the capacitor C1 and the driving circuit are bridged between the floating power supply BOOT and the floating ground SW, the voltage between the floating power supply BOOT and the floating ground SW is VBS, the voltage of the floating ground SW changes between the power supply VIN and the ground GND, the anode of the freewheeling diode D1 is grounded GND, the other end of the inductor L1 is connected to one end of the filter capacitor C2 and one end of the resistor R1 and serves as the output voltage terminal of the switching power supply, the other end of the filter capacitor C2 is grounded VOUT, the other end of the resistor R1 is connected to one end of the resistor R2 and generates the feedback voltage FB, and the other end of the resistor R2 is grounded;
the method is characterized in that: the high duty ratio control system is additionally arranged and comprises an oscillator LDO, a diode D2 for charging a capacitor C1 by the oscillator LDO, an error amplifier, a current comparator, an OR gate, a pulse generator, an RS latch and an under-voltage locking circuit for detecting voltage VBS at two ends of the capacitor C1, wherein the under-voltage locking circuit is bridged between a floating power supply BOOT and a floating ground SW, the oscillator LDO is powered by a power supply VIN, the output of the oscillator LDO is connected with the anode of the diode D2, the cathode of the diode D2 is connected with the floating power supply BOOT, the output of the under-voltage locking circuit is connected with one end of the OR gate and the input end of the pulse generator or the other end of the OR gate is connected with the output of the current comparator, the positive input end of the current comparator is connected with the floating ground SW and used for detecting the current (inductance current IL) flowing through an NMOS charging switch tube M1, the negative input end of the current comparator is connected with the output of the error amplifier, and the positive input end of the error amplifier is connected with a reference voltage VREF, the negative input end of the error amplifier is connected with a feedback voltage FB generated by voltage division of a resistor R1 and a resistor R2, the output of the OR gate is connected with the input end R of the RS latch, the output of the pulse generator is connected with the input end S of the RS latch, and the output end Q of the RS latch is connected with the input end of the driving circuit;
when the input power voltage VIN is lower than the set output voltage VOUT, the feedback voltage FB is always lower than the reference voltage VREF, the reference current of the negative input end of the current comparator controlled by the output of the error amplifier is in a maximum current state, the inductive current IL flowing through the NMOS charging switch tube M1 is always lower than the reference current of the negative input end of the current comparator, the comparison result of the current comparator does not reset and trigger the RS latch to turn off the charging switch tube M1, and the charging switch tube M1 is kept in a conducting state, because the internal circuit comprising the driving circuit, the undervoltage locking circuit and other auxiliary circuits has current to continuously consume the charge in the capacitor C1, the voltage VBS at two ends of the capacitor C1 is gradually reduced, the undervoltage locking circuit detects the voltage VBS at two ends of C1, the undervoltage locking circuit sends out a reset signal when detecting that the VBS is lower than the minimum power supply voltage VBSL required when the driving circuit normally works, the reset signal and the result of the current comparator are subjected to logical OR operation, and then reset and trigger the RS latch, the charging switch tube M1 is turned off, a reset signal is simultaneously input to the pulse generator, the pulse generator is prevented from generating a set signal, the set signal can set the RS latch and turn on the charging switch tube M1 again, after the charging switch tube M1 is turned off, the SW voltage of the node falls to the ground potential GND, the oscillator LDO charges the capacitor C1 through the diode D2, when the undervoltage locking circuit detects that VBS rises and exceeds the minimum supply voltage VBSL required when the driving circuit works normally, the reset signal disappears, the pulse generator is allowed to be set to trigger the RS latch, the charging switch tube M1 is recovered to be in a conducting state, and the charging switch tube M1 is periodically conducted for a long time through the high duty ratio control system.
2. The high duty cycle control system of a step-down DC-DC switching power supply of claim 1, wherein: the undervoltage locking circuit comprises a constant current source I1, a PMOS tube PM1, a PMOS tube PM2, a PMOS tube PM3, a PMOS tube PM4, an NMOS tube NM1, an NMOS tube NM2, an NMOS tube NM3, an inverter INV1, an inverter INV2 and a resistor R3; the input end of a constant current source I1 is connected with the drain and the grid of a PMOS pipe PM1, the grid of the PMOS pipe PM2 and the grid of a PMOS pipe PM3, the source and the substrate of a PMOS pipe PM1, the source and the substrate of a PMOS pipe PM2, the source and the substrate of a PMOS pipe PM3 are both connected with a power supply BOOT, the drain of the PMOS pipe PM2 is connected with the substrate and the source of a PMOS pipe PM4, the gate and the drain of the PMOS pipe PM4 are connected with the gate and the drain of an NMOS pipe NM1 and the gate of an NMOS pipe NM2, the source of the NMOS pipe NM1 and the substrate are connected with one end of a resistor R3 and the drain of an NMOS pipe NM3, the drain of the PMOS pipe PM3 is connected with the drain of the NMOS pipe NM2 and serves as the output end of an under-voltage locking circuit, one end of an OR gate and the input end of a pulse generator are connected with the input end of an inverter INV1 at the same time, the output end of the inverter INV1 is connected with the input end of an INV2, the output end of an inverter NM2 is connected with the gate of an NMOS pipe NM 56, the output end of the inverter 828653, the constant current source of the inverter 828653 and the source of the NMOS pipe PM 8427 are connected with the output end of the NMOS pipe PM 8427 and the substrate 3, The other end of the resistor R3 and the source and substrate of the NMOS transistor NM2 are connected to a floating ground SW.
3. The high duty cycle control system of a step-down DC-DC switching power supply of claim 2, wherein: the PMOS tube PM1, the PMOS tube PM2 and the PMOS tube PM3 are in a current mirror relationship, and the size ratio is PM1: PM2: PM 3: 1:2: 1.
4. The high duty cycle control system of a step-down DC-DC switching power supply of claim 2, wherein: the size ratio of the NMOS tube NM1 to the NMOS tube NM2 is NM1 to NM2 as 1: 1.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210679292.0A CN114928243A (en) | 2022-06-15 | 2022-06-15 | High duty ratio control system of step-down DC-DC switching power supply |
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| CN202210679292.0A CN114928243A (en) | 2022-06-15 | 2022-06-15 | High duty ratio control system of step-down DC-DC switching power supply |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115395482A (en) * | 2022-10-27 | 2022-11-25 | 深圳芯能半导体技术有限公司 | Under-voltage locking circuit and half-bridge switch driving circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115395482A (en) * | 2022-10-27 | 2022-11-25 | 深圳芯能半导体技术有限公司 | Under-voltage locking circuit and half-bridge switch driving circuit |
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