CN114915292A - Successive approximation type analog-digital converter circuit based on data weighted average algorithm - Google Patents

Abstract

The application relates to a successive approximation type analog-to-digital converter circuit based on a data weighted average algorithm. The circuit comprises: a quantizer for generating a digital signal from an input analog signal; and the data weighted average module is electrically connected with the quantizer and used for generating a data weighted average output signal according to the digital signal. By adopting the circuit, when the precision of the successive approximation type analog-digital converter is required to be improved and a multi-bit quantizer is adopted, the nonlinear error of the feedback digital-analog converter is effectively reduced, low-frequency noise is pushed to high frequency, and finally the low-frequency noise can be filtered by a digital low-pass filter, so that the performance of the successive approximation type analog-digital converter is improved, the required hardware resource is small, the circuit is simple and easy to realize, and the integrated application of a chip is facilitated.

Description

Successive approximation type analog-digital converter circuit based on data weighted average algorithm

Technical Field

The present application relates to the field of integrated circuit technologies, and in particular, to a successive approximation analog-to-digital converter circuit based on a data weighted average algorithm.

Background

The successive approximation type analog-digital converter has the advantages of low power consumption, high resolution, high precision, small size and the like, and is widely applied to various fields of the Internet of things, digital communication, automobile electronic sensing, digital audio and video and the like. In recent years, due to advances in the semiconductor and integrated circuit technology level, higher demands have been made on the power consumption, accuracy, and the like of the analog-to-digital converter.

In order to improve the precision of the successive approximation analog-digital converter under the conditions of lower order number and not too high oversampling rate, a method of a multi-bit quantizer is adopted. But the multi-bit quantizer increases the complexity of the analog-to-digital converter, requires the multi-bit digital-to-analog converter for feedback to have sufficient accuracy to guarantee the accuracy of the final quantization and introduces the non-linear error of the feedback multi-bit digital-to-analog converter, increases the low frequency noise and reduces the signal-to-noise ratio.

Disclosure of Invention

Therefore, in order to solve the above technical problem, it is necessary to provide a successive approximation type analog-to-digital converter circuit based on a data weighted average algorithm, which optimizes the analog-to-digital converter by a digital correction method to improve the accuracy of the analog-to-digital converter.

To achieve the above and other objects, a first aspect of the present application provides a successive approximation analog-to-digital converter circuit based on a data weighted average algorithm, the circuit comprising:

a quantizer for generating a digital signal from an input analog signal;

and the data weighted average module is electrically connected with the quantizer and used for generating a data weighted average output signal according to the digital signal.

In the successive approximation type analog-to-digital converter circuit based on the data weighted average algorithm in the embodiment, firstly, the quantizer converts the analog signal into the digital signal, and then the data weighted average module enables the weight of each unit of data to be the same, thereby ensuring that the probability of selecting the capacitor in the subsequent circuit is the same. The nonlinear error of the feedback digital-to-analog converter is effectively reduced, the low-frequency noise is pushed to high frequency, and finally the low-frequency noise can be filtered by a digital low-pass filter, so that the performance of the successive approximation analog-to-digital converter is improved.

In one embodiment, the data weighted average module further comprises:

and the thermometer code coding module is electrically connected with the quantizer and used for generating thermometer codes according to the digital signals.

In one embodiment, the data weighted average module further comprises:

and the accumulator is electrically connected with the quantizer and used for generating a shift selection control signal according to the digital signal.

In one embodiment, the data weighted average module further comprises:

and the barrel-shaped shifter is electrically connected with the thermometer code coding module and the accumulator and is used for generating a first output signal according to the thermometer code and the shift selection control signal.

In one embodiment, the accumulator comprises:

the adder is electrically connected with the quantizer and used for summing the digital signals to generate a first shift signal;

and the first register is electrically connected with the adder and used for storing the first shifting signal and generating a shifting selection control signal.

In one embodiment, the data weighted average module further comprises:

and the second register is electrically connected with the barrel shifter and used for storing the first output signal to generate a data weighted average output signal.

In one embodiment, the first register comprises a first-in-first-out register;

the second register comprises a first-in-first-out register.

A second aspect of the application provides an analog to digital converter comprising a successive approximation analog to digital converter circuit based on a data weighted averaging algorithm as described in any of the embodiments of the application.

A third aspect of the present application provides a data weighted average algorithm for controlling the actions of the analog-to-digital converter described in the embodiments of the present application, the method comprising:

generating a digital signal according to the obtained analog signal;

generating a thermometer code and a shift selection control signal according to the digital signal;

and generating a data weighted average output signal according to the thermometer code and the shift selection control signal.

In one embodiment, the thermometer code and the shift selection control signal generate a shift signal through a barrel shifter and determine a shift result.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a successive approximation analog-to-digital converter circuit based on a data weighted average algorithm according to an embodiment of the present application;

FIG. 2 is a signal timing diagram of a successive approximation analog-to-digital converter circuit based on a data weighted average algorithm according to an embodiment of the present application;

FIG. 3 is a schematic flow chart of a data weighted average algorithm provided in an embodiment of the present application;

fig. 4 is a schematic diagram of a data weighted average algorithm provided in an embodiment of the present application.

Description of the reference numerals:

10. a quantizer; 20. a data weighted average module; 21. a thermometer code encoding module; 22. an accumulator; 221. an adder; 222. a first register; 23. a barrel shifter; 24. a second register.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another.

It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or be connected to the other element through intervening elements. Further, "connection" in the following embodiments is understood to mean "electrical connection", "communication connection", or the like, if there is a transfer of electrical signals or data between the connected objects.

As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

As described in the background, in order to improve the accuracy of the successive approximation adc under the conditions of a lower order and not too high oversampling rate, a method of using a multi-bit quantizer is adopted, the multi-bit quantizer can increase the signal-to-noise ratio, make the system stable easily, generate less harmonic components, and make the down-sampling filter relatively simple, but the multi-bit quantizer increases the complexity of the adc, and requires a multi-bit DAC for feedback to have sufficient accuracy to ensure the accuracy of the final quantization. However, while improving the accuracy of the analog-to-digital converter, non-linearity errors of the feedback multi-bit DAC are also introduced, which must be optimized by either digital or analog correction methods.

Currently, the most commonly used digital correction technique is Dynamic Element Matching (DEM) technique, which includes single Level Averaging (indicative Level Averaging), Random Selection (Random Selection), and Data Weighted Averaging (DWA).

The DWA algorithm is a DEM technology with simpler hardware implementation and better performance, and is also called as an element rotation method. The DWA algorithm module can be realized by a Verilog digital circuit, the circuit structure is simple, the area is small, the power consumption is low, and the influence of nonlinear errors on the performance of the analog-to-digital converter can be effectively reduced.

The conventional DAC modulator uses thermometer codes, but the weight of each data bit of the thermometer codes is different, the low-order weight is large, the high-order weight is small, the low-order selection probability is large when the DAC modulator selects a capacitor, the high-order selection probability is small, mismatch errors are caused by nonuniform capacitor selection, the output of the DAC is greatly influenced, and the performance of the analog-digital converter is finally influenced.

Based on this, please refer to fig. 1, in an embodiment of the present application, a successive approximation type analog-to-digital converter circuit based on a data weighted average algorithm is provided, the circuit includes a quantizer 10 and a data weighted average module 20; a quantizer 10 for generating a digital signal from an input analog signal; a data weighted average module 20 is electrically connected to the quantizer 10 for generating a data weighted average output signal from the digital signal.

Specifically, in the successive approximation analog-to-digital converter circuit based on the data weighted average algorithm of the above embodiment, the analog signal is first converted into a digital signal by the quantizer 10, for example, in some embodiments, the analog signal is quantized into a 5-bit digital signal by the multi-bit quantizer 10. And then the weight of each bit of data is the same through the data weighted average module 20, so that the probability of selecting the capacitor of the subsequent circuit is the same. The nonlinear error of the feedback digital-to-analog converter is effectively reduced, the harmonic component in the low-frequency bandwidth of the analog-to-digital converter is greatly reduced, the low-frequency noise is pushed to high frequency, and finally the low-frequency noise can be filtered by a digital low-pass filter, so that the performance of the successive approximation analog-to-digital converter is improved.

The data weight averaging technique is also referred to as element rotation. The operating principle is to select each element by cycling so that after a number of clock cycles each element has been selected with the same probability. Therefore, the nonlinear noise of the DAC can be pushed to a higher frequency band from a low-frequency signal bandwidth and then filtered by a digital filter at the later stage.

Referring to fig. 1, the data weighted average module 20 further includes a thermometer code encoding module 21, and the thermometer code encoding module 21 is electrically connected to the quantizer 10 and configured to generate a thermometer code according to the digital signal.

Specifically, i digital signal is converted into 2 by thermometer code coding module 21 ⁱ Thermometer codes, e.g. 5bit digital signals can be converted to 2 by thermometer code encoding module 21 ⁵ The 2-system code is converted into the thermometer code, so that the interference resistance, the resolution capability and the precision can be improved.

In one embodiment, the data weighted average module 20 further comprises an accumulator 22, wherein the accumulator 22 is electrically connected to the quantizer 10 for generating a shift selection control signal according to the digital signal.

Specifically, the 5-bit digital signal is generated by the accumulator 22 and registers a pointer. Accumulator 22 is a register that stores intermediate results generated by the computations. Without a register like the accumulator 22, the result has to be written back to memory after each calculation (addition, multiplication, shift, etc.), perhaps immediately read back. However, access to main memory is slower than access from the arithmetic logic unit to the accumulator 22 with a direct path.

In one embodiment, the data weighted average module 20 further comprises a barrel shifter 23, and the barrel shifter 23 is electrically connected to both the thermometer code encoding module 21 and the accumulator 22 for generating a first output signal according to the thermometer code and the shift selection control signal.

Specifically, the pointer generated by the accumulator 22 and 32 generated by the thermometer code encoding module 21 collectively determine the output of the DWA algorithm for the thermometer code. A barrel shifter is a digital circuit that shifts a data word by a specified number of bits in one clock cycle. The barrel shifter may be implemented as a series of data selectors, with the output of one data selector being the input of the other, depending on the number of bits to be shifted. For example, taking a four-bit barrel shifter as an example, the inputs are a, B, C and D, the barrel shifter can obtain DABC, CDAB or BCDA from the input ABCD, all bits of information are left, and only the positions are changed in a circular combination, and the barrel shifter has many different applications and is an important component in a microprocessor.

In one embodiment, the accumulator 22 includes an adder 221 and a first register 222; the adder 221 is electrically connected to the quantizer 10, and is configured to perform a summation operation on the digital signals to generate a first shifted signal; the first register 222 is electrically connected to the adder 221, and is configured to store the first shift signal and generate a shift selection control signal.

Specifically, the adder 221 is directly connected to the 5-bit quantizer 10, so that the five-bit adder 221 can be selected, the complexity of the circuit can be reduced, and the cost can be saved. The adder 221 is a device that generates a sum of numbers. The device with the addend and the summand as the addend as inputs and the sum and the carry as outputs is a half adder. If the addend, the summand, and the carry of the low order bits are inputs, and the sum and the carry are outputs, a full adder is provided. Often used as computer arithmetic logic units to perform logical operations, shifts, and instruction calls. In electronics, the adder 221 is a digital circuit that performs addition calculation of a number. The ternary code, the main adder 221, operates in binary.

Specifically, the register functions to store binary codes, which are formed by combining flip-flops having a storage function. One flip-flop can store 1-bit binary codes, so a register for storing n-bit binary codes needs to be formed by n flip-flops. Registers can be divided into two broad categories, basic registers and shift registers, according to their functions. The basic registers can only be fed with data in parallel and can only be output in parallel. The data in the shift register can be shifted to the right or left bit by bit in sequence under the action of shift pulses, and the data can be input in parallel and output in parallel, can be input in series and output in series, can be input in parallel and output in series, or can be input in series and output in parallel, so that the method is very flexible and has wide application.

In one embodiment, the data weighted average module 20 further comprises a second register 24, and the second register 24 is electrically connected to the barrel shifter 23 for storing the first output signal to generate a data weighted average output signal.

In one embodiment, the first register 222 comprises a first-in-first-out register;

the second register 24 comprises a first-in-first-out register.

Specifically, a First-in First-out register (FIFO) is simply referred to as FIFO. Due to the rapid development of microelectronic technology, the capacity of a new generation FIFO chip is larger and smaller, and the price is cheaper and cheaper. As a new large-scale integrated circuit, the FIFO chip is gradually applied to high-speed data acquisition, high-speed data processing, high-speed data transmission, and multi-machine processing systems due to its characteristics of flexibility, convenience, and high efficiency. The FIFO memory is a first-in first-out double-port buffer, i.e. the first data entering the FIFO memory is first shifted out, wherein one port is an input port of the memory, and the other port is an output port of the memory. For monolithic FIFOs, there are two main structures: a trigger guide structure and a zero guide transmission structure. The FIFO of the trigger oriented transmission structure is composed of a register array, and the FIFO of the zero oriented transmission structure is composed of a dual-port RAM with read and write address pointers.

In an embodiment of the present application, there is provided an analog-to-digital converter comprising a successive approximation analog-to-digital converter circuit based on a data weighted averaging algorithm as described in any of the embodiments of the present application.

Referring to fig. 2, clk represents a clock signal, rstn represents an inverted signal of a reset input signal, ADC _ in represents an input signal of an ADC, ADC _ temp represents a thermometer code generated after passing through a thermometer code encoding module, DWA _ select represents a selection control signal, and DWA _ output represents an output signal of a DWA algorithm.

Specifically, the output from the beginning of thermometer code coding to the final DWA can be completed in one clock signal (CLK), the accumulator performs sampling and registering on the falling edge of the clock signal to generate a control signal, sampling and registering are performed on the rising edge of the clock signal after barrel-type shifting is completed, the output from the beginning of thermometer code coding to the final DWA can be completed in one clock signal, the response speed is high, and the output can be timely processed in a subsequent circuit.

Referring to fig. 3, in an embodiment of the present application, a data weighted average algorithm is provided for controlling the actions of the analog-to-digital converter in the embodiment of the present application, and the method includes:

step S10: generating a digital signal according to the obtained analog signal;

step S20: generating a thermometer code and a shift selection control signal according to the digital signal;

step S30: and generating a data weighted average output signal according to the thermometer code and the shift selection control signal.

In one embodiment, the thermometer code and the shift selection control signal generate a shift signal through a barrel shifter and determine a shift result.

In particular, for example, in some embodiments, when the quantizer is a 2-bit quantizer, a 2 is generated by the thermometer code encoding module ² The data weighted average algorithm process is as shown in fig. 4:

ADC _ TEMP [0], ADC _ TEMP [1], ADC _ TEMP [2] and ADC _ TEMP [3] are 4-bit thermometer codes, SEL [0] and SEL [1] are 2-bit selection control signals generated after passing through the accumulator module, and DWA _ out [0], DWA _ out [1], DWA _ out [2] and DWA _ out [3] are output signals of the final DWA algorithm.

It should be understood that, although the steps in the flowchart of fig. 3 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in fig. 3 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed in turn or alternately with other steps or at least a portion of the other steps or stages.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above may be implemented by hardware instructions of a computer program, which may be stored in a non-volatile computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. Any reference to memory, storage, database or other medium used in the embodiments provided herein can include at least one of non-volatile and volatile memory. Non-volatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical storage, or the like. Volatile Memory can include Random Access Memory (RAM) or external cache Memory. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others.

In the description herein, references to the description of "some embodiments," "other embodiments," "desired embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic depictions of the above terms do not necessarily refer to the same embodiment or example.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A successive approximation analog-to-digital converter circuit based on a data weighted average algorithm, the circuit comprising:

a quantizer for generating a digital signal from an input analog signal;

and the data weighted average module is electrically connected with the quantizer and used for generating a data weighted average output signal according to the digital signal.

2. The data weighted averaging algorithm based successive approximation analog-to-digital converter circuit of claim 1, wherein the data weighted averaging module further comprises:

and the thermometer code coding module is electrically connected with the quantizer and used for generating thermometer codes according to the digital signals.

3. The successive approximation analog-to-digital converter circuit based on data weighted average algorithm of claim 2, wherein the data weighted average module further comprises:

and the accumulator is electrically connected with the quantizer and used for generating a shift selection control signal according to the digital signal.

4. The data weighted averaging algorithm based successive approximation analog-to-digital converter circuit of claim 3, wherein the data weighted averaging module further comprises:

and the barrel-shaped shifter is electrically connected with the thermometer code coding module and the accumulator and is used for generating a first output signal according to the thermometer code and the shift selection control signal.

5. The data weighted average algorithm-based successive approximation analog-to-digital converter circuit of claim 4, wherein the accumulator comprises:

the adder is electrically connected with the quantizer and is used for performing summation operation on the digital signals to generate a first shift signal;

and the first register is electrically connected with the adder and used for storing the first shifting signal and generating a shifting selection control signal.

6. The successive approximation analog-to-digital converter circuit based on data weighted average algorithm of claim 5, wherein the data weighted average module further comprises:

and the second register is electrically connected with the barrel shifter and is used for storing the first output signal to generate a data weighted average output signal.

7. The data weighted average algorithm-based successive approximation analog-to-digital converter circuit of claim 6, wherein the first register comprises a first-in-first-out register;

the second register comprises a first-in-first-out register.

8. An analog-to-digital converter comprising a successive approximation analog-to-digital converter circuit based on a data weighted average algorithm according to any of claims 1 to 7.

9. A data weighted average algorithm for controlling the analog-to-digital converter of claim 8, comprising:

generating a digital signal according to the obtained analog signal;

generating a thermometer code and a shift selection control signal according to the digital signal;

and generating a data weighted average output signal according to the thermometer code and the shift selection control signal.

10. The data weighted average algorithm of claim 9, wherein generating a data weighted average output signal based on the thermometer code and the shift select control signal comprises:

the thermometer code and the shift selection control signal generate a shift signal through a barrel shifter and determine a shift result.

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