CN114900128A

CN114900128A - Voltage controlled oscillator

Info

Publication number: CN114900128A
Application number: CN202111591870.7A
Authority: CN
Inventors: 吴炎辉; 徐振洋; 兰庶; 范麟; 张陶; 邱建波
Original assignee: Chongqing Southwest Integrated Circuit Design Co ltd
Current assignee: Chongqing Southwest Integrated Circuit Design Co ltd
Priority date: 2021-12-23
Filing date: 2021-12-23
Publication date: 2022-08-12

Abstract

The invention provides a voltage-controlled oscillator which comprises a negative resistance circuit, an inductance-capacitance resonant cavity and an output circuit. The negative resistance circuit is provided with a feedback structure, and partial noise of the negative resistance circuit circulates back and forth between the output end and the input end through the feedback structure, so that the contribution of the noise generated by the negative resistance circuit to the phase noise is effectively reduced, the optimization of the phase noise of the voltage-controlled oscillator is realized, the voltage-controlled oscillator has excellent phase noise performance, and the voltage-controlled oscillator can be widely applied to a high-performance phase-locked loop system; the negative resistance circuit is designed based on an NPN triode, and due to the excellent high-frequency transmission characteristic of the NPN triode, the loss of signals in the transmission process is smaller; meanwhile, the continuous tuning module is designed based on four variable capacitance diodes arranged back to back, and compared with the traditional variable capacitance diode connection mode, the quality factor Q value of the whole inductance-capacitance resonant cavity is improved, so that the phase noise performance of the resonant cavity is further improved.

Description

Voltage controlled oscillator

Technical Field

The invention relates to the technical field of oscillators, in particular to a voltage-controlled oscillator.

Background

The phase-locked loop can be used for providing local oscillator signals for a radio frequency transceiving system or providing clock signals for a data converter and a digital circuit, and the signal quality of the local oscillator signals or the clock signals has direct influence on key indexes in the radio frequency transceiving system and the high-speed high-precision data converter. The voltage-controlled oscillator is used as an important component of the phase-locked loop, and particularly in a narrow-loop bandwidth mode, the quality of phase noise of the voltage-controlled oscillator directly affects the closed-loop phase noise performance of the phase-locked loop. With the rapid development of wireless communication technology, higher performance requirements are placed on the phase-locked loop, which requires a voltage-controlled oscillator with lower phase noise.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, it is an object of the present invention to provide a solution for a voltage controlled oscillator for optimizing the phase noise of the voltage controlled oscillator.

To achieve the above and other related objects, the present invention provides the following technical solutions.

A voltage controlled oscillator comprising:

a negative resistance circuit providing energy to sustain oscillation;

the inductance-capacitance resonant cavity is connected with the negative resistance circuit to realize oscillation and adjust the oscillation frequency;

the output circuit is connected with the inductance-capacitance resonant cavity and outputs an oscillation signal;

wherein the negative resistance circuit has a feedback structure by which part of the noise of the negative resistance circuit cycles back and forth between the output and the input.

Optionally, the negative resistance circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NPN triode, a second NPN triode, a first resistor, and a second resistor, where a source of the first PMOS transistor is connected to a power supply voltage, a gate of the first PMOS transistor is connected to a first control signal, a drain of the first PMOS transistor is connected to a collector of the first NPN triode, a base of the first NPN triode is connected to a bias voltage through the first resistor connected in series, an emitter of the first NPN triode is connected to a source of the second PMOS transistor, a gate of the second PMOS transistor is connected to the second input end of the NPN lc resonant cavity, a collector of the second triode is connected to a collector of the first NPN triode, a base of the second NPN triode is connected to the bias voltage through the second resistor connected in series, and an emitter of the second NPN triode is connected to a source of the third PMOS transistor, and the grid electrode of the third PMOS tube is connected with the first input end of the inductance-capacitance resonant cavity.

Optionally, the negative resistance circuit further includes a first capacitor, a second capacitor, a third capacitor and a fourth capacitor, the gate of the second PMOS transistor is further connected to the base of the second NPN transistor through the first capacitor connected in series, the gate of the third PMOS transistor is further connected to the base of the first NPN transistor through the second capacitor connected in series, the gate of the third PMOS transistor is further connected to the drain of the second PMOS transistor through the third capacitor connected in series, the gate of the second PMOS transistor is further connected to the drain of the third PMOS transistor through the fourth capacitor connected in series, and the first capacitor, the second capacitor, the third capacitor, the fourth capacitor and corresponding cross-connection modes constitute the feedback structure.

Optionally, the inductor-capacitor resonant cavity includes a first inductor, a continuous tuning module, and a switch capacitor, a differential first end of the first inductor is used as a first input end of the inductor-capacitor resonant cavity, a differential second end of the first inductor is used as a second input end of the inductor-capacitor resonant cavity, a common-mode end of the first inductor is grounded, and the continuous tuning module and the switch capacitor are respectively connected in parallel with the first inductor.

Optionally, the continuous tuning module comprises a first varactor, a second varactor, a third varactor, a fourth varactor, a third resistor, and a fourth resistor, the anode of the first varactor is connected with the differential first end of the first inductor, the cathode of the first varactor is connected with the cathode of the second varactor, the anode of the second varactor is connected with the anode of the third varactor and grounded, the cathode of the third varactor is connected with the cathode of the fourth varactor, the anode of the fourth varactor is connected with the differential second end of the first inductor, one end of the third resistor is connected with the cathode of the first varactor, the other end of the third resistor is connected with a second control signal, one end of the fourth resistor is connected with the cathode of the third varactor, and the other end of the fourth resistor is connected with the second control signal.

Optionally, the switched capacitor includes a first controllable capacitor switch, a second controllable capacitor switch, a third controllable capacitor switch, a fourth controllable capacitor switch, and a fifth controllable capacitor switch, which are connected in parallel; the first controllable capacitance switch comprises a first NMOS tube, a fifth capacitor, a sixth capacitor, a fifth resistor and a sixth resistor, wherein the grid electrode of the first NMOS tube is connected with a primary inverted signal of a third control signal, the source electrode of the first NMOS tube is connected with the differential first end of the first inductor through the fifth capacitor which is connected in series, the drain electrode of the first NMOS tube is connected with the differential second end of the first inductor through the sixth capacitor which is connected in series, the source electrode of the first NMOS tube is connected with the secondary inverted signal of the third control signal through the fifth resistor which is connected in series, and the drain electrode of the first NMOS tube is connected with the secondary inverted signal of the third control signal through the sixth resistor which is connected in series.

Optionally, the second controllable capacitance switch includes a second NMOS transistor, a seventh capacitor, an eighth capacitor, a seventh resistor, and an eighth resistor, a gate of the second NMOS transistor is connected to a first inverse signal of a fourth control signal, a source of the second NMOS transistor is connected to the differential first end of the first inductor through the seventh capacitor connected in series, a drain of the second NMOS transistor is connected to the differential second end of the first inductor through the eighth capacitor connected in series, a source of the second NMOS transistor is connected to a second inverse signal of the fourth control signal through the seventh resistor connected in series, and a drain of the second NMOS transistor is connected to a second inverse signal of the fourth control signal through the eighth resistor connected in series; the third controllable capacitance switch comprises a third NMOS tube, a ninth capacitor, a tenth capacitor, a ninth resistor and a tenth resistor, wherein the grid electrode of the third NMOS tube is connected with a primary inverted signal of a fifth control signal, the source electrode of the third NMOS tube is connected with the differential first end of the first inductor through the ninth capacitor connected in series, the drain electrode of the third NMOS tube is connected with the differential second end of the first inductor through the tenth capacitor connected in series, the source electrode of the third NMOS tube is connected with the secondary inverted signal of the fifth control signal through the ninth resistor connected in series, and the drain electrode of the third NMOS tube is connected with the secondary inverted signal of the fifth control signal through the tenth resistor connected in series.

Optionally, the fourth controllable capacitance switch includes a fourth NMOS transistor, an eleventh capacitor, a twelfth capacitor, an eleventh resistor, and a twelfth resistor, a gate of the fourth NMOS transistor is connected to a first inverted signal of a sixth control signal, a source of the fourth NMOS transistor is connected to the differential first end of the first inductor through the eleventh capacitor connected in series, a drain of the fourth NMOS transistor is connected to the differential second end of the first inductor through the twelfth capacitor connected in series, a source of the fourth NMOS transistor is connected to the twice inverted signal of the sixth control signal through the eleventh resistor connected in series, and a drain of the fourth NMOS transistor is connected to the twice inverted signal of the sixth control signal through the twelfth resistor connected in series; the fifth controllable capacitance switch comprises a fifth NMOS transistor, a thirteenth capacitor, a fourteenth capacitor, a thirteenth resistor and a fourteenth resistor, wherein the grid electrode of the fifth NMOS transistor is connected with a primary inverted signal of a seventh control signal, the source electrode of the fifth NMOS transistor is connected with the differential first end of the first inductor through the thirteenth capacitor connected in series, the drain electrode of the fifth NMOS transistor is connected with the differential second end of the first inductor through the fourteenth capacitor connected in series, the source electrode of the fifth NMOS transistor is connected with a secondary inverted signal of the seventh control signal through the thirteenth resistor connected in series, and the drain electrode of the fifth NMOS transistor is connected with a secondary inverted signal of the seventh control signal through the fourteenth resistor connected in series.

Optionally, the capacitance values provided by the first controllable capacitance switch, the second controllable capacitance switch, the third controllable capacitance switch, the fourth controllable capacitance switch and the fifth controllable capacitance switch are arranged in an equal ratio array with a common ratio of 2.

Optionally, the output circuit includes a second inductor, a differential first end of the second inductor is connected to the drain of the second PMOS transistor and serves as an output positive terminal of the output circuit, a differential second end of the second inductor is connected to the drain of the third PMOS transistor and serves as an output negative terminal of the output circuit, and a common-mode terminal of the second inductor is grounded.

As described above, the voltage controlled oscillator of the present invention has at least the following advantageous effects:

the negative resistance circuit has a feedback structure, and partial noise of the negative resistance circuit circulates back and forth between the output end and the input end through the feedback structure, so that the contribution of the noise generated by the negative resistance circuit to the phase noise is effectively reduced, the optimization of the phase noise of the voltage-controlled oscillator is realized, the voltage-controlled oscillator has excellent phase noise performance, and the voltage-controlled oscillator can be widely applied to a high-performance phase-locked loop system.

Drawings

Fig. 1 shows a circuit diagram of a voltage controlled oscillator according to the present invention.

Fig. 2 is a circuit diagram of the switched capacitor of fig. 1.

Fig. 3 is a graph showing phase noise simulation of the voltage-controlled oscillator of fig. 1-2 at an oscillation frequency of 3.2 GHz.

Description of the reference numerals

1-negative resistance circuit, 2-inductance-capacitance resonant cavity, 3-output circuit, C1-first capacitor, C2-second capacitor, C3-third capacitor, C4-fourth capacitor, C4-fifth capacitor, C4-sixth capacitor, C4-seventh capacitor, C4-eighth capacitor, C4-ninth capacitor, C4-tenth capacitor, C4-eleventh capacitor, C4-twelfth capacitor, C4-thirteenth capacitor, C4-fourteenth capacitor, R4-first resistor, R4-second resistor, R4-third resistor, R4-fourth resistor, R4-fifth resistor, R4-sixth resistor, R4-seventh resistor, R4-eighth resistor, R4-ninth resistor, R4-tenth resistor, R4-fifth resistor, R4-sixth resistor, R4-seventh resistor, R4-eighth resistor, R4-ninth resistor, R4-thirteenth resistor, R4-eleventh resistor, R4-thirteenth resistor, R4-fourteenth resistor, R4-fifth resistor, R4-sixth resistor, R4-P4, P-n-P-n-P-n-type transistor, q2-a second NPN triode, N1-a first NMOS transistor, N2-a second NMOS transistor, N3-a third NMOS transistor, N4-a fourth NMOS transistor, N5-a fifth NMOS transistor, L1-a first inductor, L2-a second inductor, CV 1-a first varactor, CV 2-a second varactor, CV 3-a third varactor, CV 4-a fourth varactor, VCC-a supply voltage, Vb-a bias voltage, PD-a first control signal, VTUNE-a second control signal, CS <0> -a third control signal, CS <1> -a fourth control signal, CS <2> -a fifth control signal, CS <3> -a sixth control signal, CS <4> -a seventh control signal, 0P-a first inverse signal of CS <0>, 0N-a second inverse signal of CS <1>, P <1> -a fourth inverse control signal, CS <1> -a fourth inverse control signal, N <1> -a fourth inverse control signal, 2P-a primary inverted signal of the fifth control signal CS <2>, 2N-a secondary inverted signal of the fifth control signal CS <2>, 3P-a primary inverted signal of the sixth control signal CS <3>, 3N-a secondary inverted signal of the sixth control signal CS <3>, 4P-a primary inverted signal of the seventh control signal CS <4>, 4N-a secondary inverted signal of the seventh control signal CS <4>, tanka-a first input terminal of the LC resonant cavity 2, tankb-a second input terminal of the LC resonant cavity 2, outp-an output positive terminal of the output circuit 3, outn-an output negative terminal of the output circuit 3.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1 to 3. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated. The structures, proportions, sizes, and other dimensions shown in the drawings and described in the specification are for understanding and reading the present disclosure, and are not intended to limit the scope of the present disclosure, which is defined in the claims, and are not essential to the art, and any structural modifications, changes in proportions, or adjustments in size, which do not affect the efficacy and attainment of the same are intended to fall within the scope of the present disclosure.

As shown in fig. 1, the present invention provides a voltage controlled oscillator, which includes:

a negative resistance circuit 1 that supplies energy to maintain oscillation;

the inductance-capacitance resonant cavity 2 is connected with the negative resistance circuit 1 to realize oscillation and adjust the oscillation frequency;

the output circuit 3 is connected with the inductance-capacitance resonant cavity 2 and outputs an oscillation signal;

the negative resistance circuit 1 has a feedback structure, and part of noise of the negative resistance circuit 1 circulates back and forth between the output terminal and the input terminal through the feedback structure.

In detail, as shown in fig. 1, the negative resistance circuit 1 includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a first NPN transistor Q1, a second NPN transistor Q2, a first resistor R1 and a second resistor R2, a source of the first PMOS transistor P1 is connected to the power voltage VCC, a gate of the first PMOS transistor P1 is connected to the first control signal PD, a drain of the first PMOS transistor P1 is connected to a collector of the first NPN transistor Q1, a base of the first NPN transistor Q1 is connected to the bias voltage Vb via the first resistor R1 in series, an emitter of the first NPN transistor Q1 is connected to the source of the second PMOS transistor P2, a gate of the second PMOS transistor P2 is connected to the second input terminal tankb of the resonant cavity 2, a collector of the second NPN transistor Q2 is connected to the collector of the first NPN transistor Q1, a base of the second PMOS transistor Q53 is connected to the emitter of the second NPN transistor Q2 in series, and then connected to the emitter of the second transistor P2, the gate of the third PMOS transistor P3 is connected to the first input terminal tanka of the lc-resonant cavity 2.

In detail, as shown in fig. 1, the negative resistance circuit 1 further includes a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4, a gate of the second PMOS transistor P2 is further connected to a base of the second NPN triode Q2 through the first capacitor C1 connected in series, a gate of the third PMOS transistor P3 is further connected to a base of the first NPN triode Q1 through the second capacitor C2 connected in series, a gate of the third PMOS transistor P3 is further connected to a drain of the second PMOS transistor P2 through the third capacitor C3 connected in series, a gate of the second PMOS transistor P2 is further connected to a drain of the third PMOS transistor P3 through the fourth capacitor C4 connected in series, and the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4 and corresponding cross-connection modes form a feedback structure.

In more detail, as shown in fig. 1, in the negative resistance circuit, the source of the second PMOS transistor P2 is connected in series with the first NPN transistor Q1, the source of the third PMOS transistor P3 is connected in series with the second NPN transistor Q2, in a feedback structure formed by a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4 and corresponding cross connection modes, only part of noise generated by a second PMOS tube P2, a third PMOS tube P3, a first NPN triode Q1 and a second NPN triode Q2 is injected into a subsequent inductance-capacitance resonant cavity 2, the noise injected into the inductance-capacitance resonant cavity 2 contributes to phase noise, and the other part of the noise circulates back and forth between the second PMOS tube P2 and the first NPN triode Q1 (or between the third PMOS tube P3 and the second NPN triode Q2) through a feedback structure. Meanwhile, due to the excellent high-frequency transmission characteristic of the NPN triode, the loss of the signal in the transmission process is smaller.

In detail, as shown in fig. 1, the lc resonant cavity 2 includes a first inductor L1, a continuous tuning module, and a switched capacitor, a differential first end of the first inductor L1 is used as a first input end tanka of the lc resonant cavity 2, a differential second end of the first inductor L1 is used as a second input end tankb of the lc resonant cavity 2, a common-mode end of the first inductor L1 is grounded, and the continuous tuning module and the switched capacitor are respectively connected in parallel with the first inductor L1.

In detail, as shown in fig. 1, the continuous tuning block comprises a first varactor CV1, a second varactor CV2, a third varactor CV3, a fourth varactor CV4, a third resistor R3 and a fourth resistor R4, wherein the anode of the first varactor CV1 is connected to the differential first end of the first inductor L1, the cathode of the first varactor CV1 is connected to the cathode of the second varactor CV2, the anode of the second varactor CV2 is connected to the anode of the third varactor CV3 and grounded, the cathode of the third varactor CV3 is connected to the cathode of the fourth varactor CV4, the anode of the fourth varactor CV4 is connected to the differential second end of the first inductor L1, one end of the third resistor R3 is connected to the cathode of the first varactor CV1, the other end of the third resistor R3 is connected to the second control signal VTUNE, one end of the fourth resistor R4 is connected to the cathode of the third varactor CV3, and the other end of the fourth resistor R4 is connected to the second control signal VTUNE.

In detail, as shown in fig. 2, the switched capacitor includes a first controllable capacitor switch, a second controllable capacitor switch, a third controllable capacitor switch, a fourth controllable capacitor switch and a fifth controllable capacitor switch, which are arranged in parallel, the parallel connection lines are respectively two input ends tanka and tankb of the inductor-capacitor resonant cavity 2, and the circuit structures of the first controllable capacitor switch, the second controllable capacitor switch, the third controllable capacitor switch, the fourth controllable capacitor switch and the fifth controllable capacitor switch are the same. The on-off of the first controllable capacitance switch, the second controllable capacitance switch, the third controllable capacitance switch, the fourth controllable capacitance switch and the fifth controllable capacitance switch are controlled by the input control signal CS <4:0>, so that whether the capacitance is selected or not is realized.

More specifically, as shown in fig. 2, the first controllable capacitance switch includes a first NMOS transistor N1, a fifth capacitor C5, a sixth capacitor C6, a fifth resistor R5 and a sixth resistor R6, a gate of the first NMOS transistor N1 is connected to a first inverted signal 0P of a third control signal CS <0>, a source of the first NMOS transistor N1 is connected to a differential first end of the first inductor L1 through the series-connected fifth capacitor C5, a drain of the first NMOS transistor N1 is connected to a differential second end of the first inductor L1 through the series-connected sixth capacitor C6, a source of the first NMOS transistor N1 is further connected to a second inverted signal 0N of the third control signal CS <0> through the series-connected fifth resistor R5, and a drain of the first NMOS transistor N1 is further connected to a second inverted signal 0N of the third control signal CS <0> through the series-connected sixth resistor R6.

More specifically, as shown in fig. 2, the second controllable capacitance switch includes a second NMOS transistor N2, a seventh capacitor C7, an eighth capacitor C8, a seventh resistor R7 and an eighth resistor R8, a gate of the second NMOS transistor N2 is connected to a first inverted signal 1P of the fourth control signal CS <1>, a source of the second NMOS transistor N2 is connected to the differential first end of the first inductor L1 through the seventh capacitor C7, a drain of the second NMOS transistor N2 is connected to the differential second end of the first inductor L1 through the eighth capacitor C8, a source of the second NMOS transistor N2 is further connected to a second inverted signal 1N of the fourth control signal CS <1> through the seventh resistor R7, and a drain of the second NMOS transistor N2 is further connected to the second inverted signal 1N of the fourth control signal CS <1> through the eighth resistor R8.

More specifically, as shown in fig. 2, the third controllable capacitance switch includes a third NMOS transistor N3, a ninth capacitor C9, a tenth capacitor C10, a ninth resistor R9 and a tenth resistor R10, a gate of the third NMOS transistor N3 is connected to the first inverted signal 2P of the fifth control signal CS <2>, a source of the third NMOS transistor N3 is connected to the differential first end of the first inductor L1 through the serially connected ninth capacitor C9, a drain of the third NMOS transistor N3 is connected to the differential second end of the first inductor L1 through the serially connected tenth capacitor C10, a source of the third NMOS transistor N3 is further connected to the second inverted signal 2N of the fifth control signal CS <2> through the serially connected ninth resistor R9, and a drain of the third NMOS transistor N3 is further connected to the second inverted signal 2N of the fifth control signal CS <2> through the serially connected tenth resistor R10.

More specifically, as shown in fig. 2, the fourth controllable capacitance switch includes a fourth NMOS transistor N4, an eleventh capacitor C11, a twelfth capacitor C12, an eleventh resistor R11 and a twelfth resistor R12, a gate of the fourth NMOS transistor N4 is connected to the first inverted signal 3P of the sixth control signal CS <3>, a source of the fourth NMOS transistor N4 is connected to the differential first end of the first inductor L1 through the serially connected eleventh capacitor C11, a drain of the fourth NMOS transistor N4 is connected to the differential second end of the first inductor L1 through the serially connected twelfth capacitor C12, a source of the fourth NMOS transistor N4 is further connected to the second inverted signal 3N of the sixth control signal CS <3> through the serially connected eleventh resistor R11, and a drain of the fourth NMOS transistor N4 is further connected to the second inverted signal 3N of the sixth control signal CS <3> through the serially connected twelfth resistor R12.

More specifically, as shown in fig. 2, the fifth controllable capacitance switch includes a fifth NMOS transistor N5, a thirteenth capacitor C13, a fourteenth capacitor C14, a thirteenth resistor R13 and a fourteenth resistor R14, a gate of the fifth NMOS transistor N5 is connected to the first inverted signal 4P of the seventh control signal CS <4>, a source of the fifth NMOS transistor N5 is connected to the differential first end of the first inductor L1 through the thirteenth capacitor C13, a drain of the fifth NMOS transistor N5 is connected to the differential second end of the first inductor L1 through the fourteenth capacitor C14, a source of the fifth NMOS transistor N5 is further connected to the second inverted signal 4N of the seventh control signal CS <4> through the thirteenth resistor R13, and a drain of the fifth NMOS transistor N5 is further connected to the second inverted signal 4N of the seventh control signal CS <4> through the fourteenth resistor R14.

In an optional embodiment of the present invention, the capacitance values provided by the first controllable capacitance switch, the second controllable capacitance switch, the third controllable capacitance switch, the fourth controllable capacitance switch and the fifth controllable capacitance switch are arranged in an equal ratio sequence with 2 as a common ratio, for example, the capacitance values of the fifth capacitor C5 and the sixth capacitor C6 are both C0, the capacitance values of the seventh capacitor C7 and the eighth capacitor C8 are 2C0, the capacitance values of the ninth capacitor C9 and the tenth capacitor C10 are 4C0, the capacitance values of the eleventh capacitor C11 and the twelfth capacitor C12 are 8C0, the capacitance values of the thirteenth capacitor C13 and the fourteenth capacitor C14 are 16C0, and the capacitance values of the third control signal CS <0>, the fourth control signal CS <1>, the fifth control signal CS <2>, the sixth control signal CS <3> and the seventh control signal CS <4> are used to change the capacitance value of the capacitance switch, the capacitance value and the first inductor L1 form a basic resonant cavity, oscillation is realized, and the oscillation frequency can be roughly adjusted by changing the size of the switch capacitance value.

More specifically, as shown in fig. 1, based on the coarse adjustment of the oscillation frequency based on the switched capacitor, the frequency tuning curve of the continuous tuning module is adjusted and controlled by the second control signal VTUNE, so as to achieve the fine adjustment of the oscillation frequency. It should be noted that, the continuous tuning module is designed based on four varactor diodes arranged back to back, and compared with the traditional varactor diode connection mode, the quality factor Q value of the whole inductance-capacitance resonant cavity 2 is improved, so that the phase noise performance is improved.

In detail, as shown in fig. 1, the output circuit 3 includes a second inductor L2, a differential first end of the second inductor L2 is connected to the drain of the second PMOS transistor P2 and serves as an output positive terminal outp of the output circuit 3, a differential second end of the second inductor L2 is connected to the drain of the third PMOS transistor P3 and serves as an output negative terminal outn of the output circuit 3, and a common mode terminal of the second inductor L2 is grounded.

A simulation experiment is performed on the voltage-controlled oscillator shown in fig. 1-2, and a 3.2GHz oscillation frequency phase noise curve is shown in fig. 3: as can be seen from FIG. 3, at frequency offset 100kHz, a phase noise of-120.292 dBc/Hz is achieved, with very low phase noise characteristics.

The simulation experiment result shows that: the voltage-controlled oscillator provided by the invention has excellent phase noise performance and can be applied to a radio frequency phase-locked loop system with high performance requirement.

In summary, in the voltage-controlled oscillator provided by the present invention, the negative resistance circuit has a feedback structure, and through the feedback structure, part of the noise of the negative resistance circuit circulates back and forth between the output end and the input end, so that the contribution of the noise generated by the negative resistance circuit to the phase noise is effectively reduced, the optimization of the phase noise of the voltage-controlled oscillator is realized, the voltage-controlled oscillator has excellent phase noise performance, and the voltage-controlled oscillator can be widely applied to a high-performance phase-locked loop system; the negative resistance circuit is designed based on an NPN triode, and due to the excellent high-frequency transmission characteristic of the NPN triode, the loss of signals in the transmission process is smaller; meanwhile, the continuous tuning module is designed based on four variable capacitance diodes arranged back to back, and compared with the traditional variable capacitance diode connection mode, the quality factor Q value of the whole inductance-capacitance resonant cavity is improved, so that the phase noise performance of the resonant cavity is further improved.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims

1. A voltage controlled oscillator, comprising:

a negative resistance circuit providing energy to sustain oscillation;

2. The voltage-controlled oscillator according to claim 1, wherein the negative resistance circuit comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NPN transistor, a second NPN transistor, a first resistor, and a second resistor, a source of the first PMOS transistor is connected to a power voltage, a gate of the first PMOS transistor is connected to a first control signal, a drain of the first PMOS transistor is connected to a collector of the first NPN transistor, a base of the first NPN transistor is connected to a bias voltage through the first resistor in series, an emitter of the first NPN transistor is connected to a source of the second PMOS transistor, a gate of the second PMOS transistor is connected to the second input terminal of the lc resonator, a collector of the second NPN transistor is connected to a collector of the first NPN transistor, a base of the second NPN transistor is connected to the bias voltage through the second resistor in series, an emitter of the second NPN triode is connected with a source of the third PMOS tube, and a grid of the third PMOS tube is connected with a first input end of the inductance-capacitance resonant cavity.

3. The vco of claim 2, wherein the negative resistance circuit further comprises a first capacitor, a second capacitor, a third capacitor and a fourth capacitor, the gate of the second PMOS transistor is further connected to the base of the second NPN transistor through the first capacitor connected in series, the gate of the third PMOS transistor is further connected to the base of the first NPN transistor through the second capacitor connected in series, the gate of the third PMOS transistor is further connected to the drain of the second PMOS transistor through the third capacitor connected in series, the gate of the second PMOS transistor is further connected to the drain of the third PMOS transistor through the fourth capacitor connected in series, and the first capacitor, the second capacitor, the third capacitor, the fourth capacitor and corresponding cross-connections form the feedback structure.

4. The VCO according to claim 1 or 3, wherein said LC resonator comprises a first inductor, a continuous tuning module, and a switched capacitor, a differential first terminal of said first inductor is used as a first input terminal of said LC resonator, a differential second terminal of said first inductor is used as a second input terminal of said LC resonator, a common mode terminal of said first inductor is grounded, and said continuous tuning module and said switched capacitor are respectively disposed in parallel with said first inductor.

5. The VCO according to claim 4, wherein said continuous tuning module comprises a first varactor, a second varactor, a third varactor, a fourth varactor, a third resistor, and a fourth resistor, wherein an anode of said first varactor is connected to a differential first end of said first inductor, a cathode of said first varactor is connected to a cathode of said second varactor, an anode of said second varactor is connected to an anode of said third varactor and grounded, a cathode of said third varactor is connected to a cathode of said fourth varactor, an anode of said fourth varactor is connected to a differential second end of said first inductor, one end of said third resistor is connected to a cathode of said first varactor, the other end of said third resistor is connected to a second control signal, and one end of said fourth resistor is connected to a cathode of said third varactor, the other end of the fourth resistor is connected with the second control signal.

6. The voltage controlled oscillator according to claim 5, wherein the switched capacitors comprise a first controllable capacitor switch, a second controllable capacitor switch, a third controllable capacitor switch, a fourth controllable capacitor switch and a fifth controllable capacitor switch arranged in parallel; the first controllable capacitance switch comprises a first NMOS tube, a fifth capacitor, a sixth capacitor, a fifth resistor and a sixth resistor, wherein the grid electrode of the first NMOS tube is connected with a primary inverted signal of a third control signal, the source electrode of the first NMOS tube is connected with the differential first end of the first inductor through the fifth capacitor which is connected in series, the drain electrode of the first NMOS tube is connected with the differential second end of the first inductor through the sixth capacitor which is connected in series, the source electrode of the first NMOS tube is connected with the secondary inverted signal of the third control signal through the fifth resistor which is connected in series, and the drain electrode of the first NMOS tube is connected with the secondary inverted signal of the third control signal through the sixth resistor which is connected in series.

7. The VCO according to claim 6, wherein said second controllable capacitor switch comprises a second NMOS transistor, a seventh capacitor, an eighth capacitor, a seventh resistor and an eighth resistor, a gate of said second NMOS transistor is connected to a first inverted signal of a fourth control signal, a source of said second NMOS transistor is connected to a differential first terminal of said first inductor through said seventh capacitor connected in series, a drain of said second NMOS transistor is connected to a differential second terminal of said first inductor through said eighth capacitor connected in series, a source of said second NMOS transistor is connected to a second inverted signal of said fourth control signal through said seventh resistor connected in series, and a drain of said second NMOS transistor is connected to a second inverted signal of said fourth control signal through said eighth resistor connected in series; the third controllable capacitance switch comprises a third NMOS tube, a ninth capacitor, a tenth capacitor, a ninth resistor and a tenth resistor, wherein the grid electrode of the third NMOS tube is connected with a primary inverted signal of a fifth control signal, the source electrode of the third NMOS tube is connected with the differential first end of the first inductor through the ninth capacitor connected in series, the drain electrode of the third NMOS tube is connected with the differential second end of the first inductor through the tenth capacitor connected in series, the source electrode of the third NMOS tube is connected with the secondary inverted signal of the fifth control signal through the ninth resistor connected in series, and the drain electrode of the third NMOS tube is connected with the secondary inverted signal of the fifth control signal through the tenth resistor connected in series.

8. The VCO according to claim 7, wherein the fourth controllable capacitor switch comprises a fourth NMOS transistor, an eleventh capacitor, a twelfth capacitor, an eleventh resistor, and a twelfth resistor, a gate of the fourth NMOS transistor is connected to a first inverted signal of a sixth control signal, a source of the fourth NMOS transistor is connected to a differential first terminal of the first inductor through the eleventh capacitor connected in series, a drain of the fourth NMOS transistor is connected to a differential second terminal of the first inductor through the twelfth capacitor connected in series, a source of the fourth NMOS transistor is further connected to a second inverted signal of the sixth control signal through the eleventh resistor connected in series, and a drain of the fourth NMOS transistor is further connected to a second inverted signal of the sixth control signal through the twelfth resistor connected in series; the fifth controllable capacitance switch comprises a fifth NMOS transistor, a thirteenth capacitor, a fourteenth capacitor, a thirteenth resistor and a fourteenth resistor, wherein the grid electrode of the fifth NMOS transistor is connected with a primary inverted signal of a seventh control signal, the source electrode of the fifth NMOS transistor is connected with the differential first end of the first inductor through the thirteenth capacitor connected in series, the drain electrode of the fifth NMOS transistor is connected with the differential second end of the first inductor through the fourteenth capacitor connected in series, the source electrode of the fifth NMOS transistor is connected with a secondary inverted signal of the seventh control signal through the thirteenth resistor connected in series, and the drain electrode of the fifth NMOS transistor is connected with a secondary inverted signal of the seventh control signal through the fourteenth resistor connected in series.

9. The vco of claim 8, wherein the first, second, third, fourth, and fifth rcc controls provide capacitance values in an equal ratio sequence with a common ratio of 2.

10. The vco of claim 9, wherein the output circuit comprises a second inductor, a differential first end of the second inductor is connected to the drain of the second PMOS transistor and serves as a positive output terminal of the output circuit, a differential second end of the second inductor is connected to the drain of the third PMOS transistor and serves as a negative output terminal of the output circuit, and a common-mode terminal of the second inductor is grounded.